2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "pipe/p_shader_tokens.h"
34 #include "util/u_memory.h"
35 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
38 #include "tgsi/tgsi_dump.h"
39 #include "tgsi/tgsi_info.h"
41 #include "brw_context.h"
43 #include "brw_debug.h"
44 #include "brw_disasm.h"
46 /* Choose one of the 4 vec4's which can be packed into each 16-wide reg.
48 static INLINE
struct brw_reg
brw_vec4_grf_repeat( GLuint reg
, GLuint slot
)
50 int nr
= reg
+ slot
/2;
51 int subnr
= (slot
%2) * 4;
53 return stride(brw_vec4_grf(nr
, subnr
), 0, 4, 1);
57 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
59 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
61 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
62 c
->prog_data
.total_grf
= c
->last_tmp
;
67 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
69 if (tmp
.nr
== c
->last_tmp
-1)
73 static void release_tmps( struct brw_vs_compile
*c
)
75 c
->last_tmp
= c
->first_tmp
;
79 static boolean
is_position_output( struct brw_vs_compile
*c
,
82 const struct brw_vertex_shader
*vs
= c
->vp
;
83 unsigned semantic
= vs
->info
.output_semantic_name
[vs_output
];
84 unsigned index
= vs
->info
.output_semantic_index
[vs_output
];
86 return (semantic
== TGSI_SEMANTIC_POSITION
&&
91 static boolean
find_output_slot( struct brw_vs_compile
*c
,
93 unsigned *fs_input_slot
)
95 const struct brw_vertex_shader
*vs
= c
->vp
;
96 unsigned semantic
= vs
->info
.output_semantic_name
[vs_output
];
97 unsigned index
= vs
->info
.output_semantic_index
[vs_output
];
100 for (i
= 0; i
< c
->key
.fs_signature
.nr_inputs
; i
++) {
101 if (c
->key
.fs_signature
.input
[i
].semantic
== semantic
&&
102 c
->key
.fs_signature
.input
[i
].semantic_index
== index
) {
113 * Preallocate GRF register before code emit.
114 * Do things as simply as possible. Allocate and populate all regs
117 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
119 struct brw_context
*brw
= c
->func
.brw
;
120 GLuint i
, reg
= 0, subreg
= 0, mrf
;
121 int attributes_in_vue
;
123 /* Determine whether to use a real constant buffer or use a block
124 * of GRF registers for constants. The later is faster but only
125 * works if everything fits in the GRF.
126 * XXX this heuristic/check may need some fine tuning...
128 if (c
->vp
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1 +
129 c
->vp
->info
.file_max
[TGSI_FILE_IMMEDIATE
] + 1 +
130 c
->vp
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1 + 21 > BRW_MAX_GRF
)
131 c
->vp
->use_const_buffer
= GL_TRUE
;
133 /* XXX: immediates can go elsewhere if necessary:
135 assert(c
->vp
->info
.file_max
[TGSI_FILE_IMMEDIATE
] + 1 +
136 c
->vp
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1 + 21 <= BRW_MAX_GRF
);
138 c
->vp
->use_const_buffer
= GL_FALSE
;
141 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
143 /* r0 -- reserved as usual
145 c
->r0
= brw_vec8_grf(reg
, 0);
148 /* User clip planes from curbe:
150 if (c
->key
.nr_userclip
) {
151 /* Skip over fixed planes: Or never read them into vs unit?
155 for (i
= 0; i
< c
->key
.nr_userclip
; i
++, subreg
++) {
157 stride( brw_vec4_grf(reg
+subreg
/2, (subreg
%2) * 4), 0, 4, 1);
160 /* Deal with curbe alignment:
162 subreg
= align(subreg
, 2);
163 /*reg += ((6 + c->key.nr_userclip + 3) / 4) * 2;*/
167 /* Immediates: always in the curbe.
169 * XXX: Can try to encode some immediates as brw immediates
170 * XXX: Make sure ureg sets minimal immediate size and respect it
173 for (i
= 0; i
< c
->vp
->info
.immediate_count
; i
++, subreg
++) {
174 c
->regs
[TGSI_FILE_IMMEDIATE
][i
] =
175 stride( brw_vec4_grf(reg
+subreg
/2, (subreg
%2) * 4), 0, 4, 1);
177 c
->prog_data
.nr_params
= c
->vp
->info
.immediate_count
* 4;
180 /* Vertex constant buffer.
182 * Constants from the buffer can be either cached in the curbe or
183 * loaded as needed from the actual constant buffer.
185 if (!c
->vp
->use_const_buffer
) {
186 GLuint nr_params
= c
->vp
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
188 for (i
= 0; i
< nr_params
; i
++, subreg
++) {
189 c
->regs
[TGSI_FILE_CONSTANT
][i
] =
190 stride( brw_vec4_grf(reg
+subreg
/2, (subreg
%2) * 4), 0, 4, 1);
193 c
->prog_data
.nr_params
+= nr_params
* 4;
196 /* All regs allocated
198 reg
+= (subreg
+ 1) / 2;
199 c
->prog_data
.curb_read_length
= reg
- 1;
202 /* Allocate input regs:
204 c
->nr_inputs
= c
->vp
->info
.num_inputs
;
205 for (i
= 0; i
< c
->nr_inputs
; i
++) {
206 c
->regs
[TGSI_FILE_INPUT
][i
] = brw_vec8_grf(reg
, 0);
210 /* If there are no inputs, we'll still be reading one attribute's worth
211 * because it's required -- see urb_read_length setting.
213 if (c
->nr_inputs
== 0)
218 /* Allocate outputs. The non-position outputs go straight into message regs.
220 c
->nr_outputs
= c
->prog_data
.nr_outputs
;
228 if (c
->key
.fs_signature
.nr_inputs
> BRW_MAX_MRF
) {
229 c
->overflow_grf_start
= reg
;
230 c
->overflow_count
= c
->key
.fs_signature
.nr_inputs
- BRW_MAX_MRF
;
231 reg
+= c
->overflow_count
;
234 /* XXX: need to access vertex output semantics here:
236 for (i
= 0; i
< c
->nr_outputs
; i
++) {
239 /* XXX: Put output position in slot zero always. Clipper, etc,
240 * need access to this reg.
242 if (is_position_output(c
, i
)) {
243 c
->regs
[TGSI_FILE_OUTPUT
][i
] = brw_vec8_grf(reg
, 0); /* copy to mrf 0 */
246 else if (find_output_slot(c
, i
, &slot
)) {
248 if (0 /* is_psize_output(c, i) */ ) {
249 /* c->psize_out.grf = reg; */
250 /* c->psize_out.mrf = i; */
253 /* The first (16-4) outputs can go straight into the message regs.
255 if (slot
+ mrf
< BRW_MAX_MRF
) {
256 c
->regs
[TGSI_FILE_OUTPUT
][i
] = brw_message_reg(slot
+ mrf
);
259 int grf
= c
->overflow_grf_start
+ slot
- BRW_MAX_MRF
;
260 c
->regs
[TGSI_FILE_OUTPUT
][i
] = brw_vec8_grf(grf
, 0);
264 c
->regs
[TGSI_FILE_OUTPUT
][i
] = brw_null_reg();
268 /* Allocate program temporaries:
271 for (i
= 0; i
< c
->vp
->info
.file_max
[TGSI_FILE_TEMPORARY
]+1; i
++) {
272 c
->regs
[TGSI_FILE_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
276 /* Address reg(s). Don't try to use the internal address reg until
279 for (i
= 0; i
< c
->vp
->info
.file_max
[TGSI_FILE_ADDRESS
]+1; i
++) {
280 c
->regs
[TGSI_FILE_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
284 BRW_VERTICAL_STRIDE_8
,
286 BRW_HORIZONTAL_STRIDE_1
,
292 if (c
->vp
->use_const_buffer
) {
293 for (i
= 0; i
< 3; i
++) {
294 c
->current_const
[i
].index
= -1;
295 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
301 for (i
= 0; i
< 128; i
++) {
302 if (c
->output_regs
[i
].used_in_src
) {
303 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
309 if (c
->vp
->has_flow_control
) {
310 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
314 /* Some opcodes need an internal temporary:
317 c
->last_tmp
= reg
; /* for allocation purposes */
319 /* Each input reg holds data from two vertices. The
320 * urb_read_length is the number of registers read from *each*
321 * vertex urb, so is half the amount:
323 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
325 /* Setting this field to 0 leads to undefined behavior according to the
326 * the VS_STATE docs. Our VUEs will always have at least one attribute
327 * sitting in them, even if it's padding.
329 if (c
->prog_data
.urb_read_length
== 0)
330 c
->prog_data
.urb_read_length
= 1;
332 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
333 * them to fit the biggest thing they need to.
335 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
338 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
340 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
342 c
->prog_data
.total_grf
= reg
;
344 if (BRW_DEBUG
& DEBUG_VS
) {
345 debug_printf("%s NumAddrRegs %d\n", __FUNCTION__
,
346 c
->vp
->info
.file_max
[TGSI_FILE_ADDRESS
]+1);
347 debug_printf("%s NumTemps %d\n", __FUNCTION__
,
348 c
->vp
->info
.file_max
[TGSI_FILE_TEMPORARY
]+1);
349 debug_printf("%s reg = %d\n", __FUNCTION__
, reg
);
355 * If an instruction uses a temp reg both as a src and the dest, we
356 * sometimes need to allocate an intermediate temporary.
358 static void unalias1( struct brw_vs_compile
*c
,
361 void (*func
)( struct brw_vs_compile
*,
365 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
366 struct brw_compile
*p
= &c
->func
;
367 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
369 brw_MOV(p
, dst
, tmp
);
379 * Checkes if 2-operand instruction needs an intermediate temporary.
381 static void unalias2( struct brw_vs_compile
*c
,
385 void (*func
)( struct brw_vs_compile
*,
390 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
391 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
392 struct brw_compile
*p
= &c
->func
;
393 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
394 func(c
, tmp
, arg0
, arg1
);
395 brw_MOV(p
, dst
, tmp
);
399 func(c
, dst
, arg0
, arg1
);
405 * Checkes if 3-operand instruction needs an intermediate temporary.
407 static void unalias3( struct brw_vs_compile
*c
,
412 void (*func
)( struct brw_vs_compile
*,
418 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
419 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
420 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
421 struct brw_compile
*p
= &c
->func
;
422 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
423 func(c
, tmp
, arg0
, arg1
, arg2
);
424 brw_MOV(p
, dst
, tmp
);
428 func(c
, dst
, arg0
, arg1
, arg2
);
432 static void emit_sop( struct brw_compile
*p
,
438 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
439 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
440 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
441 brw_set_predicate_control_flag_value(p
, 0xff);
444 static void emit_seq( struct brw_compile
*p
,
447 struct brw_reg arg1
)
449 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
452 static void emit_sne( struct brw_compile
*p
,
455 struct brw_reg arg1
)
457 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
459 static void emit_slt( struct brw_compile
*p
,
462 struct brw_reg arg1
)
464 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
467 static void emit_sle( struct brw_compile
*p
,
470 struct brw_reg arg1
)
472 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
475 static void emit_sgt( struct brw_compile
*p
,
478 struct brw_reg arg1
)
480 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
483 static void emit_sge( struct brw_compile
*p
,
486 struct brw_reg arg1
)
488 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
491 static void emit_max( struct brw_compile
*p
,
494 struct brw_reg arg1
)
496 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
497 brw_SEL(p
, dst
, arg1
, arg0
);
498 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
501 static void emit_min( struct brw_compile
*p
,
504 struct brw_reg arg1
)
506 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
507 brw_SEL(p
, dst
, arg0
, arg1
);
508 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
512 static void emit_math1( struct brw_vs_compile
*c
,
518 /* There are various odd behaviours with SEND on the simulator. In
519 * addition there are documented issues with the fact that the GEN4
520 * processor doesn't do dependency control properly on SEND
521 * results. So, on balance, this kludge to get around failures
522 * with writemasked math results looks like it might be necessary
523 * whether that turns out to be a simulator bug or not:
525 struct brw_compile
*p
= &c
->func
;
526 struct brw_reg tmp
= dst
;
527 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
528 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
536 BRW_MATH_SATURATE_NONE
,
539 BRW_MATH_DATA_SCALAR
,
543 brw_MOV(p
, dst
, tmp
);
549 static void emit_math2( struct brw_vs_compile
*c
,
556 struct brw_compile
*p
= &c
->func
;
557 struct brw_reg tmp
= dst
;
558 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
559 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
564 brw_MOV(p
, brw_message_reg(3), arg1
);
569 BRW_MATH_SATURATE_NONE
,
572 BRW_MATH_DATA_SCALAR
,
576 brw_MOV(p
, dst
, tmp
);
582 static void emit_exp_noalias( struct brw_vs_compile
*c
,
584 struct brw_reg arg0
)
586 struct brw_compile
*p
= &c
->func
;
589 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_X
) {
590 struct brw_reg tmp
= get_tmp(c
);
591 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
593 /* tmp_d = floor(arg0.x) */
594 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
596 /* result[0] = 2.0 ^ tmp */
598 /* Adjust exponent for floating point:
601 brw_ADD(p
, brw_writemask(tmp_d
, BRW_WRITEMASK_X
), tmp_d
, brw_imm_d(127));
603 /* Install exponent and sign.
604 * Excess drops off the edge:
606 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), BRW_WRITEMASK_X
),
607 tmp_d
, brw_imm_d(23));
612 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_Y
) {
613 /* result[1] = arg0.x - floor(arg0.x) */
614 brw_FRC(p
, brw_writemask(dst
, BRW_WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
617 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_Z
) {
618 /* As with the LOG instruction, we might be better off just
619 * doing a taylor expansion here, seeing as we have to do all
622 * If mathbox partial precision is too low, consider also:
623 * result[3] = result[0] * EXP(result[1])
626 BRW_MATH_FUNCTION_EXP
,
627 brw_writemask(dst
, BRW_WRITEMASK_Z
),
628 brw_swizzle1(arg0
, 0),
629 BRW_MATH_PRECISION_FULL
);
632 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_W
) {
633 /* result[3] = 1.0; */
634 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_W
), brw_imm_f(1));
639 static void emit_log_noalias( struct brw_vs_compile
*c
,
641 struct brw_reg arg0
)
643 struct brw_compile
*p
= &c
->func
;
644 struct brw_reg tmp
= dst
;
645 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
646 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
647 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
648 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
652 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
655 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
658 * These almost look likey they could be joined up, but not really
661 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
662 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
664 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_XZ
) {
666 brw_writemask(tmp_ud
, BRW_WRITEMASK_X
),
667 brw_swizzle1(arg0_ud
, 0),
668 brw_imm_ud((1U<<31)-1));
671 brw_writemask(tmp_ud
, BRW_WRITEMASK_X
),
676 brw_writemask(tmp
, BRW_WRITEMASK_X
),
677 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
681 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_YZ
) {
683 brw_writemask(tmp_ud
, BRW_WRITEMASK_Y
),
684 brw_swizzle1(arg0_ud
, 0),
685 brw_imm_ud((1<<23)-1));
688 brw_writemask(tmp_ud
, BRW_WRITEMASK_Y
),
690 brw_imm_ud(127<<23));
693 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_Z
) {
694 /* result[2] = result[0] + LOG2(result[1]); */
696 /* Why bother? The above is just a hint how to do this with a
697 * taylor series. Maybe we *should* use a taylor series as by
698 * the time all the above has been done it's almost certainly
699 * quicker than calling the mathbox, even with low precision.
702 * - result[0] + mathbox.LOG2(result[1])
703 * - mathbox.LOG2(arg0.x)
704 * - result[0] + inline_taylor_approx(result[1])
707 BRW_MATH_FUNCTION_LOG
,
708 brw_writemask(tmp
, BRW_WRITEMASK_Z
),
709 brw_swizzle1(tmp
, 1),
710 BRW_MATH_PRECISION_FULL
);
713 brw_writemask(tmp
, BRW_WRITEMASK_Z
),
714 brw_swizzle1(tmp
, 2),
715 brw_swizzle1(tmp
, 0));
718 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_W
) {
719 /* result[3] = 1.0; */
720 brw_MOV(p
, brw_writemask(tmp
, BRW_WRITEMASK_W
), brw_imm_f(1));
724 brw_MOV(p
, dst
, tmp
);
730 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
732 static void emit_dst_noalias( struct brw_vs_compile
*c
,
737 struct brw_compile
*p
= &c
->func
;
739 /* There must be a better way to do this:
741 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_X
)
742 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_X
), brw_imm_f(1.0));
743 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_Y
)
744 brw_MUL(p
, brw_writemask(dst
, BRW_WRITEMASK_Y
), arg0
, arg1
);
745 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_Z
)
746 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_Z
), arg0
);
747 if (dst
.dw1
.bits
.writemask
& BRW_WRITEMASK_W
)
748 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_W
), arg1
);
752 static void emit_xpd( struct brw_compile
*p
,
757 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
758 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
762 static void emit_lit_noalias( struct brw_vs_compile
*c
,
764 struct brw_reg arg0
)
766 struct brw_compile
*p
= &c
->func
;
767 struct brw_instruction
*if_insn
;
768 struct brw_reg tmp
= dst
;
769 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
774 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_YZ
), brw_imm_f(0));
775 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_XW
), brw_imm_f(1));
777 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
778 * to get all channels active inside the IF. In the clipping code
779 * we run with NoMask, so it's not an option and we can use
780 * BRW_EXECUTE_1 for all comparisions.
782 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
783 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
785 brw_MOV(p
, brw_writemask(dst
, BRW_WRITEMASK_Y
), brw_swizzle1(arg0
,0));
787 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
788 brw_MOV(p
, brw_writemask(tmp
, BRW_WRITEMASK_Z
), brw_swizzle1(arg0
,1));
789 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
792 BRW_MATH_FUNCTION_POW
,
793 brw_writemask(dst
, BRW_WRITEMASK_Z
),
794 brw_swizzle1(tmp
, 2),
795 brw_swizzle1(arg0
, 3),
796 BRW_MATH_PRECISION_PARTIAL
);
799 brw_ENDIF(p
, if_insn
);
804 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
810 struct brw_compile
*p
= &c
->func
;
812 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
813 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
814 brw_MAC(p
, dst
, arg0
, arg1
);
817 /** 3 or 4-component vector normalization */
818 static void emit_nrm( struct brw_vs_compile
*c
,
823 struct brw_compile
*p
= &c
->func
;
824 struct brw_reg tmp
= get_tmp(c
);
826 /* tmp = dot(arg0, arg0) */
828 brw_DP3(p
, tmp
, arg0
, arg0
);
830 brw_DP4(p
, tmp
, arg0
, arg0
);
832 /* tmp = 1 / sqrt(tmp) */
833 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
835 /* dst = arg0 * tmp */
836 brw_MUL(p
, dst
, arg0
, tmp
);
842 static struct brw_reg
843 get_constant(struct brw_vs_compile
*c
,
848 struct brw_compile
*p
= &c
->func
;
849 struct brw_reg const_reg
;
850 struct brw_reg const2_reg
;
852 assert(argIndex
< 3);
854 if (c
->current_const
[argIndex
].index
!= index
|| relAddr
) {
855 struct brw_reg addrReg
= c
->regs
[TGSI_FILE_ADDRESS
][0];
857 c
->current_const
[argIndex
].index
= index
;
860 printf(" fetch const[%d] for arg %d into reg %d\n",
861 src
.Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
863 /* need to fetch the constant now */
865 c
->current_const
[argIndex
].reg
,/* writeback dest */
867 relAddr
, /* relative indexing? */
868 addrReg
, /* address register */
869 16 * index
, /* byte offset */
870 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
875 const2_reg
= get_tmp(c
);
877 /* use upper half of address reg for second read */
878 addrReg
= stride(addrReg
, 0, 4, 0);
882 const2_reg
, /* writeback dest */
884 relAddr
, /* relative indexing? */
885 addrReg
, /* address register */
886 16 * index
, /* byte offset */
887 SURF_INDEX_VERT_CONST_BUFFER
892 const_reg
= c
->current_const
[argIndex
].reg
;
895 /* merge the two Owords into the constant register */
896 /* const_reg[7..4] = const2_reg[7..4] */
898 suboffset(stride(const_reg
, 0, 4, 1), 4),
899 suboffset(stride(const2_reg
, 0, 4, 1), 4));
900 release_tmp(c
, const2_reg
);
903 /* replicate lower four floats into upper half (to get XYZWXYZW) */
904 const_reg
= stride(const_reg
, 0, 4, 0);
914 /* TODO: relative addressing!
916 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
917 enum tgsi_file_type file
,
921 case TGSI_FILE_TEMPORARY
:
922 case TGSI_FILE_INPUT
:
923 case TGSI_FILE_OUTPUT
:
924 case TGSI_FILE_CONSTANT
:
925 assert(c
->regs
[file
][index
].nr
!= 0);
926 return c
->regs
[file
][index
];
928 case TGSI_FILE_ADDRESS
:
930 return c
->regs
[file
][index
];
932 case TGSI_FILE_NULL
: /* undef values */
933 return brw_null_reg();
937 return brw_null_reg();
945 * Indirect addressing: get reg[[arg] + offset].
947 static struct brw_reg
deref( struct brw_vs_compile
*c
,
951 struct brw_compile
*p
= &c
->func
;
952 struct brw_reg tmp
= vec4(get_tmp(c
));
953 struct brw_reg addr_reg
= c
->regs
[TGSI_FILE_ADDRESS
][0];
954 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
955 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
956 struct brw_reg indirect
= brw_vec4_indirect(0,0);
959 brw_push_insn_state(p
);
960 brw_set_access_mode(p
, BRW_ALIGN_1
);
962 /* This is pretty clunky - load the address register twice and
963 * fetch each 4-dword value in turn. There must be a way to do
964 * this in a single pass, but I couldn't get it to work.
966 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
967 brw_MOV(p
, tmp
, indirect
);
969 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
970 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
972 brw_pop_insn_state(p
);
975 /* NOTE: tmp not released */
981 * Get brw reg corresponding to the instruction's [argIndex] src reg.
982 * TODO: relative addressing!
984 static struct brw_reg
985 get_src_reg( struct brw_vs_compile
*c
,
993 case TGSI_FILE_TEMPORARY
:
994 case TGSI_FILE_INPUT
:
995 case TGSI_FILE_OUTPUT
:
997 return deref(c
, c
->regs
[file
][0], index
);
1000 assert(c
->regs
[file
][index
].nr
!= 0);
1001 return c
->regs
[file
][index
];
1004 case TGSI_FILE_IMMEDIATE
:
1005 return c
->regs
[file
][index
];
1007 case TGSI_FILE_CONSTANT
:
1008 if (c
->vp
->use_const_buffer
) {
1009 return get_constant(c
, argIndex
, index
, relAddr
);
1012 return deref(c
, c
->regs
[TGSI_FILE_CONSTANT
][0], index
);
1015 assert(c
->regs
[TGSI_FILE_CONSTANT
][index
].nr
!= 0);
1016 return c
->regs
[TGSI_FILE_CONSTANT
][index
];
1018 case TGSI_FILE_ADDRESS
:
1020 return c
->regs
[file
][index
];
1022 case TGSI_FILE_NULL
:
1023 /* this is a normal case since we loop over all three src args */
1024 return brw_null_reg();
1028 return brw_null_reg();
1033 static void emit_arl( struct brw_vs_compile
*c
,
1035 struct brw_reg arg0
)
1037 struct brw_compile
*p
= &c
->func
;
1038 struct brw_reg tmp
= dst
;
1039 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1044 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
1045 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
1048 release_tmp(c
, tmp
);
1053 * Return the brw reg for the given instruction's src argument.
1055 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
1056 const struct tgsi_full_src_register
*src
,
1061 if (src
->Register
.File
== TGSI_FILE_NULL
)
1062 return brw_null_reg();
1064 reg
= get_src_reg(c
, argIndex
,
1066 src
->Register
.Index
,
1067 src
->Register
.Indirect
);
1069 /* Convert 3-bit swizzle to 2-bit.
1071 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(src
->Register
.SwizzleX
,
1072 src
->Register
.SwizzleY
,
1073 src
->Register
.SwizzleZ
,
1074 src
->Register
.SwizzleW
);
1076 reg
.negate
= src
->Register
.Negate
? 1 : 0;
1086 * Get brw register for the given program dest register.
1088 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
1091 unsigned writemask
)
1096 case TGSI_FILE_TEMPORARY
:
1097 case TGSI_FILE_OUTPUT
:
1098 assert(c
->regs
[file
][index
].nr
!= 0);
1099 reg
= c
->regs
[file
][index
];
1101 case TGSI_FILE_ADDRESS
:
1103 reg
= c
->regs
[file
][index
];
1105 case TGSI_FILE_NULL
:
1106 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1107 reg
= brw_null_reg();
1111 reg
= brw_null_reg();
1114 reg
.dw1
.bits
.writemask
= writemask
;
1123 * Post-vertex-program processing. Send the results to the URB.
1125 static void emit_vertex_write( struct brw_vs_compile
*c
)
1127 struct brw_compile
*p
= &c
->func
;
1128 struct brw_context
*brw
= p
->brw
;
1129 struct brw_reg m0
= brw_message_reg(0);
1130 struct brw_reg pos
= c
->regs
[TGSI_FILE_OUTPUT
][VERT_RESULT_HPOS
];
1134 GLuint len_vertext_header
= 2;
1136 /* Build ndc coords */
1138 /* ndc = 1.0 / pos.w */
1139 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1140 /* ndc.xyz = pos * ndc */
1141 brw_MUL(p
, brw_writemask(ndc
, BRW_WRITEMASK_XYZ
), pos
, ndc
);
1143 /* Update the header for point size, user clipping flags, and -ve rhw
1146 if (c
->prog_data
.writes_psiz
||
1147 c
->key
.nr_userclip
||
1148 brw
->has_negative_rhw_bug
)
1150 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1153 brw_MOV(p
, header1
, brw_imm_ud(0));
1155 brw_set_access_mode(p
, BRW_ALIGN_16
);
1157 if (c
->prog_data
.writes_psiz
) {
1158 struct brw_reg psiz
= c
->regs
[TGSI_FILE_OUTPUT
][VERT_RESULT_PSIZ
];
1159 brw_MUL(p
, brw_writemask(header1
, BRW_WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1160 brw_AND(p
, brw_writemask(header1
, BRW_WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1163 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1164 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1165 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1166 brw_OR(p
, brw_writemask(header1
, BRW_WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1167 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1170 /* i965 clipping workaround:
1171 * 1) Test for -ve rhw
1173 * set ndc = (0,0,0,0)
1176 * Later, clipping will detect ucp[6] and ensure the primitive is
1177 * clipped against all fixed planes.
1179 if (brw
->has_negative_rhw_bug
) {
1181 vec8(brw_null_reg()),
1183 brw_swizzle1(ndc
, 3),
1186 brw_OR(p
, brw_writemask(header1
, BRW_WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1187 brw_MOV(p
, ndc
, brw_imm_f(0));
1188 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1191 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1192 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1193 brw_set_access_mode(p
, BRW_ALIGN_16
);
1195 release_tmp(c
, header1
);
1198 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1201 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1202 * of zeros followed by two sets of NDC coordinates:
1204 brw_set_access_mode(p
, BRW_ALIGN_1
);
1205 brw_MOV(p
, offset(m0
, 2), ndc
);
1207 if (brw
->gen
== 5) {
1208 /* There are 20 DWs (D0-D19) in VUE vertex header on IGDNG */
1209 brw_MOV(p
, offset(m0
, 3), pos
); /* a portion of vertex header */
1210 /* m4, m5 contain the distances from vertex to the user clip planeXXX.
1211 * Seems it is useless for us.
1212 * m6 is used for aligning, so that the remainder of vertex element is
1215 brw_MOV(p
, offset(m0
, 7), pos
); /* the remainder of vertex element */
1216 len_vertext_header
= 6;
1218 brw_MOV(p
, offset(m0
, 3), pos
);
1219 len_vertext_header
= 2;
1222 eot
= (c
->overflow_count
== 0);
1225 brw_null_reg(), /* dest */
1226 0, /* starting mrf reg nr */
1230 MIN2(c
->nr_outputs
+ 1 + len_vertext_header
, (BRW_MAX_MRF
-1)), /* msg len */
1231 0, /* response len */
1233 eot
, /* writes complete */
1234 0, /* urb destination offset */
1235 BRW_URB_SWIZZLE_INTERLEAVE
);
1237 /* Not all of the vertex outputs/results fit into the MRF.
1238 * Move the overflowed attributes from the GRF to the MRF and
1239 * issue another brw_urb_WRITE().
1241 for (i
= 0; i
< c
->overflow_count
; i
+= BRW_MAX_MRF
) {
1242 unsigned nr
= MIN2(c
->overflow_count
- i
, BRW_MAX_MRF
);
1245 eot
= (i
+ nr
>= c
->overflow_count
);
1247 /* XXX I'm not 100% sure about which MRF regs to use here. Starting
1250 for (j
= 0; j
< nr
; j
++) {
1251 brw_MOV(p
, brw_message_reg(4+j
),
1252 brw_vec8_grf(c
->overflow_grf_start
+ i
+ j
, 0));
1256 brw_null_reg(), /* dest */
1257 4, /* starting mrf reg nr */
1262 0, /* response len */
1264 eot
, /* writes complete */
1265 i
-1, /* urb destination offset */
1266 BRW_URB_SWIZZLE_INTERLEAVE
);
1272 * Called after code generation to resolve subroutine calls and the
1274 * \param end_inst points to brw code for END instruction
1275 * \param last_inst points to last instruction emitted before vertex write
1278 post_vs_emit( struct brw_vs_compile
*c
,
1279 struct brw_instruction
*end_inst
,
1280 struct brw_instruction
*last_inst
)
1284 brw_resolve_cals(&c
->func
);
1286 /* patch up the END code to jump past subroutines, etc */
1287 offset
= last_inst
- end_inst
;
1289 brw_set_src1(end_inst
, brw_imm_d(offset
* 16));
1291 end_inst
->header
.opcode
= BRW_OPCODE_NOP
;
1296 get_predicate(const struct tgsi_full_instruction
*inst
)
1298 /* XXX: disabling for now
1301 if (inst
->dst
.CondMask
== COND_TR
)
1302 return BRW_PREDICATE_NONE
;
1304 /* All of GLSL only produces predicates for COND_NE and one channel per
1305 * vector. Fail badly if someone starts doing something else, as it might
1306 * mean infinite looping or something.
1308 * We'd like to support all the condition codes, but our hardware doesn't
1309 * quite match the Mesa IR, which is modeled after the NV extensions. For
1310 * those, the instruction may update the condition codes or not, then any
1311 * later instruction may use one of those condition codes. For gen4, the
1312 * instruction may update the flags register based on one of the condition
1313 * codes output by the instruction, and then further instructions may
1314 * predicate on that. We can probably support this, but it won't
1315 * necessarily be easy.
1317 /* assert(inst->dst.CondMask == COND_NE); */
1319 switch (inst
->dst
.CondSwizzle
) {
1321 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1323 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1325 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1327 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1329 debug_printf("Unexpected predicate: 0x%08x\n",
1330 inst
->dst
.CondMask
);
1331 return BRW_PREDICATE_NORMAL
;
1334 return BRW_PREDICATE_NORMAL
;
1338 static void emit_insn(struct brw_vs_compile
*c
,
1339 const struct tgsi_full_instruction
*inst
)
1341 unsigned opcode
= inst
->Instruction
.Opcode
;
1342 unsigned label
= inst
->Label
.Label
;
1343 struct brw_compile
*p
= &c
->func
;
1344 struct brw_context
*brw
= p
->brw
;
1345 struct brw_reg args
[3], dst
;
1349 printf("%d: ", insn
);
1350 _mesa_print_instruction(inst
);
1353 /* Get argument regs.
1355 for (i
= 0; i
< 3; i
++) {
1356 args
[i
] = get_arg(c
, &inst
->Src
[i
], i
);
1359 /* Get dest regs. Note that it is possible for a reg to be both
1360 * dst and arg, given the static allocation of registers. So
1361 * care needs to be taken emitting multi-operation instructions.
1364 inst
->Dst
[0].Register
.File
,
1365 inst
->Dst
[0].Register
.Index
,
1366 inst
->Dst
[0].Register
.WriteMask
);
1370 if (inst
->Instruction
.Saturate
!= TGSI_SAT_NONE
) {
1371 debug_printf("Unsupported saturate in vertex shader");
1375 case TGSI_OPCODE_ABS
:
1376 brw_MOV(p
, dst
, brw_abs(args
[0]));
1378 case TGSI_OPCODE_ADD
:
1379 brw_ADD(p
, dst
, args
[0], args
[1]);
1381 case TGSI_OPCODE_COS
:
1382 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1384 case TGSI_OPCODE_DP3
:
1385 brw_DP3(p
, dst
, args
[0], args
[1]);
1387 case TGSI_OPCODE_DP4
:
1388 brw_DP4(p
, dst
, args
[0], args
[1]);
1390 case TGSI_OPCODE_DPH
:
1391 brw_DPH(p
, dst
, args
[0], args
[1]);
1393 case TGSI_OPCODE_NRM
:
1394 emit_nrm(c
, dst
, args
[0], 3);
1396 case TGSI_OPCODE_NRM4
:
1397 emit_nrm(c
, dst
, args
[0], 4);
1399 case TGSI_OPCODE_DST
:
1400 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1402 case TGSI_OPCODE_EXP
:
1403 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1405 case TGSI_OPCODE_EX2
:
1406 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1408 case TGSI_OPCODE_ARL
:
1409 emit_arl(c
, dst
, args
[0]);
1411 case TGSI_OPCODE_FLR
:
1412 brw_RNDD(p
, dst
, args
[0]);
1414 case TGSI_OPCODE_FRC
:
1415 brw_FRC(p
, dst
, args
[0]);
1417 case TGSI_OPCODE_LOG
:
1418 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1420 case TGSI_OPCODE_LG2
:
1421 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1423 case TGSI_OPCODE_LIT
:
1424 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1426 case TGSI_OPCODE_LRP
:
1427 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1429 case TGSI_OPCODE_MAD
:
1430 brw_MOV(p
, brw_acc_reg(), args
[2]);
1431 brw_MAC(p
, dst
, args
[0], args
[1]);
1433 case TGSI_OPCODE_MAX
:
1434 emit_max(p
, dst
, args
[0], args
[1]);
1436 case TGSI_OPCODE_MIN
:
1437 emit_min(p
, dst
, args
[0], args
[1]);
1439 case TGSI_OPCODE_MOV
:
1440 brw_MOV(p
, dst
, args
[0]);
1442 case TGSI_OPCODE_MUL
:
1443 brw_MUL(p
, dst
, args
[0], args
[1]);
1445 case TGSI_OPCODE_POW
:
1446 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1448 case TGSI_OPCODE_RCP
:
1449 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1451 case TGSI_OPCODE_RSQ
:
1452 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
,
1453 brw_swizzle(args
[0], 0,0,0,0), BRW_MATH_PRECISION_FULL
);
1455 case TGSI_OPCODE_SEQ
:
1456 emit_seq(p
, dst
, args
[0], args
[1]);
1458 case TGSI_OPCODE_SIN
:
1459 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1461 case TGSI_OPCODE_SNE
:
1462 emit_sne(p
, dst
, args
[0], args
[1]);
1464 case TGSI_OPCODE_SGE
:
1465 emit_sge(p
, dst
, args
[0], args
[1]);
1467 case TGSI_OPCODE_SGT
:
1468 emit_sgt(p
, dst
, args
[0], args
[1]);
1470 case TGSI_OPCODE_SLT
:
1471 emit_slt(p
, dst
, args
[0], args
[1]);
1473 case TGSI_OPCODE_SLE
:
1474 emit_sle(p
, dst
, args
[0], args
[1]);
1476 case TGSI_OPCODE_SUB
:
1477 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1479 case TGSI_OPCODE_TRUNC
:
1480 /* round toward zero */
1481 brw_RNDZ(p
, dst
, args
[0]);
1483 case TGSI_OPCODE_XPD
:
1484 emit_xpd(p
, dst
, args
[0], args
[1]);
1486 case TGSI_OPCODE_IF
:
1487 assert(c
->if_depth
< MAX_IF_DEPTH
);
1488 c
->if_inst
[c
->if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1489 /* Note that brw_IF smashes the predicate_control field. */
1490 c
->if_inst
[c
->if_depth
]->header
.predicate_control
= get_predicate(inst
);
1493 case TGSI_OPCODE_ELSE
:
1494 c
->if_inst
[c
->if_depth
-1] = brw_ELSE(p
, c
->if_inst
[c
->if_depth
-1]);
1496 case TGSI_OPCODE_ENDIF
:
1497 assert(c
->if_depth
> 0);
1498 brw_ENDIF(p
, c
->if_inst
[--c
->if_depth
]);
1500 case TGSI_OPCODE_BGNLOOP
:
1501 c
->loop_inst
[c
->loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1503 case TGSI_OPCODE_BRK
:
1504 brw_set_predicate_control(p
, get_predicate(inst
));
1506 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1508 case TGSI_OPCODE_CONT
:
1509 brw_set_predicate_control(p
, get_predicate(inst
));
1511 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1513 case TGSI_OPCODE_ENDLOOP
:
1515 struct brw_instruction
*inst0
, *inst1
;
1523 inst0
= inst1
= brw_WHILE(p
, c
->loop_inst
[c
->loop_depth
]);
1524 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1525 while (inst0
> c
->loop_inst
[c
->loop_depth
]) {
1527 if (inst0
->header
.opcode
== TGSI_OPCODE_BRK
) {
1528 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1529 inst0
->bits3
.if_else
.pop_count
= 0;
1531 else if (inst0
->header
.opcode
== TGSI_OPCODE_CONT
) {
1532 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1533 inst0
->bits3
.if_else
.pop_count
= 0;
1538 case TGSI_OPCODE_BRA
:
1539 brw_set_predicate_control(p
, get_predicate(inst
));
1540 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1541 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1543 case TGSI_OPCODE_CAL
:
1544 brw_set_access_mode(p
, BRW_ALIGN_1
);
1545 brw_ADD(p
, deref_1d(c
->stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1546 brw_set_access_mode(p
, BRW_ALIGN_16
);
1547 brw_ADD(p
, get_addr_reg(c
->stack_index
),
1548 get_addr_reg(c
->stack_index
), brw_imm_d(4));
1549 brw_save_call(p
, label
, p
->nr_insn
);
1550 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1552 case TGSI_OPCODE_RET
:
1553 brw_ADD(p
, get_addr_reg(c
->stack_index
),
1554 get_addr_reg(c
->stack_index
), brw_imm_d(-4));
1555 brw_set_access_mode(p
, BRW_ALIGN_1
);
1556 brw_MOV(p
, brw_ip_reg(), deref_1d(c
->stack_index
, 0));
1557 brw_set_access_mode(p
, BRW_ALIGN_16
);
1559 case TGSI_OPCODE_END
:
1560 c
->end_offset
= p
->nr_insn
;
1561 /* this instruction will get patched later to jump past subroutine
1564 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1566 case TGSI_OPCODE_BGNSUB
:
1567 brw_save_label(p
, p
->nr_insn
, p
->nr_insn
);
1569 case TGSI_OPCODE_ENDSUB
:
1573 debug_printf("Unsupported opcode %i (%s) in vertex shader",
1575 tgsi_get_opcode_name(opcode
));
1578 /* Set the predication update on the last instruction of the native
1579 * instruction sequence.
1581 * This would be problematic if it was set on a math instruction,
1582 * but that shouldn't be the case with the current GLSL compiler.
1587 if (inst
->CondUpdate
) {
1588 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1590 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1591 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1599 /* Emit the vertex program instructions here.
1601 void brw_vs_emit(struct brw_vs_compile
*c
)
1603 struct brw_compile
*p
= &c
->func
;
1604 const struct tgsi_token
*tokens
= c
->vp
->tokens
;
1605 struct brw_instruction
*end_inst
, *last_inst
;
1606 struct tgsi_parse_context parse
;
1607 struct tgsi_full_instruction
*inst
;
1609 if (BRW_DEBUG
& DEBUG_VS
)
1610 tgsi_dump(c
->vp
->tokens
, 0);
1612 c
->stack_index
= brw_indirect(0, 0);
1614 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1615 brw_set_access_mode(p
, BRW_ALIGN_16
);
1618 /* Static register allocation
1620 brw_vs_alloc_regs(c
);
1622 if (c
->vp
->has_flow_control
) {
1623 brw_MOV(p
, get_addr_reg(c
->stack_index
), brw_address(c
->stack
));
1628 tgsi_parse_init( &parse
, tokens
);
1629 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1630 tgsi_parse_token( &parse
);
1632 switch( parse
.FullToken
.Token
.Type
) {
1633 case TGSI_TOKEN_TYPE_DECLARATION
:
1634 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1637 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1638 inst
= &parse
.FullToken
.FullInstruction
;
1639 emit_insn( c
, inst
);
1646 tgsi_parse_free( &parse
);
1648 end_inst
= &p
->store
[c
->end_offset
];
1649 last_inst
= &p
->store
[p
->nr_insn
];
1651 /* The END instruction will be patched to jump to this code */
1652 emit_vertex_write(c
);
1654 post_vs_emit(c
, end_inst
, last_inst
);
1656 if (BRW_DEBUG
& DEBUG_VS
) {
1657 debug_printf("vs-native:\n");
1658 brw_disasm(stderr
, p
->store
, p
->nr_insn
, p
->brw
->gen
);