Merge branch 'gallium-msaa'
[mesa.git] / src / gallium / drivers / i965 / brw_vs_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "util/u_math.h"
33
34
35 #include "brw_debug.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38 #include "brw_defines.h"
39
40 struct brw_vs_unit_key {
41 unsigned int total_grf;
42 unsigned int urb_entry_read_length;
43 unsigned int curb_entry_read_length;
44
45 unsigned int curbe_offset;
46
47 unsigned int nr_urb_entries, urb_size;
48
49 unsigned int nr_surfaces;
50 };
51
52 static void
53 vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key)
54 {
55 memset(key, 0, sizeof(*key));
56
57 /* CACHE_NEW_VS_PROG */
58 key->total_grf = brw->vs.prog_data->total_grf;
59 key->urb_entry_read_length = brw->vs.prog_data->urb_read_length;
60 key->curb_entry_read_length = brw->vs.prog_data->curb_read_length;
61
62 /* BRW_NEW_URB_FENCE */
63 key->nr_urb_entries = brw->urb.nr_vs_entries;
64 key->urb_size = brw->urb.vsize;
65
66 /* BRW_NEW_NR_VS_SURFACES */
67 key->nr_surfaces = brw->vs.nr_surfaces;
68
69 /* PIPE_NEW_CLIP */
70 if (brw->curr.ucp.nr) {
71 /* Note that we read in the userclip planes as well, hence
72 * clip_start:
73 */
74 key->curbe_offset = brw->curbe.clip_start;
75 }
76 else {
77 key->curbe_offset = brw->curbe.vs_start;
78 }
79 }
80
81 static enum pipe_error
82 vs_unit_create_from_key(struct brw_context *brw,
83 struct brw_vs_unit_key *key,
84 struct brw_winsys_reloc *reloc,
85 struct brw_winsys_buffer **bo_out)
86 {
87 enum pipe_error ret;
88 struct brw_vs_unit_state vs;
89 int chipset_max_threads;
90
91 memset(&vs, 0, sizeof(vs));
92
93 vs.thread0.kernel_start_pointer = 0; /* reloc */
94 vs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
95 vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
96 /* Choosing multiple program flow means that we may get 2-vertex threads,
97 * which will have the channel mask for dwords 4-7 enabled in the thread,
98 * and those dwords will be written to the second URB handle when we
99 * brw_urb_WRITE() results.
100 */
101 vs.thread1.single_program_flow = 0;
102
103 if (BRW_IS_IGDNG(brw))
104 vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
105 else
106 vs.thread1.binding_table_entry_count = key->nr_surfaces;
107
108 vs.thread3.urb_entry_read_length = key->urb_entry_read_length;
109 vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
110 vs.thread3.dispatch_grf_start_reg = 1;
111 vs.thread3.urb_entry_read_offset = 0;
112 vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
113
114 if (BRW_IS_IGDNG(brw))
115 vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2;
116 else
117 vs.thread4.nr_urb_entries = key->nr_urb_entries;
118
119 vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
120
121 if (BRW_IS_IGDNG(brw))
122 chipset_max_threads = 72;
123 else if (BRW_IS_G4X(brw))
124 chipset_max_threads = 32;
125 else
126 chipset_max_threads = 16;
127
128 vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
129 1, chipset_max_threads) - 1;
130
131 if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
132 vs.thread4.max_threads = 0;
133
134 /* No samplers for ARB_vp programs:
135 */
136 /* It has to be set to 0 for IGDNG
137 */
138 vs.vs5.sampler_count = 0;
139
140 if (BRW_DEBUG & DEBUG_STATS)
141 vs.thread4.stats_enable = 1;
142
143 /* Vertex program always enabled:
144 */
145 vs.vs6.vs_enable = 1;
146
147 ret = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
148 key, sizeof(*key),
149 reloc, 1,
150 &vs, sizeof(vs),
151 NULL, NULL,
152 bo_out);
153 if (ret)
154 return ret;
155
156 return PIPE_OK;
157 }
158
159 static int prepare_vs_unit(struct brw_context *brw)
160 {
161 struct brw_vs_unit_key key;
162 enum pipe_error ret;
163 struct brw_winsys_reloc reloc[1];
164 unsigned grf_reg_count;
165
166 vs_unit_populate_key(brw, &key);
167
168 grf_reg_count = (align(key.total_grf, 16) / 16 - 1);
169
170 /* Emit VS program relocation */
171 make_reloc(&reloc[0],
172 BRW_USAGE_STATE,
173 grf_reg_count << 1,
174 offsetof(struct brw_vs_unit_state, thread0),
175 brw->vs.prog_bo);
176
177
178 if (brw_search_cache(&brw->cache, BRW_VS_UNIT,
179 &key, sizeof(key),
180 reloc, 1,
181 NULL,
182 &brw->vs.state_bo))
183 return PIPE_OK;
184
185 ret = vs_unit_create_from_key(brw, &key, reloc, &brw->vs.state_bo);
186 if (ret)
187 return ret;
188
189 return PIPE_OK;
190 }
191
192 const struct brw_tracked_state brw_vs_unit = {
193 .dirty = {
194 .mesa = (PIPE_NEW_CLIP),
195 .brw = (BRW_NEW_CURBE_OFFSETS |
196 BRW_NEW_NR_VS_SURFACES |
197 BRW_NEW_URB_FENCE),
198 .cache = CACHE_NEW_VS_PROG
199 },
200 .prepare = prepare_vs_unit,
201 };