i965g: convert read/write domain pairs into single usage value
[mesa.git] / src / gallium / drivers / i965 / brw_vs_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "util/u_math.h"
33
34
35 #include "brw_debug.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38 #include "brw_defines.h"
39
40 struct brw_vs_unit_key {
41 unsigned int total_grf;
42 unsigned int urb_entry_read_length;
43 unsigned int curb_entry_read_length;
44
45 unsigned int curbe_offset;
46
47 unsigned int nr_urb_entries, urb_size;
48
49 unsigned int nr_surfaces;
50 };
51
52 static void
53 vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key)
54 {
55 memset(key, 0, sizeof(*key));
56
57 /* CACHE_NEW_VS_PROG */
58 key->total_grf = brw->vs.prog_data->total_grf;
59 key->urb_entry_read_length = brw->vs.prog_data->urb_read_length;
60 key->curb_entry_read_length = brw->vs.prog_data->curb_read_length;
61
62 /* BRW_NEW_URB_FENCE */
63 key->nr_urb_entries = brw->urb.nr_vs_entries;
64 key->urb_size = brw->urb.vsize;
65
66 /* BRW_NEW_NR_VS_SURFACES */
67 key->nr_surfaces = brw->vs.nr_surfaces;
68
69 /* PIPE_NEW_CLIP */
70 if (brw->curr.ucp.nr) {
71 /* Note that we read in the userclip planes as well, hence
72 * clip_start:
73 */
74 key->curbe_offset = brw->curbe.clip_start;
75 }
76 else {
77 key->curbe_offset = brw->curbe.vs_start;
78 }
79 }
80
81 static struct brw_winsys_buffer *
82 vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
83 {
84 struct brw_vs_unit_state vs;
85 struct brw_winsys_buffer *bo;
86 int chipset_max_threads;
87
88 memset(&vs, 0, sizeof(vs));
89
90 vs.thread0.kernel_start_pointer = brw->vs.prog_bo->offset[0] >> 6; /* reloc */
91 vs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
92 vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
93 /* Choosing multiple program flow means that we may get 2-vertex threads,
94 * which will have the channel mask for dwords 4-7 enabled in the thread,
95 * and those dwords will be written to the second URB handle when we
96 * brw_urb_WRITE() results.
97 */
98 vs.thread1.single_program_flow = 0;
99
100 if (BRW_IS_IGDNG(brw))
101 vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
102 else
103 vs.thread1.binding_table_entry_count = key->nr_surfaces;
104
105 vs.thread3.urb_entry_read_length = key->urb_entry_read_length;
106 vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
107 vs.thread3.dispatch_grf_start_reg = 1;
108 vs.thread3.urb_entry_read_offset = 0;
109 vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
110
111 if (BRW_IS_IGDNG(brw))
112 vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2;
113 else
114 vs.thread4.nr_urb_entries = key->nr_urb_entries;
115
116 vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
117
118 if (BRW_IS_IGDNG(brw))
119 chipset_max_threads = 72;
120 else if (BRW_IS_G4X(brw))
121 chipset_max_threads = 32;
122 else
123 chipset_max_threads = 16;
124
125 vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
126 1, chipset_max_threads) - 1;
127
128 if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
129 vs.thread4.max_threads = 0;
130
131 /* No samplers for ARB_vp programs:
132 */
133 /* It has to be set to 0 for IGDNG
134 */
135 vs.vs5.sampler_count = 0;
136
137 if (BRW_DEBUG & DEBUG_STATS)
138 vs.thread4.stats_enable = 1;
139
140 /* Vertex program always enabled:
141 */
142 vs.vs6.vs_enable = 1;
143
144 bo = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
145 key, sizeof(*key),
146 &brw->vs.prog_bo, 1,
147 &vs, sizeof(vs),
148 NULL, NULL);
149
150 /* Emit VS program relocation */
151 brw->sws->bo_emit_reloc(bo,
152 BRW_USAGE_STATE,
153 vs.thread0.grf_reg_count << 1,
154 offsetof(struct brw_vs_unit_state, thread0),
155 brw->vs.prog_bo);
156
157 return bo;
158 }
159
160 static int prepare_vs_unit(struct brw_context *brw)
161 {
162 struct brw_vs_unit_key key;
163
164 vs_unit_populate_key(brw, &key);
165
166 brw->sws->bo_unreference(brw->vs.state_bo);
167 brw->vs.state_bo = brw_search_cache(&brw->cache, BRW_VS_UNIT,
168 &key, sizeof(key),
169 &brw->vs.prog_bo, 1,
170 NULL);
171 if (brw->vs.state_bo == NULL) {
172 brw->vs.state_bo = vs_unit_create_from_key(brw, &key);
173 }
174
175 return 0;
176 }
177
178 const struct brw_tracked_state brw_vs_unit = {
179 .dirty = {
180 .mesa = (PIPE_NEW_CLIP),
181 .brw = (BRW_NEW_CURBE_OFFSETS |
182 BRW_NEW_NR_VS_SURFACES |
183 BRW_NEW_URB_FENCE),
184 .cache = CACHE_NEW_VS_PROG
185 },
186 .prepare = prepare_vs_unit,
187 };