src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31 #include "tgsi/tgsi_info.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_screen.h"
  35 #include "brw_wm.h"
  36 #include "brw_state.h"
  37 #include "brw_debug.h"
  38 #include "brw_resource.h"
  39 #include "brw_pipe_rast.h"
  40
  41
  42 /** Return number of src args for given instruction */
  43 GLuint brw_wm_nr_args( GLuint opcode )
  44 {
  45    switch (opcode) {
  46    case WM_FRONTFACING:
  47    case WM_PIXELXY:
  48       return 0;
  49    case WM_CINTERP:
  50    case WM_WPOSXY:
  51    case WM_DELTAXY:
  52       return 1;
  53    case WM_LINTERP:
  54    case WM_PIXELW:
  55       return 2;
  56    case WM_FB_WRITE:
  57    case WM_PINTERP:
  58       return 3;
  59    case TGSI_OPCODE_TEX:
  60    case TGSI_OPCODE_TXP:
  61    case TGSI_OPCODE_TXB:
  62    case TGSI_OPCODE_TXD:
  63       /* sampler arg is held as a field in the instruction, not in an
  64        * actual register:
  65        */
  66       return tgsi_get_opcode_info(opcode)->num_src - 1;
  67
  68    default:
  69       assert(opcode < MAX_OPCODE);
  70       return tgsi_get_opcode_info(opcode)->num_src;
  71    }
  72 }
  73
  74
  75 GLuint brw_wm_is_scalar_result( GLuint opcode )
  76 {
  77    switch (opcode) {
  78    case TGSI_OPCODE_COS:
  79    case TGSI_OPCODE_EX2:
  80    case TGSI_OPCODE_LG2:
  81    case TGSI_OPCODE_POW:
  82    case TGSI_OPCODE_RCP:
  83    case TGSI_OPCODE_RSQ:
  84    case TGSI_OPCODE_SIN:
  85    case TGSI_OPCODE_DP3:
  86    case TGSI_OPCODE_DP4:
  87    case TGSI_OPCODE_DPH:
  88    case TGSI_OPCODE_DST:
  89       return 1;
  90
  91    default:
  92       return 0;
  93    }
  94 }
  95
  96
  97 /**
  98  * Do GPU code generation for shaders without flow control.  Shaders
  99  * without flow control instructions can more readily be analysed for
 100  * SSA-style optimizations.
 101  */
 102 static void
 103 brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c)
 104 {
 105    /* Augment fragment program.  Add instructions for pre- and
 106     * post-fragment-program tasks such as interpolation and fogging.
 107     */
 108    brw_wm_pass_fp(c);
 109
 110    /* Translate to intermediate representation.  Build register usage
 111     * chains.
 112     */
 113    brw_wm_pass0(c);
 114
 115    /* Dead code removal.
 116     */
 117    brw_wm_pass1(c);
 118
 119    /* Register allocation.
 120     * Divide by two because we operate on 16 pixels at a time and require
 121     * two GRF entries for each logical shader register.
 122     */
 123    c->grf_limit = BRW_WM_MAX_GRF / 2;
 124
 125    brw_wm_pass2(c);
 126
 127    /* how many general-purpose registers are used */
 128    c->prog_data.total_grf = c->max_wm_grf;
 129
 130    /* Scratch space is used for register spilling */
 131    if (c->last_scratch) {
 132       c->prog_data.total_scratch = c->last_scratch + 0x40;
 133    }
 134    else {
 135       c->prog_data.total_scratch = 0;
 136    }
 137
 138    /* Emit GEN4 code.
 139     */
 140    brw_wm_emit(c);
 141 }
 142
 143
 144 /**
 145  * All Mesa program -> GPU code generation goes through this function.
 146  * Depending on the instructions used (i.e. flow control instructions)
 147  * we'll use one of two code generators.
 148  */
 149 static enum pipe_error do_wm_prog( struct brw_context *brw,
 150                                    struct brw_fragment_shader *fp,
 151                                    struct brw_wm_prog_key *key,
 152                                    struct brw_winsys_buffer **bo_out)
 153 {
 154    enum pipe_error ret;
 155    struct brw_wm_compile *c;
 156    const GLuint *program;
 157    GLuint program_size;
 158
 159    if (brw->wm.compile_data == NULL) {
 160       brw->wm.compile_data = MALLOC(sizeof(*brw->wm.compile_data));
 161       if (!brw->wm.compile_data)
 162          return PIPE_ERROR_OUT_OF_MEMORY;
 163    }
 164
 165    c = brw->wm.compile_data;
 166    memset(c, 0, sizeof *c);
 167
 168    c->key = *key;
 169    c->fp = fp;
 170    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 171
 172    brw_init_compile(brw, &c->func);
 173
 174    /*
 175     * Shader which use GLSL features such as flow control are handled
 176     * differently from "simple" shaders.
 177     */
 178    if (fp->has_flow_control) {
 179       c->dispatch_width = 8;
 180       /* XXX: GLSL support
 181        */
 182       exit(1);
 183       /* brw_wm_branching_shader_emit(brw, c); */
 184    }
 185    else {
 186       c->dispatch_width = 16;
 187       brw_wm_linear_shader_emit(brw, c);
 188    }
 189
 190    if (BRW_DEBUG & DEBUG_WM)
 191       debug_printf("\n");
 192
 193    /* get the program
 194     */
 195    ret = brw_get_program(&c->func, &program, &program_size);
 196    if (ret)
 197       return ret;
 198
 199    ret = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 200                            &c->key, sizeof(c->key),
 201                            NULL, 0,
 202                            program, program_size,
 203                            &c->prog_data,
 204                            &brw->wm.prog_data,
 205                            bo_out );
 206    if (ret)
 207       return ret;
 208
 209    return PIPE_OK;
 210 }
 211
 212
 213
 214 static void brw_wm_populate_key( struct brw_context *brw,
 215                                  struct brw_wm_prog_key *key )
 216 {
 217    unsigned lookup, line_aa;
 218    unsigned i;
 219
 220    memset(key, 0, sizeof(*key));
 221
 222    /* PIPE_NEW_FRAGMENT_SHADER
 223     * PIPE_NEW_DEPTH_STENCIL_ALPHA
 224     */
 225    lookup = (brw->curr.zstencil->iz_lookup |
 226              brw->curr.fragment_shader->iz_lookup);
 227
 228
 229    /* PIPE_NEW_RAST
 230     * BRW_NEW_REDUCED_PRIMITIVE
 231     */
 232    switch (brw->reduced_primitive) {
 233    case PIPE_PRIM_POINTS:
 234       line_aa = AA_NEVER;
 235       break;
 236    case PIPE_PRIM_LINES:
 237       line_aa = (brw->curr.rast->templ.line_smooth ?
 238                  AA_ALWAYS : AA_NEVER);
 239       break;
 240    default:
 241       line_aa = brw->curr.rast->unfilled_aa_line;
 242       break;
 243    }
 244
 245    brw_wm_lookup_iz(line_aa,
 246                     lookup,
 247                     brw->curr.fragment_shader->uses_depth,
 248                     key);
 249
 250    /* PIPE_NEW_RAST */
 251    key->flat_shade = brw->curr.rast->templ.flatshade;
 252
 253
 254    /* PIPE_NEW_BOUND_TEXTURES */
 255    for (i = 0; i < brw->curr.num_fragment_sampler_views; i++) {
 256       const struct brw_texture *tex = brw_texture(brw->curr.fragment_sampler_views[i]->texture);
 257
 258       if (tex->b.b.format == PIPE_FORMAT_UYVY)
 259          key->yuvtex_mask |= 1 << i;
 260
 261       if (tex->b.b.format == PIPE_FORMAT_YUYV)
 262          key->yuvtex_swap_mask |= 1 << i;
 263
 264       /* XXX: shadow texture
 265        */
 266       /* key->shadowtex_mask |= 1<<i; */
 267    }
 268
 269    /* CACHE_NEW_VS_PROG */
 270    key->vp_nr_outputs = brw->vs.prog_data->nr_outputs;
 271
 272    key->nr_cbufs = brw->curr.fb.nr_cbufs;
 273
 274    key->nr_inputs = brw->curr.fragment_shader->info.num_inputs;
 275
 276    /* The unique fragment program ID */
 277    key->program_string_id = brw->curr.fragment_shader->id;
 278 }
 279
 280
 281 static enum pipe_error brw_prepare_wm_prog(struct brw_context *brw)
 282 {
 283    struct brw_wm_prog_key key;
 284    struct brw_fragment_shader *fs = brw->curr.fragment_shader;
 285    enum pipe_error ret;
 286
 287    brw_wm_populate_key(brw, &key);
 288
 289    /* Make an early check for the key.
 290     */
 291    if (brw_search_cache(&brw->cache, BRW_WM_PROG,
 292                         &key, sizeof(key),
 293                         NULL, 0,
 294                         &brw->wm.prog_data,
 295                         &brw->wm.prog_bo))
 296       return PIPE_OK;
 297
 298    ret = do_wm_prog(brw, fs, &key, &brw->wm.prog_bo);
 299    if (ret)
 300       return ret;
 301
 302    return PIPE_OK;
 303 }
 304
 305
 306 const struct brw_tracked_state brw_wm_prog = {
 307    .dirty = {
 308       .mesa  = (PIPE_NEW_FRAGMENT_SHADER |
 309                 PIPE_NEW_DEPTH_STENCIL_ALPHA |
 310                 PIPE_NEW_RAST |
 311                 PIPE_NEW_NR_CBUFS |
 312                 PIPE_NEW_BOUND_TEXTURES),
 313       .brw   = (BRW_NEW_WM_INPUT_DIMENSIONS |
 314                 BRW_NEW_REDUCED_PRIMITIVE),
 315       .cache = CACHE_NEW_VS_PROG,
 316    },
 317    .prepare = brw_prepare_wm_prog
 318 };
 319