src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31 #include "tgsi/tgsi_info.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_screen.h"
  35 #include "brw_util.h"
  36 #include "brw_wm.h"
  37 #include "brw_state.h"
  38 #include "brw_debug.h"
  39 #include "brw_pipe_rast.h"
  40
  41
  42 /** Return number of src args for given instruction */
  43 GLuint brw_wm_nr_args( GLuint opcode )
  44 {
  45    switch (opcode) {
  46    case WM_FRONTFACING:
  47    case WM_PIXELXY:
  48       return 0;
  49    case WM_CINTERP:
  50    case WM_WPOSXY:
  51    case WM_DELTAXY:
  52       return 1;
  53    case WM_LINTERP:
  54    case WM_PIXELW:
  55       return 2;
  56    case WM_FB_WRITE:
  57    case WM_PINTERP:
  58       return 3;
  59    default:
  60       assert(opcode < MAX_OPCODE);
  61       return tgsi_get_opcode_info(opcode)->num_src;
  62    }
  63 }
  64
  65
  66 GLuint brw_wm_is_scalar_result( GLuint opcode )
  67 {
  68    switch (opcode) {
  69    case TGSI_OPCODE_COS:
  70    case TGSI_OPCODE_EX2:
  71    case TGSI_OPCODE_LG2:
  72    case TGSI_OPCODE_POW:
  73    case TGSI_OPCODE_RCP:
  74    case TGSI_OPCODE_RSQ:
  75    case TGSI_OPCODE_SIN:
  76    case TGSI_OPCODE_DP3:
  77    case TGSI_OPCODE_DP4:
  78    case TGSI_OPCODE_DPH:
  79    case TGSI_OPCODE_DST:
  80       return 1;
  81
  82    default:
  83       return 0;
  84    }
  85 }
  86
  87
  88 /**
  89  * Do GPU code generation for shaders without flow control.  Shaders
  90  * without flow control instructions can more readily be analysed for
  91  * SSA-style optimizations.
  92  */
  93 static void
  94 brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c)
  95 {
  96    /* Augment fragment program.  Add instructions for pre- and
  97     * post-fragment-program tasks such as interpolation and fogging.
  98     */
  99    brw_wm_pass_fp(c);
 100
 101    /* Translate to intermediate representation.  Build register usage
 102     * chains.
 103     */
 104    brw_wm_pass0(c);
 105
 106    /* Dead code removal.
 107     */
 108    brw_wm_pass1(c);
 109
 110    /* Register allocation.
 111     * Divide by two because we operate on 16 pixels at a time and require
 112     * two GRF entries for each logical shader register.
 113     */
 114    c->grf_limit = BRW_WM_MAX_GRF / 2;
 115
 116    brw_wm_pass2(c);
 117
 118    /* how many general-purpose registers are used */
 119    c->prog_data.total_grf = c->max_wm_grf;
 120
 121    /* Scratch space is used for register spilling */
 122    if (c->last_scratch) {
 123       c->prog_data.total_scratch = c->last_scratch + 0x40;
 124    }
 125    else {
 126       c->prog_data.total_scratch = 0;
 127    }
 128
 129    /* Emit GEN4 code.
 130     */
 131    brw_wm_emit(c);
 132 }
 133
 134
 135 /**
 136  * All Mesa program -> GPU code generation goes through this function.
 137  * Depending on the instructions used (i.e. flow control instructions)
 138  * we'll use one of two code generators.
 139  */
 140 static int do_wm_prog( struct brw_context *brw,
 141                         struct brw_fragment_shader *fp,
 142                         struct brw_wm_prog_key *key)
 143 {
 144    struct brw_wm_compile *c;
 145    const GLuint *program;
 146    GLuint program_size;
 147
 148    c = brw->wm.compile_data;
 149    if (c == NULL) {
 150       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 151       c = brw->wm.compile_data;
 152       if (c == NULL) {
 153          /* Ouch - big out of memory problem.  Can't continue
 154           * without triggering a segfault, no way to signal,
 155           * so just return.
 156           */
 157          return PIPE_ERROR_OUT_OF_MEMORY;
 158       }
 159    } else {
 160       memset(c, 0, sizeof(*brw->wm.compile_data));
 161    }
 162    memcpy(&c->key, key, sizeof(*key));
 163
 164    c->fp = fp;
 165    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 166
 167    brw_init_compile(brw, &c->func);
 168
 169    /* temporary sanity check assertion */
 170    assert(fp->has_flow_control == brw_wm_has_flow_control(c->fp));
 171
 172    /*
 173     * Shader which use GLSL features such as flow control are handled
 174     * differently from "simple" shaders.
 175     */
 176    if (fp->has_flow_control) {
 177       c->dispatch_width = 8;
 178       /* XXX: GLSL support
 179        */
 180       exit(1);
 181       //brw_wm_branching_shader_emit(brw, c);
 182    }
 183    else {
 184       c->dispatch_width = 16;
 185       brw_wm_linear_shader_emit(brw, c);
 186    }
 187
 188    if (BRW_DEBUG & DEBUG_WM)
 189       debug_printf("\n");
 190
 191    /* get the program
 192     */
 193    program = brw_get_program(&c->func, &program_size);
 194
 195    brw->sws->bo_unreference(brw->wm.prog_bo);
 196    brw->wm.prog_bo = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 197                                        &c->key, sizeof(c->key),
 198                                        NULL, 0,
 199                                        program, program_size,
 200                                        &c->prog_data,
 201                                        &brw->wm.prog_data );
 202
 203    return 0;
 204 }
 205
 206
 207
 208 static void brw_wm_populate_key( struct brw_context *brw,
 209                                  struct brw_wm_prog_key *key )
 210 {
 211    unsigned lookup, line_aa;
 212    unsigned i;
 213
 214    memset(key, 0, sizeof(*key));
 215
 216    /* PIPE_NEW_FRAGMENT_SHADER
 217     * PIPE_NEW_DEPTH_STENCIL_ALPHA
 218     */
 219    lookup = (brw->curr.zstencil->iz_lookup |
 220              brw->curr.fragment_shader->iz_lookup);
 221
 222
 223    /* PIPE_NEW_RAST
 224     * BRW_NEW_REDUCED_PRIMITIVE
 225     */
 226    switch (brw->reduced_primitive) {
 227    case PIPE_PRIM_POINTS:
 228       line_aa = AA_NEVER;
 229       break;
 230    case PIPE_PRIM_LINES:
 231       line_aa = AA_ALWAYS;
 232       break;
 233    default:
 234       line_aa = brw->curr.rast->unfilled_aa_line;
 235       break;
 236    }
 237
 238    brw_wm_lookup_iz(line_aa,
 239                     lookup,
 240                     brw->curr.fragment_shader->uses_depth,
 241                     key);
 242
 243    /* PIPE_NEW_RAST */
 244    key->flat_shade = brw->curr.rast->templ.flatshade;
 245
 246
 247    /* PIPE_NEW_BOUND_TEXTURES */
 248    for (i = 0; i < brw->curr.num_textures; i++) {
 249       const struct brw_texture *tex = brw_texture(brw->curr.texture[i]);
 250
 251       if (tex->base.format == PIPE_FORMAT_YCBCR)
 252          key->yuvtex_mask |= 1 << i;
 253
 254       if (tex->base.format == PIPE_FORMAT_YCBCR_REV)
 255          key->yuvtex_swap_mask |= 1 << i;
 256
 257       /* XXX: shadow texture
 258        */
 259       /* key->shadowtex_mask |= 1<<i; */
 260    }
 261
 262    /* CACHE_NEW_VS_PROG */
 263    key->vp_nr_outputs = brw->vs.prog_data->nr_outputs;
 264
 265    /* The unique fragment program ID */
 266    key->program_string_id = brw->curr.fragment_shader->id;
 267 }
 268
 269
 270 static int brw_prepare_wm_prog(struct brw_context *brw)
 271 {
 272    struct brw_wm_prog_key key;
 273    struct brw_fragment_shader *fs = brw->curr.fragment_shader;
 274
 275    brw_wm_populate_key(brw, &key);
 276
 277    /* Make an early check for the key.
 278     */
 279    brw->sws->bo_unreference(brw->wm.prog_bo);
 280    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 281                                       &key, sizeof(key),
 282                                       NULL, 0,
 283                                       &brw->wm.prog_data);
 284    if (brw->wm.prog_bo == NULL)
 285       return do_wm_prog(brw, fs, &key);
 286
 287    return 0;
 288 }
 289
 290
 291 const struct brw_tracked_state brw_wm_prog = {
 292    .dirty = {
 293       .mesa  = (PIPE_NEW_FRAGMENT_SHADER |
 294                 PIPE_NEW_DEPTH_STENCIL_ALPHA |
 295                 PIPE_NEW_RAST |
 296                 PIPE_NEW_BOUND_TEXTURES),
 297       .brw   = (BRW_NEW_WM_INPUT_DIMENSIONS |
 298                 BRW_NEW_REDUCED_PRIMITIVE),
 299       .cache = CACHE_NEW_VS_PROG,
 300    },
 301    .prepare = brw_prepare_wm_prog
 302 };
 303