src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_util.h"
  34 #include "brw_wm.h"
  35 #include "brw_state.h"
  36
  37
  38 /** Return number of src args for given instruction */
  39 GLuint brw_wm_nr_args( GLuint opcode )
  40 {
  41    switch (opcode) {
  42    case WM_FRONTFACING:
  43    case WM_PIXELXY:
  44       return 0;
  45    case WM_CINTERP:
  46    case WM_WPOSXY:
  47    case WM_DELTAXY:
  48       return 1;
  49    case WM_LINTERP:
  50    case WM_PIXELW:
  51       return 2;
  52    case WM_FB_WRITE:
  53    case WM_PINTERP:
  54       return 3;
  55    default:
  56       assert(opcode < MAX_OPCODE);
  57       return _mesa_num_inst_src_regs(opcode);
  58    }
  59 }
  60
  61
  62 GLuint brw_wm_is_scalar_result( GLuint opcode )
  63 {
  64    switch (opcode) {
  65    case OPCODE_COS:
  66    case OPCODE_EX2:
  67    case OPCODE_LG2:
  68    case OPCODE_POW:
  69    case OPCODE_RCP:
  70    case OPCODE_RSQ:
  71    case OPCODE_SIN:
  72    case OPCODE_DP3:
  73    case OPCODE_DP4:
  74    case OPCODE_DPH:
  75    case OPCODE_DST:
  76       return 1;
  77
  78    default:
  79       return 0;
  80    }
  81 }
  82
  83
  84 /**
  85  * Do GPU code generation for non-GLSL shader.  non-GLSL shaders have
  86  * no flow control instructions so we can more readily do SSA-style
  87  * optimizations.
  88  */
  89 static void
  90 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
  91 {
  92    /* Augment fragment program.  Add instructions for pre- and
  93     * post-fragment-program tasks such as interpolation and fogging.
  94     */
  95    brw_wm_pass_fp(c);
  96
  97    /* Translate to intermediate representation.  Build register usage
  98     * chains.
  99     */
 100    brw_wm_pass0(c);
 101
 102    /* Dead code removal.
 103     */
 104    brw_wm_pass1(c);
 105
 106    /* Register allocation.
 107     * Divide by two because we operate on 16 pixels at a time and require
 108     * two GRF entries for each logical shader register.
 109     */
 110    c->grf_limit = BRW_WM_MAX_GRF / 2;
 111
 112    brw_wm_pass2(c);
 113
 114    /* how many general-purpose registers are used */
 115    c->prog_data.total_grf = c->max_wm_grf;
 116
 117    /* Scratch space is used for register spilling */
 118    if (c->last_scratch) {
 119       c->prog_data.total_scratch = c->last_scratch + 0x40;
 120    }
 121    else {
 122       c->prog_data.total_scratch = 0;
 123    }
 124
 125    /* Emit GEN4 code.
 126     */
 127    brw_wm_emit(c);
 128 }
 129
 130
 131 /**
 132  * All Mesa program -> GPU code generation goes through this function.
 133  * Depending on the instructions used (i.e. flow control instructions)
 134  * we'll use one of two code generators.
 135  */
 136 static void do_wm_prog( struct brw_context *brw,
 137                         struct brw_fragment_program *fp,
 138                         struct brw_wm_prog_key *key)
 139 {
 140    struct brw_wm_compile *c;
 141    const GLuint *program;
 142    GLuint program_size;
 143
 144    c = brw->wm.compile_data;
 145    if (c == NULL) {
 146       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 147       c = brw->wm.compile_data;
 148       if (c == NULL) {
 149          /* Ouch - big out of memory problem.  Can't continue
 150           * without triggering a segfault, no way to signal,
 151           * so just return.
 152           */
 153          return;
 154       }
 155    } else {
 156       memset(c, 0, sizeof(*brw->wm.compile_data));
 157    }
 158    memcpy(&c->key, key, sizeof(*key));
 159
 160    c->fp = fp;
 161    c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
 162
 163    brw_init_compile(brw, &c->func);
 164
 165    /* temporary sanity check assertion */
 166    ASSERT(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
 167
 168    /*
 169     * Shader which use GLSL features such as flow control are handled
 170     * differently from "simple" shaders.
 171     */
 172    if (fp->isGLSL) {
 173       c->dispatch_width = 8;
 174       brw_wm_glsl_emit(brw, c);
 175    }
 176    else {
 177       c->dispatch_width = 16;
 178       brw_wm_non_glsl_emit(brw, c);
 179    }
 180
 181    if (INTEL_DEBUG & DEBUG_WM)
 182       fprintf(stderr, "\n");
 183
 184    /* get the program
 185     */
 186    program = brw_get_program(&c->func, &program_size);
 187
 188    brw->sws->bo_unreference(brw->wm.prog_bo);
 189    brw->wm.prog_bo = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 190                                        &c->key, sizeof(c->key),
 191                                        NULL, 0,
 192                                        program, program_size,
 193                                        &c->prog_data,
 194                                        &brw->wm.prog_data );
 195 }
 196
 197
 198
 199 static void brw_wm_populate_key( struct brw_context *brw,
 200                                  struct brw_wm_prog_key *key )
 201 {
 202    /* BRW_NEW_FRAGMENT_PROGRAM */
 203    const struct brw_fragment_program *fp =
 204       (struct brw_fragment_program *)brw->fragment_program;
 205    GLboolean uses_depth = (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
 206    GLuint lookup = 0;
 207    GLuint line_aa;
 208    GLuint i;
 209
 210    memset(key, 0, sizeof(*key));
 211
 212    /* Build the index for table lookup
 213     */
 214    /* _NEW_COLOR */
 215    if (fp->program.UsesKill ||
 216        ctx->Color.AlphaEnabled)
 217       lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 218
 219    if (fp->program.Base.OutputsWritten & (1<<FRAG_RESULT_DEPTH))
 220       lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 221
 222    /* _NEW_DEPTH */
 223    if (ctx->Depth.Test)
 224       lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
 225
 226    if (ctx->Depth.Test &&
 227        ctx->Depth.Mask) /* ?? */
 228       lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
 229
 230    /* _NEW_STENCIL */
 231    if (ctx->Stencil._Enabled) {
 232       lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
 233
 234       if (ctx->Stencil.WriteMask[0] ||
 235           ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
 236          lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
 237    }
 238
 239    line_aa = AA_NEVER;
 240
 241    /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
 242    if (ctx->Line.SmoothFlag) {
 243       if (brw->intel.reduced_primitive == GL_LINES) {
 244          line_aa = AA_ALWAYS;
 245       }
 246       else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
 247          if (ctx->Polygon.FrontMode == GL_LINE) {
 248             line_aa = AA_SOMETIMES;
 249
 250             if (ctx->Polygon.BackMode == GL_LINE ||
 251                 (ctx->Polygon.CullFlag &&
 252                  ctx->Polygon.CullFaceMode == GL_BACK))
 253                line_aa = AA_ALWAYS;
 254          }
 255          else if (ctx->Polygon.BackMode == GL_LINE) {
 256             line_aa = AA_SOMETIMES;
 257
 258             if ((ctx->Polygon.CullFlag &&
 259                  ctx->Polygon.CullFaceMode == GL_FRONT))
 260                line_aa = AA_ALWAYS;
 261          }
 262       }
 263    }
 264
 265    brw_wm_lookup_iz(line_aa,
 266                     lookup,
 267                     uses_depth,
 268                     key);
 269
 270    /* Revisit this, figure out if it's really useful, and either push
 271     * it into the state tracker so that everyone benefits (use to
 272     * create fs varients with TEX rather than TXP), or discard.
 273     */
 274    key->proj_attrib_mask = ~0; /*brw->wm.input_size_masks[4-1];*/
 275
 276    /* PIPE_NEW_RAST */
 277    key->flat_shade = brw->rast.flat_shade;
 278
 279    /* This can be determined by looking at the INTERP mode each input decl.
 280     */
 281    key->linear_color = 0;
 282
 283    /* _NEW_TEXTURE */
 284    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 285       if (i < brw->nr_textures) {
 286          const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
 287          const struct gl_texture_object *t = unit->_Current;
 288          const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 289
 290          if (img->InternalFormat == GL_YCBCR_MESA) {
 291             key->yuvtex_mask |= 1 << i;
 292             if (img->TexFormat->MesaFormat == MESA_FORMAT_YCBCR)
 293                key->yuvtex_swap_mask |= 1 << i;
 294          }
 295
 296          key->tex_swizzles[i] = t->_Swizzle;
 297
 298          if (0)
 299             key->shadowtex_mask |= 1<<i;
 300       }
 301       else {
 302          key->tex_swizzles[i] = SWIZZLE_NOOP;
 303       }
 304    }
 305
 306
 307    /* _NEW_FRAMEBUFFER */
 308    if (brw->intel.driDrawable != NULL) {
 309       key->drawable_height = brw->fb.cbufs[0].height;
 310    }
 311
 312    /* CACHE_NEW_VS_PROG */
 313    key->vp_outputs_written = brw->vs.prog_data->outputs_written; /* bitmask */
 314
 315    /* The unique fragment program ID */
 316    key->program_string_id = fp->id;
 317 }
 318
 319
 320 static void brw_prepare_wm_prog(struct brw_context *brw)
 321 {
 322    struct brw_wm_prog_key key;
 323    struct brw_fragment_program *fp = (struct brw_fragment_program *)
 324       brw->fragment_program;
 325
 326    brw_wm_populate_key(brw, &key);
 327
 328    /* Make an early check for the key.
 329     */
 330    brw->sws->bo_unreference(brw->wm.prog_bo);
 331    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 332                                       &key, sizeof(key),
 333                                       NULL, 0,
 334                                       &brw->wm.prog_data);
 335    if (brw->wm.prog_bo == NULL)
 336       do_wm_prog(brw, fp, &key);
 337 }
 338
 339
 340 const struct brw_tracked_state brw_wm_prog = {
 341    .dirty = {
 342       .mesa  = (_NEW_COLOR |
 343                 _NEW_DEPTH |
 344                 _NEW_HINT |
 345                 _NEW_STENCIL |
 346                 _NEW_POLYGON |
 347                 _NEW_LINE |
 348                 _NEW_LIGHT |
 349                 _NEW_BUFFERS |
 350                 _NEW_TEXTURE),
 351       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 352                 BRW_NEW_WM_INPUT_DIMENSIONS |
 353                 BRW_NEW_REDUCED_PRIMITIVE),
 354       .cache = CACHE_NEW_VS_PROG,
 355    },
 356    .prepare = brw_prepare_wm_prog
 357 };
 358