src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31 #include "pipe/p_error.h"
  32
  33 #include "tgsi/tgsi_info.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_screen.h"
  37 #include "brw_util.h"
  38 #include "brw_wm.h"
  39 #include "brw_state.h"
  40 #include "brw_debug.h"
  41 #include "brw_pipe_rast.h"
  42
  43
  44 /** Return number of src args for given instruction */
  45 GLuint brw_wm_nr_args( GLuint opcode )
  46 {
  47    switch (opcode) {
  48    case WM_FRONTFACING:
  49    case WM_PIXELXY:
  50       return 0;
  51    case WM_CINTERP:
  52    case WM_WPOSXY:
  53    case WM_DELTAXY:
  54       return 1;
  55    case WM_LINTERP:
  56    case WM_PIXELW:
  57       return 2;
  58    case WM_FB_WRITE:
  59    case WM_PINTERP:
  60       return 3;
  61    default:
  62       assert(opcode < MAX_OPCODE);
  63       return tgsi_get_opcode_info(opcode)->num_src;
  64    }
  65 }
  66
  67
  68 GLuint brw_wm_is_scalar_result( GLuint opcode )
  69 {
  70    switch (opcode) {
  71    case TGSI_OPCODE_COS:
  72    case TGSI_OPCODE_EX2:
  73    case TGSI_OPCODE_LG2:
  74    case TGSI_OPCODE_POW:
  75    case TGSI_OPCODE_RCP:
  76    case TGSI_OPCODE_RSQ:
  77    case TGSI_OPCODE_SIN:
  78    case TGSI_OPCODE_DP3:
  79    case TGSI_OPCODE_DP4:
  80    case TGSI_OPCODE_DPH:
  81    case TGSI_OPCODE_DST:
  82       return 1;
  83
  84    default:
  85       return 0;
  86    }
  87 }
  88
  89
  90 /**
  91  * Do GPU code generation for shaders without flow control.  Shaders
  92  * without flow control instructions can more readily be analysed for
  93  * SSA-style optimizations.
  94  */
  95 static void
  96 brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c)
  97 {
  98    /* Augment fragment program.  Add instructions for pre- and
  99     * post-fragment-program tasks such as interpolation and fogging.
 100     */
 101    brw_wm_pass_fp(c);
 102
 103    /* Translate to intermediate representation.  Build register usage
 104     * chains.
 105     */
 106    brw_wm_pass0(c);
 107
 108    /* Dead code removal.
 109     */
 110    brw_wm_pass1(c);
 111
 112    /* Register allocation.
 113     * Divide by two because we operate on 16 pixels at a time and require
 114     * two GRF entries for each logical shader register.
 115     */
 116    c->grf_limit = BRW_WM_MAX_GRF / 2;
 117
 118    brw_wm_pass2(c);
 119
 120    /* how many general-purpose registers are used */
 121    c->prog_data.total_grf = c->max_wm_grf;
 122
 123    /* Scratch space is used for register spilling */
 124    if (c->last_scratch) {
 125       c->prog_data.total_scratch = c->last_scratch + 0x40;
 126    }
 127    else {
 128       c->prog_data.total_scratch = 0;
 129    }
 130
 131    /* Emit GEN4 code.
 132     */
 133    brw_wm_emit(c);
 134 }
 135
 136
 137 /**
 138  * All Mesa program -> GPU code generation goes through this function.
 139  * Depending on the instructions used (i.e. flow control instructions)
 140  * we'll use one of two code generators.
 141  */
 142 static int do_wm_prog( struct brw_context *brw,
 143                         struct brw_fragment_shader *fp,
 144                         struct brw_wm_prog_key *key)
 145 {
 146    struct brw_wm_compile *c;
 147    const GLuint *program;
 148    GLuint program_size;
 149
 150    c = brw->wm.compile_data;
 151    if (c == NULL) {
 152       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 153       c = brw->wm.compile_data;
 154       if (c == NULL) {
 155          /* Ouch - big out of memory problem.  Can't continue
 156           * without triggering a segfault, no way to signal,
 157           * so just return.
 158           */
 159          return PIPE_ERROR_OUT_OF_MEMORY;
 160       }
 161    } else {
 162       memset(c, 0, sizeof(*brw->wm.compile_data));
 163    }
 164    memcpy(&c->key, key, sizeof(*key));
 165
 166    c->fp = fp;
 167    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 168
 169    brw_init_compile(brw, &c->func);
 170
 171    /* temporary sanity check assertion */
 172    assert(fp->has_flow_control == brw_wm_has_flow_control(c->fp));
 173
 174    /*
 175     * Shader which use GLSL features such as flow control are handled
 176     * differently from "simple" shaders.
 177     */
 178    if (fp->has_flow_control) {
 179       c->dispatch_width = 8;
 180       /* XXX: GLSL support
 181        */
 182       exit(1);
 183       //brw_wm_branching_shader_emit(brw, c);
 184    }
 185    else {
 186       c->dispatch_width = 16;
 187       brw_wm_linear_shader_emit(brw, c);
 188    }
 189
 190    if (BRW_DEBUG & DEBUG_WM)
 191       debug_printf("\n");
 192
 193    /* get the program
 194     */
 195    program = brw_get_program(&c->func, &program_size);
 196
 197    brw->sws->bo_unreference(brw->wm.prog_bo);
 198    brw->wm.prog_bo = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 199                                        &c->key, sizeof(c->key),
 200                                        NULL, 0,
 201                                        program, program_size,
 202                                        &c->prog_data,
 203                                        &brw->wm.prog_data );
 204
 205    return 0;
 206 }
 207
 208
 209
 210 static void brw_wm_populate_key( struct brw_context *brw,
 211                                  struct brw_wm_prog_key *key )
 212 {
 213    unsigned lookup, line_aa;
 214    unsigned i;
 215
 216    memset(key, 0, sizeof(*key));
 217
 218    /* PIPE_NEW_FRAGMENT_SHADER
 219     * PIPE_NEW_DEPTH_STENCIL_ALPHA
 220     */
 221    lookup = (brw->curr.zstencil->iz_lookup |
 222              brw->curr.fragment_shader->iz_lookup);
 223
 224
 225    /* PIPE_NEW_RAST
 226     * BRW_NEW_REDUCED_PRIMITIVE
 227     */
 228    switch (brw->reduced_primitive) {
 229    case PIPE_PRIM_POINTS:
 230       line_aa = AA_NEVER;
 231       break;
 232    case PIPE_PRIM_LINES:
 233       line_aa = AA_ALWAYS;
 234       break;
 235    default:
 236       line_aa = brw->curr.rast->unfilled_aa_line;
 237       break;
 238    }
 239
 240    brw_wm_lookup_iz(line_aa,
 241                     lookup,
 242                     brw->curr.fragment_shader->uses_depth,
 243                     key);
 244
 245    /* PIPE_NEW_RAST */
 246    key->flat_shade = brw->curr.rast->templ.flatshade;
 247
 248
 249    /* PIPE_NEW_BOUND_TEXTURES */
 250    for (i = 0; i < brw->curr.num_textures; i++) {
 251       const struct brw_texture *tex = brw_texture(brw->curr.texture[i]);
 252
 253       if (tex->base.format == PIPE_FORMAT_YCBCR)
 254          key->yuvtex_mask |= 1 << i;
 255
 256       if (tex->base.format == PIPE_FORMAT_YCBCR_REV)
 257          key->yuvtex_swap_mask |= 1 << i;
 258
 259       /* XXX: shadow texture
 260        */
 261       /* key->shadowtex_mask |= 1<<i; */
 262    }
 263
 264    /* CACHE_NEW_VS_PROG */
 265    key->vp_nr_outputs = brw->vs.prog_data->nr_outputs;
 266
 267    /* The unique fragment program ID */
 268    key->program_string_id = brw->curr.fragment_shader->id;
 269 }
 270
 271
 272 static int brw_prepare_wm_prog(struct brw_context *brw)
 273 {
 274    struct brw_wm_prog_key key;
 275    struct brw_fragment_shader *fs = brw->curr.fragment_shader;
 276
 277    brw_wm_populate_key(brw, &key);
 278
 279    /* Make an early check for the key.
 280     */
 281    brw->sws->bo_unreference(brw->wm.prog_bo);
 282    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 283                                       &key, sizeof(key),
 284                                       NULL, 0,
 285                                       &brw->wm.prog_data);
 286    if (brw->wm.prog_bo == NULL)
 287       return do_wm_prog(brw, fs, &key);
 288
 289    return 0;
 290 }
 291
 292
 293 const struct brw_tracked_state brw_wm_prog = {
 294    .dirty = {
 295       .mesa  = (PIPE_NEW_FRAGMENT_SHADER |
 296                 PIPE_NEW_DEPTH_STENCIL_ALPHA |
 297                 PIPE_NEW_RAST |
 298                 PIPE_NEW_BOUND_TEXTURES),
 299       .brw   = (BRW_NEW_WM_INPUT_DIMENSIONS |
 300                 BRW_NEW_REDUCED_PRIMITIVE),
 301       .cache = CACHE_NEW_VS_PROG,
 302    },
 303    .prepare = brw_prepare_wm_prog
 304 };
 305