src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "tgsi/tgsi_info.h"
  33
  34 #include "brw_context.h"
  35 #include "brw_util.h"
  36 #include "brw_wm.h"
  37 #include "brw_state.h"
  38 #include "brw_debug.h"
  39
  40
  41 /** Return number of src args for given instruction */
  42 GLuint brw_wm_nr_args( GLuint opcode )
  43 {
  44    switch (opcode) {
  45    case WM_FRONTFACING:
  46    case WM_PIXELXY:
  47       return 0;
  48    case WM_CINTERP:
  49    case WM_WPOSXY:
  50    case WM_DELTAXY:
  51       return 1;
  52    case WM_LINTERP:
  53    case WM_PIXELW:
  54       return 2;
  55    case WM_FB_WRITE:
  56    case WM_PINTERP:
  57       return 3;
  58    default:
  59       assert(opcode < MAX_OPCODE);
  60       return tgsi_get_opcode_info(opcode)->num_src;
  61    }
  62 }
  63
  64
  65 GLuint brw_wm_is_scalar_result( GLuint opcode )
  66 {
  67    switch (opcode) {
  68    case TGSI_OPCODE_COS:
  69    case TGSI_OPCODE_EX2:
  70    case TGSI_OPCODE_LG2:
  71    case TGSI_OPCODE_POW:
  72    case TGSI_OPCODE_RCP:
  73    case TGSI_OPCODE_RSQ:
  74    case TGSI_OPCODE_SIN:
  75    case TGSI_OPCODE_DP3:
  76    case TGSI_OPCODE_DP4:
  77    case TGSI_OPCODE_DPH:
  78    case TGSI_OPCODE_DST:
  79       return 1;
  80
  81    default:
  82       return 0;
  83    }
  84 }
  85
  86
  87 /**
  88  * Do GPU code generation for non-GLSL shader.  non-GLSL shaders have
  89  * no flow control instructions so we can more readily do SSA-style
  90  * optimizations.
  91  */
  92 static void
  93 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
  94 {
  95    /* Augment fragment program.  Add instructions for pre- and
  96     * post-fragment-program tasks such as interpolation and fogging.
  97     */
  98    brw_wm_pass_fp(c);
  99
 100    /* Translate to intermediate representation.  Build register usage
 101     * chains.
 102     */
 103    brw_wm_pass0(c);
 104
 105    /* Dead code removal.
 106     */
 107    brw_wm_pass1(c);
 108
 109    /* Register allocation.
 110     * Divide by two because we operate on 16 pixels at a time and require
 111     * two GRF entries for each logical shader register.
 112     */
 113    c->grf_limit = BRW_WM_MAX_GRF / 2;
 114
 115    brw_wm_pass2(c);
 116
 117    /* how many general-purpose registers are used */
 118    c->prog_data.total_grf = c->max_wm_grf;
 119
 120    /* Scratch space is used for register spilling */
 121    if (c->last_scratch) {
 122       c->prog_data.total_scratch = c->last_scratch + 0x40;
 123    }
 124    else {
 125       c->prog_data.total_scratch = 0;
 126    }
 127
 128    /* Emit GEN4 code.
 129     */
 130    brw_wm_emit(c);
 131 }
 132
 133
 134 /**
 135  * All Mesa program -> GPU code generation goes through this function.
 136  * Depending on the instructions used (i.e. flow control instructions)
 137  * we'll use one of two code generators.
 138  */
 139 static void do_wm_prog( struct brw_context *brw,
 140                         struct brw_fragment_shader *fp,
 141                         struct brw_wm_prog_key *key)
 142 {
 143    struct brw_wm_compile *c;
 144    const GLuint *program;
 145    GLuint program_size;
 146
 147    c = brw->wm.compile_data;
 148    if (c == NULL) {
 149       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 150       c = brw->wm.compile_data;
 151       if (c == NULL) {
 152          /* Ouch - big out of memory problem.  Can't continue
 153           * without triggering a segfault, no way to signal,
 154           * so just return.
 155           */
 156          return;
 157       }
 158    } else {
 159       memset(c, 0, sizeof(*brw->wm.compile_data));
 160    }
 161    memcpy(&c->key, key, sizeof(*key));
 162
 163    c->fp = fp;
 164    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 165
 166    brw_init_compile(brw, &c->func);
 167
 168    /* temporary sanity check assertion */
 169    assert(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
 170
 171    /*
 172     * Shader which use GLSL features such as flow control are handled
 173     * differently from "simple" shaders.
 174     */
 175    if (fp->isGLSL) {
 176       c->dispatch_width = 8;
 177       brw_wm_glsl_emit(brw, c);
 178    }
 179    else {
 180       c->dispatch_width = 16;
 181       brw_wm_non_glsl_emit(brw, c);
 182    }
 183
 184    if (BRW_DEBUG & DEBUG_WM)
 185       debug_printf("\n");
 186
 187    /* get the program
 188     */
 189    program = brw_get_program(&c->func, &program_size);
 190
 191    brw->sws->bo_unreference(brw->wm.prog_bo);
 192    brw->wm.prog_bo = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 193                                        &c->key, sizeof(c->key),
 194                                        NULL, 0,
 195                                        program, program_size,
 196                                        &c->prog_data,
 197                                        &brw->wm.prog_data );
 198 }
 199
 200
 201
 202 static void brw_wm_populate_key( struct brw_context *brw,
 203                                  struct brw_wm_prog_key *key )
 204 {
 205    /* BRW_NEW_FRAGMENT_PROGRAM */
 206    const struct brw_fragment_program *fp = brw->curr.fragment_shader;
 207    GLboolean uses_depth = (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
 208    GLuint lookup = 0;
 209    GLuint line_aa;
 210    GLuint i;
 211
 212    memset(key, 0, sizeof(*key));
 213
 214    /* Build the index for table lookup
 215     */
 216    /* _NEW_COLOR */
 217    if (fp->program.UsesKill ||
 218        ctx->Color.AlphaEnabled)
 219       lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 220
 221    if (fp->program.Base.OutputsWritten & (1<<FRAG_RESULT_DEPTH))
 222       lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 223
 224    /* _NEW_DEPTH */
 225    if (ctx->Depth.Test)
 226       lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
 227
 228    if (ctx->Depth.Test &&
 229        ctx->Depth.Mask) /* ?? */
 230       lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
 231
 232    /* _NEW_STENCIL */
 233    if (ctx->Stencil._Enabled) {
 234       lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
 235
 236       if (ctx->Stencil.WriteMask[0] ||
 237           ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
 238          lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
 239    }
 240
 241    line_aa = AA_NEVER;
 242
 243    /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
 244    if (ctx->Line.SmoothFlag) {
 245       if (brw->intel.reduced_primitive == GL_LINES) {
 246          line_aa = AA_ALWAYS;
 247       }
 248       else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
 249          if (ctx->Polygon.FrontMode == GL_LINE) {
 250             line_aa = AA_SOMETIMES;
 251
 252             if (ctx->Polygon.BackMode == GL_LINE ||
 253                 (ctx->Polygon.CullFlag &&
 254                  ctx->Polygon.CullFaceMode == GL_BACK))
 255                line_aa = AA_ALWAYS;
 256          }
 257          else if (ctx->Polygon.BackMode == GL_LINE) {
 258             line_aa = AA_SOMETIMES;
 259
 260             if ((ctx->Polygon.CullFlag &&
 261                  ctx->Polygon.CullFaceMode == GL_FRONT))
 262                line_aa = AA_ALWAYS;
 263          }
 264       }
 265    }
 266
 267    brw_wm_lookup_iz(line_aa,
 268                     lookup,
 269                     uses_depth,
 270                     key);
 271
 272    /* Revisit this, figure out if it's really useful, and either push
 273     * it into the state tracker so that everyone benefits (use to
 274     * create fs varients with TEX rather than TXP), or discard.
 275     */
 276    key->proj_attrib_mask = ~0; /*brw->wm.input_size_masks[4-1];*/
 277
 278    /* PIPE_NEW_RAST */
 279    key->flat_shade = brw->rast.flat_shade;
 280
 281    /* This can be determined by looking at the INTERP mode each input decl.
 282     */
 283    key->linear_color = 0;
 284
 285    /* _NEW_TEXTURE */
 286    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 287       if (i < brw->nr_textures) {
 288          const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
 289          const struct gl_texture_object *t = unit->_Current;
 290          const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 291
 292          if (img->InternalFormat == GL_YCBCR_MESA) {
 293             key->yuvtex_mask |= 1 << i;
 294             if (img->TexFormat->MesaFormat == MESA_FORMAT_YCBCR)
 295                key->yuvtex_swap_mask |= 1 << i;
 296          }
 297
 298          key->tex_swizzles[i] = t->_Swizzle;
 299
 300          if (0)
 301             key->shadowtex_mask |= 1<<i;
 302       }
 303       else {
 304          key->tex_swizzles[i] = SWIZZLE_NOOP;
 305       }
 306    }
 307
 308
 309    /* _NEW_FRAMEBUFFER */
 310    if (brw->intel.driDrawable != NULL) {
 311       key->drawable_height = brw->fb.cbufs[0].height;
 312    }
 313
 314    /* CACHE_NEW_VS_PROG */
 315    key->vp_nr_outputs_written = brw->vs.prog_data->nr_outputs_written;
 316
 317    /* The unique fragment program ID */
 318    key->program_string_id = fp->id;
 319 }
 320
 321
 322 static void brw_prepare_wm_prog(struct brw_context *brw)
 323 {
 324    struct brw_wm_prog_key key;
 325    struct brw_fragment_program *fp = (struct brw_fragment_program *)
 326       brw->fragment_program;
 327
 328    brw_wm_populate_key(brw, &key);
 329
 330    /* Make an early check for the key.
 331     */
 332    brw->sws->bo_unreference(brw->wm.prog_bo);
 333    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 334                                       &key, sizeof(key),
 335                                       NULL, 0,
 336                                       &brw->wm.prog_data);
 337    if (brw->wm.prog_bo == NULL)
 338       do_wm_prog(brw, fp, &key);
 339 }
 340
 341
 342 const struct brw_tracked_state brw_wm_prog = {
 343    .dirty = {
 344       .mesa  = (_NEW_COLOR |
 345                 _NEW_DEPTH |
 346                 _NEW_HINT |
 347                 _NEW_STENCIL |
 348                 _NEW_POLYGON |
 349                 _NEW_LINE |
 350                 _NEW_LIGHT |
 351                 _NEW_BUFFERS |
 352                 _NEW_TEXTURE),
 353       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 354                 BRW_NEW_WM_INPUT_DIMENSIONS |
 355                 BRW_NEW_REDUCED_PRIMITIVE),
 356       .cache = CACHE_NEW_VS_PROG,
 357    },
 358    .prepare = brw_prepare_wm_prog
 359 };
 360