src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31 #include "pipe/p_error.h"
  32
  33 #include "tgsi/tgsi_info.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_screen.h"
  37 #include "brw_util.h"
  38 #include "brw_wm.h"
  39 #include "brw_state.h"
  40 #include "brw_debug.h"
  41 #include "brw_pipe_rast.h"
  42
  43
  44 /** Return number of src args for given instruction */
  45 GLuint brw_wm_nr_args( GLuint opcode )
  46 {
  47    switch (opcode) {
  48    case WM_FRONTFACING:
  49    case WM_PIXELXY:
  50       return 0;
  51    case WM_CINTERP:
  52    case WM_WPOSXY:
  53    case WM_DELTAXY:
  54       return 1;
  55    case WM_LINTERP:
  56    case WM_PIXELW:
  57       return 2;
  58    case WM_FB_WRITE:
  59    case WM_PINTERP:
  60       return 3;
  61    default:
  62       assert(opcode < MAX_OPCODE);
  63       return tgsi_get_opcode_info(opcode)->num_src;
  64    }
  65 }
  66
  67
  68 GLuint brw_wm_is_scalar_result( GLuint opcode )
  69 {
  70    switch (opcode) {
  71    case TGSI_OPCODE_COS:
  72    case TGSI_OPCODE_EX2:
  73    case TGSI_OPCODE_LG2:
  74    case TGSI_OPCODE_POW:
  75    case TGSI_OPCODE_RCP:
  76    case TGSI_OPCODE_RSQ:
  77    case TGSI_OPCODE_SIN:
  78    case TGSI_OPCODE_DP3:
  79    case TGSI_OPCODE_DP4:
  80    case TGSI_OPCODE_DPH:
  81    case TGSI_OPCODE_DST:
  82       return 1;
  83
  84    default:
  85       return 0;
  86    }
  87 }
  88
  89
  90 /**
  91  * Do GPU code generation for shaders without flow control.  Shaders
  92  * without flow control instructions can more readily be analysed for
  93  * SSA-style optimizations.
  94  */
  95 static void
  96 brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c)
  97 {
  98    /* Augment fragment program.  Add instructions for pre- and
  99     * post-fragment-program tasks such as interpolation and fogging.
 100     */
 101    brw_wm_pass_fp(c);
 102
 103    /* Translate to intermediate representation.  Build register usage
 104     * chains.
 105     */
 106    brw_wm_pass0(c);
 107
 108    /* Dead code removal.
 109     */
 110    brw_wm_pass1(c);
 111
 112    /* Register allocation.
 113     * Divide by two because we operate on 16 pixels at a time and require
 114     * two GRF entries for each logical shader register.
 115     */
 116    c->grf_limit = BRW_WM_MAX_GRF / 2;
 117
 118    brw_wm_pass2(c);
 119
 120    /* how many general-purpose registers are used */
 121    c->prog_data.total_grf = c->max_wm_grf;
 122
 123    /* Scratch space is used for register spilling */
 124    if (c->last_scratch) {
 125       c->prog_data.total_scratch = c->last_scratch + 0x40;
 126    }
 127    else {
 128       c->prog_data.total_scratch = 0;
 129    }
 130
 131    /* Emit GEN4 code.
 132     */
 133    brw_wm_emit(c);
 134 }
 135
 136
 137 /**
 138  * All Mesa program -> GPU code generation goes through this function.
 139  * Depending on the instructions used (i.e. flow control instructions)
 140  * we'll use one of two code generators.
 141  */
 142 static int do_wm_prog( struct brw_context *brw,
 143                         struct brw_fragment_shader *fp,
 144                         struct brw_wm_prog_key *key)
 145 {
 146    struct brw_wm_compile *c;
 147    const GLuint *program;
 148    GLuint program_size;
 149
 150    c = brw->wm.compile_data;
 151    if (c == NULL) {
 152       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 153       c = brw->wm.compile_data;
 154       if (c == NULL) {
 155          /* Ouch - big out of memory problem.  Can't continue
 156           * without triggering a segfault, no way to signal,
 157           * so just return.
 158           */
 159          return PIPE_ERROR_OUT_OF_MEMORY;
 160       }
 161    } else {
 162       memset(c, 0, sizeof(*brw->wm.compile_data));
 163    }
 164    memcpy(&c->key, key, sizeof(*key));
 165
 166    c->fp = fp;
 167    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 168
 169    brw_init_compile(brw, &c->func);
 170
 171    /* temporary sanity check assertion */
 172    assert(fp->has_flow_control == brw_wm_has_flow_control(c->fp));
 173
 174    /*
 175     * Shader which use GLSL features such as flow control are handled
 176     * differently from "simple" shaders.
 177     */
 178    if (fp->has_flow_control) {
 179       c->dispatch_width = 8;
 180       brw_wm_branching_shader_emit(brw, c);
 181    }
 182    else {
 183       c->dispatch_width = 16;
 184       brw_wm_linear_shader_emit(brw, c);
 185    }
 186
 187    if (BRW_DEBUG & DEBUG_WM)
 188       debug_printf("\n");
 189
 190    /* get the program
 191     */
 192    program = brw_get_program(&c->func, &program_size);
 193
 194    brw->sws->bo_unreference(brw->wm.prog_bo);
 195    brw->wm.prog_bo = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 196                                        &c->key, sizeof(c->key),
 197                                        NULL, 0,
 198                                        program, program_size,
 199                                        &c->prog_data,
 200                                        &brw->wm.prog_data );
 201
 202    return 0;
 203 }
 204
 205
 206
 207 static void brw_wm_populate_key( struct brw_context *brw,
 208                                  struct brw_wm_prog_key *key )
 209 {
 210    unsigned lookup, line_aa;
 211    unsigned i;
 212
 213    memset(key, 0, sizeof(*key));
 214
 215    /* PIPE_NEW_FRAGMENT_SHADER
 216     * PIPE_NEW_DEPTH_STENCIL_ALPHA
 217     */
 218    lookup = (brw->curr.zstencil->iz_lookup |
 219              brw->curr.fragment_shader->iz_lookup);
 220
 221
 222    /* PIPE_NEW_RAST
 223     * BRW_NEW_REDUCED_PRIMITIVE
 224     */
 225    switch (brw->reduced_primitive) {
 226    case PIPE_PRIM_POINTS:
 227       line_aa = AA_NEVER;
 228       break;
 229    case PIPE_PRIM_LINES:
 230       line_aa = AA_ALWAYS;
 231       break;
 232    default:
 233       line_aa = brw->curr.rast->unfilled_aa_line;
 234       break;
 235    }
 236
 237    brw_wm_lookup_iz(line_aa,
 238                     lookup,
 239                     brw->curr.fragment_shader->uses_depth,
 240                     key);
 241
 242    /* Revisit this, figure out if it's really useful, and either push
 243     * it into the state tracker so that everyone benefits (use to
 244     * create fs varients with TEX rather than TXP), or discard.
 245     */
 246    key->proj_attrib_mask = ~0; /*brw->wm.input_size_masks[4-1];*/
 247
 248    /* PIPE_NEW_RAST */
 249    key->flat_shade = brw->curr.rast->templ.flatshade;
 250
 251    /* This can be determined by looking at the INTERP mode each input decl.
 252     */
 253    key->linear_attrib_mask = 0;
 254
 255    /* PIPE_NEW_BOUND_TEXTURES */
 256    for (i = 0; i < brw->curr.num_textures; i++) {
 257       const struct brw_texture *tex = brw->curr.texture[i];
 258
 259       if (tex->base.format == PIPE_FORMAT_YCBCR)
 260          key->yuvtex_mask |= 1 << i;
 261
 262       if (tex->base.format == PIPE_FORMAT_YCBCR_REV)
 263          key->yuvtex_swap_mask |= 1 << i;
 264
 265       /* XXX: shadow texture
 266        */
 267       /* key->shadowtex_mask |= 1<<i; */
 268    }
 269
 270    /* CACHE_NEW_VS_PROG */
 271    key->vp_nr_outputs = brw->vs.prog_data->nr_outputs;
 272
 273    /* The unique fragment program ID */
 274    key->program_string_id = brw->curr.fragment_shader->id;
 275 }
 276
 277
 278 static int brw_prepare_wm_prog(struct brw_context *brw)
 279 {
 280    struct brw_wm_prog_key key;
 281    struct brw_fragment_shader *fs = brw->curr.fragment_shader;
 282
 283    brw_wm_populate_key(brw, &key);
 284
 285    /* Make an early check for the key.
 286     */
 287    brw->sws->bo_unreference(brw->wm.prog_bo);
 288    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 289                                       &key, sizeof(key),
 290                                       NULL, 0,
 291                                       &brw->wm.prog_data);
 292    if (brw->wm.prog_bo == NULL)
 293       return do_wm_prog(brw, fs, &key);
 294
 295    return 0;
 296 }
 297
 298
 299 const struct brw_tracked_state brw_wm_prog = {
 300    .dirty = {
 301       .mesa  = (PIPE_NEW_FRAGMENT_SHADER |
 302                 PIPE_NEW_DEPTH_STENCIL_ALPHA |
 303                 PIPE_NEW_RAST |
 304                 PIPE_NEW_BOUND_TEXTURES),
 305       .brw   = (BRW_NEW_WM_INPUT_DIMENSIONS |
 306                 BRW_NEW_REDUCED_PRIMITIVE),
 307       .cache = CACHE_NEW_VS_PROG,
 308    },
 309    .prepare = brw_prepare_wm_prog
 310 };
 311