src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31 #include "tgsi/tgsi_info.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_screen.h"
  35 #include "brw_util.h"
  36 #include "brw_wm.h"
  37 #include "brw_state.h"
  38 #include "brw_debug.h"
  39 #include "brw_pipe_rast.h"
  40
  41
  42 /** Return number of src args for given instruction */
  43 GLuint brw_wm_nr_args( GLuint opcode )
  44 {
  45    switch (opcode) {
  46    case WM_FRONTFACING:
  47    case WM_PIXELXY:
  48       return 0;
  49    case WM_CINTERP:
  50    case WM_WPOSXY:
  51    case WM_DELTAXY:
  52       return 1;
  53    case WM_LINTERP:
  54    case WM_PIXELW:
  55       return 2;
  56    case WM_FB_WRITE:
  57    case WM_PINTERP:
  58       return 3;
  59    default:
  60       assert(opcode < MAX_OPCODE);
  61       return tgsi_get_opcode_info(opcode)->num_src;
  62    }
  63 }
  64
  65
  66 GLuint brw_wm_is_scalar_result( GLuint opcode )
  67 {
  68    switch (opcode) {
  69    case TGSI_OPCODE_COS:
  70    case TGSI_OPCODE_EX2:
  71    case TGSI_OPCODE_LG2:
  72    case TGSI_OPCODE_POW:
  73    case TGSI_OPCODE_RCP:
  74    case TGSI_OPCODE_RSQ:
  75    case TGSI_OPCODE_SIN:
  76    case TGSI_OPCODE_DP3:
  77    case TGSI_OPCODE_DP4:
  78    case TGSI_OPCODE_DPH:
  79    case TGSI_OPCODE_DST:
  80       return 1;
  81
  82    default:
  83       return 0;
  84    }
  85 }
  86
  87
  88 /**
  89  * Do GPU code generation for shaders without flow control.  Shaders
  90  * without flow control instructions can more readily be analysed for
  91  * SSA-style optimizations.
  92  */
  93 static void
  94 brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c)
  95 {
  96    /* Augment fragment program.  Add instructions for pre- and
  97     * post-fragment-program tasks such as interpolation and fogging.
  98     */
  99    brw_wm_pass_fp(c);
 100
 101    /* Translate to intermediate representation.  Build register usage
 102     * chains.
 103     */
 104    brw_wm_pass0(c);
 105
 106    /* Dead code removal.
 107     */
 108    brw_wm_pass1(c);
 109
 110    /* Register allocation.
 111     * Divide by two because we operate on 16 pixels at a time and require
 112     * two GRF entries for each logical shader register.
 113     */
 114    c->grf_limit = BRW_WM_MAX_GRF / 2;
 115
 116    brw_wm_pass2(c);
 117
 118    /* how many general-purpose registers are used */
 119    c->prog_data.total_grf = c->max_wm_grf;
 120
 121    /* Scratch space is used for register spilling */
 122    if (c->last_scratch) {
 123       c->prog_data.total_scratch = c->last_scratch + 0x40;
 124    }
 125    else {
 126       c->prog_data.total_scratch = 0;
 127    }
 128
 129    /* Emit GEN4 code.
 130     */
 131    brw_wm_emit(c);
 132 }
 133
 134
 135 /**
 136  * All Mesa program -> GPU code generation goes through this function.
 137  * Depending on the instructions used (i.e. flow control instructions)
 138  * we'll use one of two code generators.
 139  */
 140 static enum pipe_error do_wm_prog( struct brw_context *brw,
 141                                    struct brw_fragment_shader *fp,
 142                                    struct brw_wm_prog_key *key,
 143                                    struct brw_winsys_buffer **bo_out)
 144 {
 145    enum pipe_error ret;
 146    struct brw_wm_compile *c;
 147    const GLuint *program;
 148    GLuint program_size;
 149
 150    if (brw->wm.compile_data == NULL) {
 151       brw->wm.compile_data = MALLOC(sizeof(*brw->wm.compile_data));
 152       if (!brw->wm.compile_data)
 153          return PIPE_ERROR_OUT_OF_MEMORY;
 154    }
 155
 156    c = brw->wm.compile_data;
 157    memset(c, 0, sizeof *c);
 158
 159    c->key = *key;
 160    c->fp = fp;
 161    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 162
 163    brw_init_compile(brw, &c->func);
 164
 165    /*
 166     * Shader which use GLSL features such as flow control are handled
 167     * differently from "simple" shaders.
 168     */
 169    if (fp->has_flow_control) {
 170       c->dispatch_width = 8;
 171       /* XXX: GLSL support
 172        */
 173       exit(1);
 174       //brw_wm_branching_shader_emit(brw, c);
 175    }
 176    else {
 177       c->dispatch_width = 16;
 178       brw_wm_linear_shader_emit(brw, c);
 179    }
 180
 181    if (BRW_DEBUG & DEBUG_WM)
 182       debug_printf("\n");
 183
 184    /* get the program
 185     */
 186    ret = brw_get_program(&c->func, &program, &program_size);
 187    if (ret)
 188       return ret;
 189
 190    ret = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 191                            &c->key, sizeof(c->key),
 192                            NULL, 0,
 193                            program, program_size,
 194                            &c->prog_data,
 195                            &brw->wm.prog_data,
 196                            bo_out );
 197    if (ret)
 198       return ret;
 199
 200    return PIPE_OK;
 201 }
 202
 203
 204
 205 static void brw_wm_populate_key( struct brw_context *brw,
 206                                  struct brw_wm_prog_key *key )
 207 {
 208    unsigned lookup, line_aa;
 209    unsigned i;
 210
 211    memset(key, 0, sizeof(*key));
 212
 213    /* PIPE_NEW_FRAGMENT_SHADER
 214     * PIPE_NEW_DEPTH_STENCIL_ALPHA
 215     */
 216    lookup = (brw->curr.zstencil->iz_lookup |
 217              brw->curr.fragment_shader->iz_lookup);
 218
 219
 220    /* PIPE_NEW_RAST
 221     * BRW_NEW_REDUCED_PRIMITIVE
 222     */
 223    switch (brw->reduced_primitive) {
 224    case PIPE_PRIM_POINTS:
 225       line_aa = AA_NEVER;
 226       break;
 227    case PIPE_PRIM_LINES:
 228       line_aa = (brw->curr.rast->templ.line_smooth ?
 229                  AA_ALWAYS : AA_NEVER);
 230       break;
 231    default:
 232       line_aa = brw->curr.rast->unfilled_aa_line;
 233       break;
 234    }
 235
 236    brw_wm_lookup_iz(line_aa,
 237                     lookup,
 238                     brw->curr.fragment_shader->uses_depth,
 239                     key);
 240
 241    /* PIPE_NEW_RAST */
 242    key->flat_shade = brw->curr.rast->templ.flatshade;
 243
 244
 245    /* PIPE_NEW_BOUND_TEXTURES */
 246    for (i = 0; i < brw->curr.num_textures; i++) {
 247       const struct brw_texture *tex = brw_texture(brw->curr.texture[i]);
 248
 249       if (tex->base.format == PIPE_FORMAT_YCBCR)
 250          key->yuvtex_mask |= 1 << i;
 251
 252       if (tex->base.format == PIPE_FORMAT_YCBCR_REV)
 253          key->yuvtex_swap_mask |= 1 << i;
 254
 255       /* XXX: shadow texture
 256        */
 257       /* key->shadowtex_mask |= 1<<i; */
 258    }
 259
 260    /* CACHE_NEW_VS_PROG */
 261    key->vp_nr_outputs = brw->vs.prog_data->nr_outputs;
 262
 263    key->nr_cbufs = brw->curr.fb.nr_cbufs;
 264
 265    key->nr_inputs = brw->curr.fragment_shader->info.num_inputs;
 266
 267    /* The unique fragment program ID */
 268    key->program_string_id = brw->curr.fragment_shader->id;
 269 }
 270
 271
 272 static enum pipe_error brw_prepare_wm_prog(struct brw_context *brw)
 273 {
 274    struct brw_wm_prog_key key;
 275    struct brw_fragment_shader *fs = brw->curr.fragment_shader;
 276    enum pipe_error ret;
 277
 278    brw_wm_populate_key(brw, &key);
 279
 280    /* Make an early check for the key.
 281     */
 282    if (brw_search_cache(&brw->cache, BRW_WM_PROG,
 283                         &key, sizeof(key),
 284                         NULL, 0,
 285                         &brw->wm.prog_data,
 286                         &brw->wm.prog_bo))
 287       return PIPE_OK;
 288
 289    ret = do_wm_prog(brw, fs, &key, &brw->wm.prog_bo);
 290    if (ret)
 291       return ret;
 292
 293    return PIPE_OK;
 294 }
 295
 296
 297 const struct brw_tracked_state brw_wm_prog = {
 298    .dirty = {
 299       .mesa  = (PIPE_NEW_FRAGMENT_SHADER |
 300                 PIPE_NEW_DEPTH_STENCIL_ALPHA |
 301                 PIPE_NEW_RAST |
 302                 PIPE_NEW_NR_CBUFS |
 303                 PIPE_NEW_BOUND_TEXTURES),
 304       .brw   = (BRW_NEW_WM_INPUT_DIMENSIONS |
 305                 BRW_NEW_REDUCED_PRIMITIVE),
 306       .cache = CACHE_NEW_VS_PROG,
 307    },
 308    .prepare = brw_prepare_wm_prog
 309 };
 310