src/gallium/drivers/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36 #include "brw_context.h"
  37 #include "brw_eu.h"
  38
  39 #define SATURATE (1<<5)
  40
  41 /* A big lookup table is used to figure out which and how many
  42  * additional regs will inserted before the main payload in the WM
  43  * program execution.  These mainly relate to depth and stencil
  44  * processing and the early-depth-test optimization.
  45  */
  46 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  47 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  48 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  49 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  51 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  52 #define IZ_BIT_MAX                  0x40
  53
  54 #define AA_NEVER     0
  55 #define AA_SOMETIMES 1
  56 #define AA_ALWAYS    2
  57
  58 struct brw_wm_prog_key {
  59    GLuint source_depth_reg:3;
  60    GLuint aa_dest_stencil_reg:3;
  61    GLuint dest_depth_reg:3;
  62    GLuint nr_depth_regs:3;
  63    GLuint computes_depth:1;
  64    GLuint source_depth_to_render_target:1;
  65    GLuint flat_shade:1;
  66    GLuint runtime_check_aads_emit:1;
  67
  68    GLuint shadowtex_mask:16;
  69    GLuint yuvtex_mask:16;
  70    GLuint yuvtex_swap_mask:16;  /* UV swaped */
  71
  72    GLuint vp_nr_outputs:6;
  73    GLuint nr_inputs:6;
  74    GLuint nr_cbufs:3;
  75    GLuint has_flow_control:1;
  76
  77    GLuint program_string_id;
  78 };
  79
  80
  81 /* A bit of a glossary:
  82  *
  83  * brw_wm_value: A computed value or program input.  Values are
  84  * constant, they are created once and are never modified.  When a
  85  * fragment program register is written or overwritten, new values are
  86  * created fresh, preserving the rule that values are constant.
  87  *
  88  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  89  * instruction or as a program output, that is tracked with an
  90  * instance of this struct.  All references to a value occur after it
  91  * is created.  After the last reference, a value is dead and can be
  92  * discarded.
  93  *
  94  * brw_wm_grf: Represents a physical hardware register.  May be either
  95  * empty or hold a value.  Register allocation is the process of
  96  * assigning values to grf registers.  This occurs in pass2 and the
  97  * brw_wm_grf struct is not used before that.
  98  *
  99  * Fragment program registers: These are time-varying constructs that
 100  * are hard to reason about and which we translate away in pass0.  A
 101  * single fragment program register element (eg. temp[0].x) will be
 102  * translated to one or more brw_wm_value structs, one for each time
 103  * that temp[0].x is written to during the program.
 104  */
 105
 106
 107
 108 /* Used in pass2 to track register allocation.
 109  */
 110 struct brw_wm_grf {
 111    struct brw_wm_value *value;
 112    GLuint nextuse;
 113 };
 114
 115 struct brw_wm_value {
 116    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 117    struct brw_wm_ref *lastuse;
 118    struct brw_wm_grf *resident;
 119    GLuint contributes_to_output:1;
 120    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 121 };
 122
 123 struct brw_wm_ref {
 124    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 125    struct brw_wm_value *value;
 126    struct brw_wm_ref *prevuse;
 127    GLuint unspill_reg:7;        /* unspill to reg */
 128    GLuint emitted:1;
 129    GLuint insn:24;
 130 };
 131
 132 struct brw_wm_imm_ref {
 133    const struct brw_wm_ref *ref;
 134    GLfloat imm1f;
 135 };
 136
 137
 138 struct brw_wm_instruction {
 139    struct brw_wm_value *dst[4];
 140    struct brw_wm_ref *src[3][4];
 141    GLuint opcode:8;
 142    GLuint saturate:1;
 143    GLuint writemask:4;
 144    GLuint tex_unit:4;   /* texture/sampler unit for texture instructions */
 145    GLuint tex_target:4; /* TGSI_TEXTURE_x for texture instructions*/
 146    GLuint eot:1;        /* End of thread indicator for FB_WRITE*/
 147    GLuint target:10;    /* target binding table index for FB_WRITE*/
 148 };
 149
 150
 151 #define BRW_WM_MAX_INSN  2048
 152 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 153 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 154 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 155 #define BRW_WM_MAX_PARAM 256
 156 #define BRW_WM_MAX_CONST 256
 157 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
 158 #define BRW_WM_MAX_SUBROUTINE 16
 159
 160
 161 /* New opcodes to track internal operations required for WM unit.
 162  * These are added early so that the registers used can be tracked,
 163  * freed and reused like those of other instructions.
 164  */
 165 #define MAX_OPCODE        TGSI_OPCODE_LAST
 166 #define WM_PIXELXY        (MAX_OPCODE)
 167 #define WM_DELTAXY        (MAX_OPCODE + 1)
 168 #define WM_PIXELW         (MAX_OPCODE + 2)
 169 #define WM_LINTERP        (MAX_OPCODE + 3)
 170 #define WM_PINTERP        (MAX_OPCODE + 4)
 171 #define WM_CINTERP        (MAX_OPCODE + 5)
 172 #define WM_WPOSXY         (MAX_OPCODE + 6)
 173 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 174 #define WM_FRONTFACING    (MAX_OPCODE + 8)
 175 #define MAX_WM_OPCODE     (MAX_OPCODE + 9)
 176
 177 #define BRW_FILE_PAYLOAD   (TGSI_FILE_COUNT)
 178 #define PAYLOAD_DEPTH      (PIPE_MAX_SHADER_INPUTS) /* ?? */
 179
 180 #define X    0
 181 #define Y    1
 182 #define Z    2
 183 #define W    3
 184 #define GET_SWZ(swz, comp) (((swz) >> ((comp)*2)) & 0x3)
 185
 186
 187 struct brw_fp_src {
 188    unsigned file:4;
 189    unsigned index:16;
 190    unsigned swizzle:8;
 191    unsigned indirect:1;
 192    unsigned negate:1;
 193    unsigned abs:1;
 194 };
 195
 196 struct brw_fp_dst {
 197    unsigned file:4;
 198    unsigned index:16;
 199    unsigned writemask:4;
 200    unsigned indirect:1;
 201    unsigned saturate:1;
 202 };
 203
 204 struct brw_fp_instruction {
 205    struct brw_fp_dst dst;
 206    struct brw_fp_src src[3];
 207    unsigned opcode:8;
 208    unsigned tex_unit:4;
 209    unsigned tex_target:4;
 210    unsigned target:10;          /* destination surface for FB_WRITE */
 211    unsigned eot:1;              /* mark last instruction (usually FB_WRITE) */
 212 };
 213
 214
 215 struct brw_wm_compile {
 216    struct brw_compile func;
 217    struct brw_wm_prog_key key;
 218    struct brw_wm_prog_data prog_data;
 219
 220    struct brw_fragment_shader *fp;
 221
 222    GLfloat (*env_param)[4];
 223
 224    enum {
 225       START,
 226       PASS2_DONE
 227    } state;
 228
 229    /* Initial pass - translate fp instructions to fp instructions,
 230     * simplifying and adding instructions for interpolation and
 231     * framebuffer writes.
 232     */
 233    struct {
 234       GLfloat v[4];
 235       unsigned nr;
 236    } immediate[BRW_WM_MAX_CONST+3];
 237    GLuint nr_immediates;
 238
 239    struct brw_fp_instruction fp_instructions[BRW_WM_MAX_INSN];
 240    GLuint nr_fp_insns;
 241    GLuint fp_temp;
 242    GLuint fp_interp_emitted;
 243    GLuint fp_fragcolor_emitted;
 244    GLuint fp_first_internal_temp;
 245
 246    struct brw_fp_src fp_pixel_xy;
 247    struct brw_fp_src fp_delta_xy;
 248    struct brw_fp_src fp_pixel_w;
 249
 250
 251    /* Subsequent passes using SSA representation:
 252     */
 253    struct brw_wm_value vreg[BRW_WM_MAX_VREG];
 254    GLuint nr_vreg;
 255
 256    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 257    GLuint nr_creg;
 258
 259    struct {
 260       struct brw_wm_value depth[4]; /* includes r0/r1 */
 261       struct brw_wm_value input_interp[PIPE_MAX_SHADER_INPUTS];
 262    } payload;
 263
 264
 265    const struct brw_wm_ref *pass0_fp_reg[BRW_FILE_PAYLOAD+1][256][4];
 266
 267    struct brw_wm_ref undef_ref;
 268    struct brw_wm_value undef_value;
 269
 270    struct brw_wm_ref refs[BRW_WM_MAX_REF];
 271    GLuint nr_refs;
 272
 273    struct brw_wm_instruction instruction[BRW_WM_MAX_INSN];
 274    GLuint nr_insns;
 275
 276    struct brw_wm_imm_ref imm_ref[BRW_WM_MAX_CONST];
 277    GLuint nr_imm_refs;
 278
 279    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 280
 281    GLuint grf_limit;
 282    GLuint max_wm_grf;
 283    GLuint last_scratch;
 284
 285    GLuint cur_inst;  /**< index of current instruction */
 286
 287    GLboolean out_of_regs;  /**< ran out of GRF registers? */
 288
 289    /** Mapping from Mesa registers to hardware registers */
 290    struct {
 291       GLboolean inited;
 292       struct brw_reg reg;
 293    } wm_regs[BRW_FILE_PAYLOAD+1][256][4];
 294
 295    GLboolean used_grf[BRW_WM_MAX_GRF];
 296    GLuint first_free_grf;
 297    struct brw_reg stack;
 298    struct brw_reg emit_mask_reg;
 299    GLuint tmp_regs[BRW_WM_MAX_GRF];
 300    GLuint tmp_index;
 301    GLuint tmp_max;
 302    GLuint subroutines[BRW_WM_MAX_SUBROUTINE];
 303    GLuint dispatch_width;
 304
 305    /** we may need up to 3 constants per instruction (if use_const_buffer) */
 306    struct {
 307       GLint index;
 308       struct brw_reg reg;
 309    } current_const[3];
 310
 311    GLuint error;
 312 };
 313
 314
 315 GLuint brw_wm_nr_args( GLuint opcode );
 316 GLuint brw_wm_is_scalar_result( GLuint opcode );
 317
 318 int brw_wm_pass_fp( struct brw_wm_compile *c );
 319 void brw_wm_pass0( struct brw_wm_compile *c );
 320 void brw_wm_pass1( struct brw_wm_compile *c );
 321 void brw_wm_pass2( struct brw_wm_compile *c );
 322 void brw_wm_emit( struct brw_wm_compile *c );
 323
 324 void brw_wm_print_value( struct brw_wm_compile *c,
 325                          struct brw_wm_value *value );
 326
 327 void brw_wm_print_ref( struct brw_wm_compile *c,
 328                        struct brw_wm_ref *ref );
 329
 330 void brw_wm_print_insn( struct brw_wm_compile *c,
 331                         struct brw_wm_instruction *inst );
 332
 333 void brw_wm_print_program( struct brw_wm_compile *c,
 334                            const char *stage );
 335
 336 void brw_wm_lookup_iz( GLuint line_aa,
 337                        GLuint lookup,
 338                        GLboolean ps_uses_depth,
 339                        struct brw_wm_prog_key *key );
 340
 341 void brw_wm_branching_shader_emit(struct brw_context *brw, struct brw_wm_compile *c);
 342
 343 void emit_ddxy(struct brw_compile *p,
 344                const struct brw_reg *dst,
 345                GLuint mask,
 346                GLboolean is_ddx,
 347                const struct brw_reg *arg0);
 348
 349 #endif