src/gallium/drivers/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36 #include "brw_context.h"
  37 #include "brw_eu.h"
  38
  39 #define SATURATE (1<<5)
  40
  41 /* A big lookup table is used to figure out which and how many
  42  * additional regs will inserted before the main payload in the WM
  43  * program execution.  These mainly relate to depth and stencil
  44  * processing and the early-depth-test optimization.
  45  */
  46 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  47 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  48 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  49 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  51 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  52 #define IZ_BIT_MAX                  0x40
  53
  54 #define AA_NEVER     0
  55 #define AA_SOMETIMES 1
  56 #define AA_ALWAYS    2
  57
  58 struct brw_wm_prog_key {
  59    GLuint source_depth_reg:3;
  60    GLuint aa_dest_stencil_reg:3;
  61    GLuint dest_depth_reg:3;
  62    GLuint nr_depth_regs:3;
  63    GLuint computes_depth:1;
  64    GLuint source_depth_to_render_target:1;
  65    GLuint flat_shade:1;
  66    GLuint runtime_check_aads_emit:1;
  67
  68    GLuint shadowtex_mask:16;
  69    GLuint yuvtex_mask:16;
  70    GLuint yuvtex_swap_mask:16;  /* UV swaped */
  71
  72    GLuint vp_nr_outputs:6;
  73    GLuint nr_inputs:6;
  74    GLuint nr_cbufs:3;
  75    GLuint has_flow_control:1;
  76
  77    GLuint program_string_id;
  78 };
  79
  80
  81 /* A bit of a glossary:
  82  *
  83  * brw_wm_value: A computed value or program input.  Values are
  84  * constant, they are created once and are never modified.  When a
  85  * fragment program register is written or overwritten, new values are
  86  * created fresh, preserving the rule that values are constant.
  87  *
  88  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  89  * instruction or as a program output, that is tracked with an
  90  * instance of this struct.  All references to a value occur after it
  91  * is created.  After the last reference, a value is dead and can be
  92  * discarded.
  93  *
  94  * brw_wm_grf: Represents a physical hardware register.  May be either
  95  * empty or hold a value.  Register allocation is the process of
  96  * assigning values to grf registers.  This occurs in pass2 and the
  97  * brw_wm_grf struct is not used before that.
  98  *
  99  * Fragment program registers: These are time-varying constructs that
 100  * are hard to reason about and which we translate away in pass0.  A
 101  * single fragment program register element (eg. temp[0].x) will be
 102  * translated to one or more brw_wm_value structs, one for each time
 103  * that temp[0].x is written to during the program.
 104  */
 105
 106
 107
 108 /* Used in pass2 to track register allocation.
 109  */
 110 struct brw_wm_grf {
 111    struct brw_wm_value *value;
 112    GLuint nextuse;
 113 };
 114
 115 struct brw_wm_value {
 116    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 117    struct brw_wm_ref *lastuse;
 118    struct brw_wm_grf *resident;
 119    GLuint contributes_to_output:1;
 120    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 121 };
 122
 123 struct brw_wm_ref {
 124    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 125    struct brw_wm_value *value;
 126    struct brw_wm_ref *prevuse;
 127    GLuint unspill_reg:7;        /* unspill to reg */
 128    GLuint emitted:1;
 129    GLuint insn:24;
 130 };
 131
 132 struct brw_wm_instruction {
 133    struct brw_wm_value *dst[4];
 134    struct brw_wm_ref *src[3][4];
 135    GLuint opcode:8;
 136    GLuint saturate:1;
 137    GLuint writemask:4;
 138    GLuint sampler:4;
 139    GLuint tex_unit:4;   /* texture/sampler unit for texture instructions */
 140    GLuint target:4;     /* TGSI_TEXTURE_x for texture instructions,
 141                          * target binding table index for FB_WRITE
 142                          */
 143    GLuint eot:1;        /* End of thread indicator for FB_WRITE*/
 144 };
 145
 146
 147 #define BRW_WM_MAX_INSN  2048
 148 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 149 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 150 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 151 #define BRW_WM_MAX_PARAM 256
 152 #define BRW_WM_MAX_CONST 256
 153 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
 154 #define BRW_WM_MAX_SUBROUTINE 16
 155
 156
 157 /* New opcodes to track internal operations required for WM unit.
 158  * These are added early so that the registers used can be tracked,
 159  * freed and reused like those of other instructions.
 160  */
 161 #define MAX_OPCODE        TGSI_OPCODE_LAST
 162 #define WM_PIXELXY        (MAX_OPCODE)
 163 #define WM_DELTAXY        (MAX_OPCODE + 1)
 164 #define WM_PIXELW         (MAX_OPCODE + 2)
 165 #define WM_LINTERP        (MAX_OPCODE + 3)
 166 #define WM_PINTERP        (MAX_OPCODE + 4)
 167 #define WM_CINTERP        (MAX_OPCODE + 5)
 168 #define WM_WPOSXY         (MAX_OPCODE + 6)
 169 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 170 #define WM_FRONTFACING    (MAX_OPCODE + 8)
 171 #define MAX_WM_OPCODE     (MAX_OPCODE + 9)
 172
 173 #define BRW_FILE_PAYLOAD   (TGSI_FILE_COUNT)
 174 #define PAYLOAD_DEPTH      (PIPE_MAX_SHADER_INPUTS) /* ?? */
 175
 176 #define X    0
 177 #define Y    1
 178 #define Z    2
 179 #define W    3
 180
 181
 182 struct brw_fp_src {
 183    unsigned file:4;
 184    unsigned index:16;
 185    unsigned swizzle:8;
 186    unsigned indirect:1;
 187    unsigned negate:1;
 188    unsigned abs:1;
 189 };
 190
 191 struct brw_fp_dst {
 192    unsigned file:4;
 193    unsigned index:16;
 194    unsigned writemask:4;
 195    unsigned indirect:1;
 196    unsigned saturate:1;
 197 };
 198
 199 struct brw_fp_instruction {
 200    struct brw_fp_dst dst;
 201    struct brw_fp_src src[3];
 202    unsigned opcode:8;
 203    unsigned target:8; /* XXX: special usage for FB_WRITE */
 204    unsigned tex_unit:4;
 205    unsigned sampler:4;
 206    unsigned pad:8;
 207 };
 208
 209
 210 struct brw_wm_compile {
 211    struct brw_compile func;
 212    struct brw_wm_prog_key key;
 213    struct brw_wm_prog_data prog_data;
 214
 215    struct brw_fragment_shader *fp;
 216
 217    GLfloat (*env_param)[4];
 218
 219    enum {
 220       START,
 221       PASS2_DONE
 222    } state;
 223
 224    /* Initial pass - translate fp instructions to fp instructions,
 225     * simplifying and adding instructions for interpolation and
 226     * framebuffer writes.
 227     */
 228    struct {
 229       GLfloat v[4];
 230       unsigned nr;
 231    } immediate[BRW_WM_MAX_CONST+3];
 232    GLuint nr_immediates;
 233
 234    struct brw_fp_instruction fp_instructions[BRW_WM_MAX_INSN];
 235    GLuint nr_fp_insns;
 236    GLuint fp_temp;
 237    GLuint fp_interp_emitted;
 238    GLuint fp_fragcolor_emitted;
 239    GLuint fp_first_internal_temp;
 240
 241    struct brw_fp_src fp_pixel_xy;
 242    struct brw_fp_src fp_delta_xy;
 243    struct brw_fp_src fp_pixel_w;
 244
 245
 246    /* Subsequent passes using SSA representation:
 247     */
 248    struct brw_wm_value vreg[BRW_WM_MAX_VREG];
 249    GLuint nr_vreg;
 250
 251    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 252    GLuint nr_creg;
 253
 254    struct {
 255       struct brw_wm_value depth[4]; /* includes r0/r1 */
 256       struct brw_wm_value input_interp[PIPE_MAX_SHADER_INPUTS];
 257    } payload;
 258
 259
 260    const struct brw_wm_ref *pass0_fp_reg[BRW_FILE_PAYLOAD+1][256][4];
 261
 262    struct brw_wm_ref undef_ref;
 263    struct brw_wm_value undef_value;
 264
 265    struct brw_wm_ref refs[BRW_WM_MAX_REF];
 266    GLuint nr_refs;
 267
 268    struct brw_wm_instruction instruction[BRW_WM_MAX_INSN];
 269    GLuint nr_insns;
 270
 271    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 272
 273    GLuint grf_limit;
 274    GLuint max_wm_grf;
 275    GLuint last_scratch;
 276
 277    GLuint cur_inst;  /**< index of current instruction */
 278
 279    GLboolean out_of_regs;  /**< ran out of GRF registers? */
 280
 281    /** Mapping from Mesa registers to hardware registers */
 282    struct {
 283       GLboolean inited;
 284       struct brw_reg reg;
 285    } wm_regs[BRW_FILE_PAYLOAD+1][256][4];
 286
 287    GLboolean used_grf[BRW_WM_MAX_GRF];
 288    GLuint first_free_grf;
 289    struct brw_reg stack;
 290    struct brw_reg emit_mask_reg;
 291    GLuint tmp_regs[BRW_WM_MAX_GRF];
 292    GLuint tmp_index;
 293    GLuint tmp_max;
 294    GLuint subroutines[BRW_WM_MAX_SUBROUTINE];
 295    GLuint dispatch_width;
 296
 297    /** we may need up to 3 constants per instruction (if use_const_buffer) */
 298    struct {
 299       GLint index;
 300       struct brw_reg reg;
 301    } current_const[3];
 302
 303    GLuint error;
 304 };
 305
 306
 307 GLuint brw_wm_nr_args( GLuint opcode );
 308 GLuint brw_wm_is_scalar_result( GLuint opcode );
 309
 310 int brw_wm_pass_fp( struct brw_wm_compile *c );
 311 void brw_wm_pass0( struct brw_wm_compile *c );
 312 void brw_wm_pass1( struct brw_wm_compile *c );
 313 void brw_wm_pass2( struct brw_wm_compile *c );
 314 void brw_wm_emit( struct brw_wm_compile *c );
 315
 316 void brw_wm_print_value( struct brw_wm_compile *c,
 317                          struct brw_wm_value *value );
 318
 319 void brw_wm_print_ref( struct brw_wm_compile *c,
 320                        struct brw_wm_ref *ref );
 321
 322 void brw_wm_print_insn( struct brw_wm_compile *c,
 323                         struct brw_wm_instruction *inst );
 324
 325 void brw_wm_print_program( struct brw_wm_compile *c,
 326                            const char *stage );
 327
 328 void brw_wm_print_fp_program( struct brw_wm_compile *c,
 329                               const char *stage );
 330
 331 void brw_wm_lookup_iz( GLuint line_aa,
 332                        GLuint lookup,
 333                        GLboolean ps_uses_depth,
 334                        struct brw_wm_prog_key *key );
 335
 336 void brw_wm_branching_shader_emit(struct brw_context *brw, struct brw_wm_compile *c);
 337
 338 void emit_ddxy(struct brw_compile *p,
 339                const struct brw_reg *dst,
 340                GLuint mask,
 341                GLboolean is_ddx,
 342                const struct brw_reg *arg0);
 343
 344 #endif