src/gallium/drivers/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36 #include "brw_context.h"
  37 #include "brw_eu.h"
  38
  39 #define SATURATE (1<<5)
  40
  41 /* A big lookup table is used to figure out which and how many
  42  * additional regs will inserted before the main payload in the WM
  43  * program execution.  These mainly relate to depth and stencil
  44  * processing and the early-depth-test optimization.
  45  */
  46 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  47 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  48 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  49 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  51 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  52 #define IZ_BIT_MAX                  0x40
  53
  54 #define AA_NEVER     0
  55 #define AA_SOMETIMES 1
  56 #define AA_ALWAYS    2
  57
  58 struct brw_wm_prog_key {
  59    unsigned proj_attrib_mask;    /**< one bit per fragment program attribute */
  60    unsigned linear_attrib_mask;  /**< linear interpolation vs perspective interp */
  61
  62    GLuint source_depth_reg:3;
  63    GLuint aa_dest_stencil_reg:3;
  64    GLuint dest_depth_reg:3;
  65    GLuint nr_depth_regs:3;
  66    GLuint computes_depth:1;
  67    GLuint source_depth_to_render_target:1;
  68    GLuint flat_shade:1;
  69    GLuint runtime_check_aads_emit:1;
  70
  71    GLuint shadowtex_mask:16;
  72    GLuint yuvtex_mask:16;
  73    GLuint yuvtex_swap_mask:16;  /* UV swaped */
  74
  75    GLuint vp_nr_outputs:6;
  76    GLuint nr_cbufs:3;
  77    GLuint has_flow_control:1;
  78
  79    GLuint program_string_id;
  80 };
  81
  82
  83 /* A bit of a glossary:
  84  *
  85  * brw_wm_value: A computed value or program input.  Values are
  86  * constant, they are created once and are never modified.  When a
  87  * fragment program register is written or overwritten, new values are
  88  * created fresh, preserving the rule that values are constant.
  89  *
  90  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  91  * instruction or as a program output, that is tracked with an
  92  * instance of this struct.  All references to a value occur after it
  93  * is created.  After the last reference, a value is dead and can be
  94  * discarded.
  95  *
  96  * brw_wm_grf: Represents a physical hardware register.  May be either
  97  * empty or hold a value.  Register allocation is the process of
  98  * assigning values to grf registers.  This occurs in pass2 and the
  99  * brw_wm_grf struct is not used before that.
 100  *
 101  * Fragment program registers: These are time-varying constructs that
 102  * are hard to reason about and which we translate away in pass0.  A
 103  * single fragment program register element (eg. temp[0].x) will be
 104  * translated to one or more brw_wm_value structs, one for each time
 105  * that temp[0].x is written to during the program.
 106  */
 107
 108
 109
 110 /* Used in pass2 to track register allocation.
 111  */
 112 struct brw_wm_grf {
 113    struct brw_wm_value *value;
 114    GLuint nextuse;
 115 };
 116
 117 struct brw_wm_value {
 118    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 119    struct brw_wm_ref *lastuse;
 120    struct brw_wm_grf *resident;
 121    GLuint contributes_to_output:1;
 122    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 123 };
 124
 125 struct brw_wm_ref {
 126    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 127    struct brw_wm_value *value;
 128    struct brw_wm_ref *prevuse;
 129    GLuint unspill_reg:7;        /* unspill to reg */
 130    GLuint emitted:1;
 131    GLuint insn:24;
 132 };
 133
 134 struct brw_wm_imm_ref {
 135    const struct brw_wm_ref *ref;
 136    GLfloat imm1f;
 137 };
 138
 139
 140 struct brw_wm_instruction {
 141    struct brw_wm_value *dst[4];
 142    struct brw_wm_ref *src[3][4];
 143    GLuint opcode:8;
 144    GLuint saturate:1;
 145    GLuint writemask:4;
 146    GLuint tex_unit:4;   /* texture/sampler unit for texture instructions */
 147    GLuint tex_target:4; /* TGSI_TEXTURE_x for texture instructions*/
 148    GLuint eot:1;        /* End of thread indicator for FB_WRITE*/
 149    GLuint target:10;    /* target binding table index for FB_WRITE*/
 150 };
 151
 152
 153 #define BRW_WM_MAX_INSN  2048
 154 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 155 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 156 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 157 #define BRW_WM_MAX_PARAM 256
 158 #define BRW_WM_MAX_CONST 256
 159 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
 160 #define BRW_WM_MAX_SUBROUTINE 16
 161
 162
 163 /* New opcodes to track internal operations required for WM unit.
 164  * These are added early so that the registers used can be tracked,
 165  * freed and reused like those of other instructions.
 166  */
 167 #define MAX_OPCODE        TGSI_OPCODE_LAST
 168 #define WM_PIXELXY        (MAX_OPCODE)
 169 #define WM_DELTAXY        (MAX_OPCODE + 1)
 170 #define WM_PIXELW         (MAX_OPCODE + 2)
 171 #define WM_LINTERP        (MAX_OPCODE + 3)
 172 #define WM_PINTERP        (MAX_OPCODE + 4)
 173 #define WM_CINTERP        (MAX_OPCODE + 5)
 174 #define WM_WPOSXY         (MAX_OPCODE + 6)
 175 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 176 #define WM_FRONTFACING    (MAX_OPCODE + 8)
 177 #define MAX_WM_OPCODE     (MAX_OPCODE + 9)
 178
 179 #define BRW_FILE_PAYLOAD   (TGSI_FILE_COUNT)
 180 #define PAYLOAD_DEPTH      (PIPE_MAX_SHADER_INPUTS) /* ?? */
 181
 182
 183 struct brw_fp_src {
 184    unsigned file:4;
 185    unsigned index:16;
 186    unsigned swizzle:8;
 187    unsigned indirect:1;
 188    unsigned negate:1;
 189    unsigned abs:1;
 190 };
 191
 192 struct brw_fp_dst {
 193    unsigned file:4;
 194    unsigned index:16;
 195    unsigned writemask:4;
 196    unsigned indirect:1;
 197    unsigned saturate:1;
 198 };
 199
 200 struct brw_fp_instruction {
 201    struct brw_fp_dst dst;
 202    struct brw_fp_src src[3];
 203    unsigned opcode:8;
 204    unsigned tex_unit:4;
 205    unsigned tex_target:4;
 206    unsigned target:10;          /* destination surface for FB_WRITE */
 207    unsigned eot:1;              /* mark last instruction (usually FB_WRITE) */
 208 };
 209
 210
 211 struct brw_wm_compile {
 212    struct brw_compile func;
 213    struct brw_wm_prog_key key;
 214    struct brw_wm_prog_data prog_data;
 215
 216    struct brw_fragment_shader *fp;
 217
 218    GLfloat (*env_param)[4];
 219
 220    enum {
 221       START,
 222       PASS2_DONE
 223    } state;
 224
 225    /* Initial pass - translate fp instructions to fp instructions,
 226     * simplifying and adding instructions for interpolation and
 227     * framebuffer writes.
 228     */
 229    struct {
 230       GLfloat v[4];
 231       unsigned nr;
 232    } immediate[BRW_WM_MAX_CONST+3];
 233    GLuint nr_immediates;
 234
 235    struct brw_fp_instruction fp_instructions[BRW_WM_MAX_INSN];
 236    GLuint nr_fp_insns;
 237    GLuint fp_temp;
 238    GLuint fp_interp_emitted;
 239    GLuint fp_fragcolor_emitted;
 240    GLuint fp_first_internal_temp;
 241
 242    struct brw_fp_src fp_pixel_xy;
 243    struct brw_fp_src fp_delta_xy;
 244    struct brw_fp_src fp_pixel_w;
 245
 246
 247    /* Subsequent passes using SSA representation:
 248     */
 249    struct brw_wm_value vreg[BRW_WM_MAX_VREG];
 250    GLuint nr_vreg;
 251
 252    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 253    GLuint nr_creg;
 254
 255    struct {
 256       struct brw_wm_value depth[4]; /* includes r0/r1 */
 257       struct brw_wm_value input_interp[PIPE_MAX_SHADER_INPUTS];
 258    } payload;
 259
 260
 261    const struct brw_wm_ref *pass0_fp_reg[BRW_FILE_PAYLOAD+1][256][4];
 262
 263    struct brw_wm_ref undef_ref;
 264    struct brw_wm_value undef_value;
 265
 266    struct brw_wm_ref refs[BRW_WM_MAX_REF];
 267    GLuint nr_refs;
 268
 269    struct brw_wm_instruction instruction[BRW_WM_MAX_INSN];
 270    GLuint nr_insns;
 271
 272    struct brw_wm_imm_ref imm_ref[BRW_WM_MAX_CONST];
 273    GLuint nr_imm_refs;
 274
 275    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 276
 277    GLuint grf_limit;
 278    GLuint max_wm_grf;
 279    GLuint last_scratch;
 280
 281    GLuint cur_inst;  /**< index of current instruction */
 282
 283    GLboolean out_of_regs;  /**< ran out of GRF registers? */
 284
 285    /** Mapping from Mesa registers to hardware registers */
 286    struct {
 287       GLboolean inited;
 288       struct brw_reg reg;
 289    } wm_regs[BRW_FILE_PAYLOAD+1][256][4];
 290
 291    GLboolean used_grf[BRW_WM_MAX_GRF];
 292    GLuint first_free_grf;
 293    struct brw_reg stack;
 294    struct brw_reg emit_mask_reg;
 295    GLuint tmp_regs[BRW_WM_MAX_GRF];
 296    GLuint tmp_index;
 297    GLuint tmp_max;
 298    GLuint subroutines[BRW_WM_MAX_SUBROUTINE];
 299    GLuint dispatch_width;
 300
 301    /** we may need up to 3 constants per instruction (if use_const_buffer) */
 302    struct {
 303       GLint index;
 304       struct brw_reg reg;
 305    } current_const[3];
 306
 307    GLuint error;
 308 };
 309
 310
 311 GLuint brw_wm_nr_args( GLuint opcode );
 312 GLuint brw_wm_is_scalar_result( GLuint opcode );
 313
 314 int brw_wm_pass_fp( struct brw_wm_compile *c );
 315 void brw_wm_pass0( struct brw_wm_compile *c );
 316 void brw_wm_pass1( struct brw_wm_compile *c );
 317 void brw_wm_pass2( struct brw_wm_compile *c );
 318 void brw_wm_emit( struct brw_wm_compile *c );
 319
 320 void brw_wm_print_value( struct brw_wm_compile *c,
 321                          struct brw_wm_value *value );
 322
 323 void brw_wm_print_ref( struct brw_wm_compile *c,
 324                        struct brw_wm_ref *ref );
 325
 326 void brw_wm_print_insn( struct brw_wm_compile *c,
 327                         struct brw_wm_instruction *inst );
 328
 329 void brw_wm_print_program( struct brw_wm_compile *c,
 330                            const char *stage );
 331
 332 void brw_wm_lookup_iz( GLuint line_aa,
 333                        GLuint lookup,
 334                        GLboolean ps_uses_depth,
 335                        struct brw_wm_prog_key *key );
 336
 337 GLboolean brw_wm_has_flow_control(const struct brw_fragment_shader *fp);
 338 void brw_wm_branching_shader_emit(struct brw_context *brw, struct brw_wm_compile *c);
 339
 340 void emit_ddxy(struct brw_compile *p,
 341                const struct brw_reg *dst,
 342                GLuint mask,
 343                GLboolean is_ddx,
 344                const struct brw_reg *arg0);
 345
 346 #endif