2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
35 #include "brw_debug.h"
40 /***********************************************************************
43 static struct brw_wm_ref
*get_ref( struct brw_wm_compile
*c
)
45 assert(c
->nr_refs
< BRW_WM_MAX_REF
);
46 return &c
->refs
[c
->nr_refs
++];
49 static struct brw_wm_value
*get_value( struct brw_wm_compile
*c
)
51 assert(c
->nr_refs
< BRW_WM_MAX_VREG
);
52 return &c
->vreg
[c
->nr_vreg
++];
55 /** return pointer to a newly allocated instruction */
56 static struct brw_wm_instruction
*get_instruction( struct brw_wm_compile
*c
)
58 assert(c
->nr_insns
< BRW_WM_MAX_INSN
);
59 return &c
->instruction
[c
->nr_insns
++];
62 /***********************************************************************
65 /** Init the "undef" register */
66 static void pass0_init_undef( struct brw_wm_compile
*c
)
68 struct brw_wm_ref
*ref
= &c
->undef_ref
;
69 ref
->value
= &c
->undef_value
;
70 ref
->hw_reg
= brw_vec8_grf(0, 0);
75 /** Set a FP register to a value */
76 static void pass0_set_fpreg_value( struct brw_wm_compile
*c
,
80 struct brw_wm_value
*value
)
82 struct brw_wm_ref
*ref
= get_ref(c
);
84 ref
->hw_reg
= brw_vec8_grf(0, 0);
87 c
->pass0_fp_reg
[file
][idx
][component
] = ref
;
90 /** Set a FP register to a ref */
91 static void pass0_set_fpreg_ref( struct brw_wm_compile
*c
,
95 const struct brw_wm_ref
*src_ref
)
97 c
->pass0_fp_reg
[file
][idx
][component
] = src_ref
;
100 static const struct brw_wm_ref
*get_param_ref( struct brw_wm_compile
*c
,
104 GLuint i
= idx
* 4 + component
;
106 if (i
>= BRW_WM_MAX_PARAM
) {
107 debug_printf("%s: out of params\n", __FUNCTION__
);
108 c
->prog_data
.error
= 1;
112 struct brw_wm_ref
*ref
= get_ref(c
);
114 c
->nr_creg
= MAX2(c
->nr_creg
, (i
+16)/16);
116 /* Push the offsets into hw_reg. These will be added to the
117 * real register numbers once one is allocated in pass2.
119 ref
->hw_reg
= brw_vec1_grf((i
&8)?1:0, i
%8);
120 ref
->value
= &c
->creg
[i
/16];
131 /* Lookup our internal registers
133 static const struct brw_wm_ref
*pass0_get_reg( struct brw_wm_compile
*c
,
138 const struct brw_wm_ref
*ref
= c
->pass0_fp_reg
[file
][idx
][component
];
142 case TGSI_FILE_INPUT
:
143 case TGSI_FILE_TEMPORARY
:
144 case TGSI_FILE_OUTPUT
:
145 case BRW_FILE_PAYLOAD
:
146 /* should already be done?? */
149 case TGSI_FILE_CONSTANT
:
150 ref
= get_param_ref(c
,
151 c
->fp
->info
.immediate_count
+ idx
,
155 case TGSI_FILE_IMMEDIATE
:
156 ref
= get_param_ref(c
,
166 c
->pass0_fp_reg
[file
][idx
][component
] = ref
;
177 /***********************************************************************
178 * Straight translation to internal instruction format
181 static void pass0_set_dst( struct brw_wm_compile
*c
,
182 struct brw_wm_instruction
*out
,
183 const struct brw_fp_instruction
*inst
,
186 const struct brw_fp_dst dst
= inst
->dst
;
189 for (i
= 0; i
< 4; i
++) {
190 if (writemask
& (1<<i
)) {
191 out
->dst
[i
] = get_value(c
);
192 pass0_set_fpreg_value(c
, dst
.file
, dst
.index
, i
, out
->dst
[i
]);
196 out
->writemask
= writemask
;
200 static const struct brw_wm_ref
*get_fp_src_reg_ref( struct brw_wm_compile
*c
,
201 struct brw_fp_src src
,
204 return pass0_get_reg(c
, src
.file
, src
.index
, BRW_GET_SWZ(src
.swizzle
,i
));
208 static struct brw_wm_ref
*get_new_ref( struct brw_wm_compile
*c
,
209 struct brw_fp_src src
,
211 struct brw_wm_instruction
*insn
)
213 const struct brw_wm_ref
*ref
= get_fp_src_reg_ref(c
, src
, i
);
214 struct brw_wm_ref
*newref
= get_ref(c
);
216 newref
->value
= ref
->value
;
217 newref
->hw_reg
= ref
->hw_reg
;
220 newref
->insn
= insn
- c
->instruction
;
221 newref
->prevuse
= newref
->value
->lastuse
;
222 newref
->value
->lastuse
= newref
;
226 newref
->hw_reg
.negate
^= 1;
229 newref
->hw_reg
.negate
= 0;
230 newref
->hw_reg
.abs
= 1;
238 translate_insn(struct brw_wm_compile
*c
,
239 const struct brw_fp_instruction
*inst
)
241 struct brw_wm_instruction
*out
= get_instruction(c
);
242 GLuint writemask
= inst
->dst
.writemask
;
243 GLuint nr_args
= brw_wm_nr_args(inst
->opcode
);
246 /* Copy some data out of the instruction
248 out
->opcode
= inst
->opcode
;
249 out
->saturate
= inst
->dst
.saturate
;
250 out
->tex_unit
= inst
->tex_unit
;
251 out
->target
= inst
->target
;
255 out
->eot
= (inst
->opcode
== WM_FB_WRITE
&&
256 inst
->tex_unit
!= 0);
261 for (i
= 0; i
< nr_args
; i
++) {
262 for (j
= 0; j
< 4; j
++) {
263 out
->src
[i
][j
] = get_new_ref(c
, inst
->src
[i
], j
, out
);
269 pass0_set_dst(c
, out
, inst
, writemask
);
274 /***********************************************************************
275 * Optimize moves and swizzles away:
277 static void pass0_precalc_mov( struct brw_wm_compile
*c
,
278 const struct brw_fp_instruction
*inst
)
280 const struct brw_fp_dst dst
= inst
->dst
;
281 GLuint writemask
= dst
.writemask
;
282 struct brw_wm_ref
*refs
[4];
285 /* Get the effect of a MOV by manipulating our register table:
286 * First get all refs, then assign refs. This ensures that "in-place"
289 * are handled correctly. Previously, these two steps were done in
290 * one loop and the above case was incorrectly handled.
292 for (i
= 0; i
< 4; i
++) {
293 refs
[i
] = get_new_ref(c
, inst
->src
[0], i
, NULL
);
295 for (i
= 0; i
< 4; i
++) {
296 if (writemask
& (1 << i
)) {
297 pass0_set_fpreg_ref( c
, dst
.file
, dst
.index
, i
, refs
[i
]);
303 /* Initialize payload "registers".
305 static void pass0_init_payload( struct brw_wm_compile
*c
)
309 for (i
= 0; i
< 4; i
++) {
310 GLuint j
= i
>= c
->key
.nr_depth_regs
? 0 : i
;
311 pass0_set_fpreg_value( c
, BRW_FILE_PAYLOAD
, PAYLOAD_DEPTH
, i
,
312 &c
->payload
.depth
[j
] );
315 for (i
= 0; i
< c
->key
.nr_inputs
; i
++)
316 pass0_set_fpreg_value( c
, BRW_FILE_PAYLOAD
, i
, 0,
317 &c
->payload
.input_interp
[i
] );
321 /***********************************************************************
324 * Work forwards to give each calculated value a unique number. Where
325 * an instruction produces duplicate values (eg DP3), all are given
328 * Translate away swizzling and eliminate non-saturating moves.
330 * Translate instructions from our fp_instruction structs to our
331 * internal brw_wm_instruction representation.
333 void brw_wm_pass0( struct brw_wm_compile
*c
)
341 pass0_init_payload(c
);
343 for (insn
= 0; insn
< c
->nr_fp_insns
; insn
++) {
344 const struct brw_fp_instruction
*inst
= &c
->fp_instructions
[insn
];
346 /* Optimize away moves, otherwise emit translated instruction:
348 switch (inst
->opcode
) {
349 case TGSI_OPCODE_MOV
:
350 if (!inst
->dst
.saturate
) {
351 pass0_precalc_mov(c
, inst
);
354 translate_insn(c
, inst
);
358 translate_insn(c
, inst
);
363 if (BRW_DEBUG
& DEBUG_WM
) {
364 brw_wm_print_program(c
, "pass0");