src/gallium/drivers/i965/brw_wm_pass2.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_debug.h"
  34 #include "brw_wm.h"
  35
  36
  37 /* Use these to force spilling so that that functionality can be
  38  * tested with known-good examples rather than having to construct new
  39  * tests.
  40  */
  41 #define TEST_PAYLOAD_SPILLS 0
  42 #define TEST_DST_SPILLS 0
  43
  44 static void spill_value(struct brw_wm_compile *c,
  45                         struct brw_wm_value *value);
  46
  47 static void prealloc_reg(struct brw_wm_compile *c,
  48                          struct brw_wm_value *value,
  49                          GLuint reg)
  50 {
  51    if (value->lastuse) {
  52       /* Set nextuse to zero, it will be corrected by
  53        * update_register_usage().
  54        */
  55       c->pass2_grf[reg].value = value;
  56       c->pass2_grf[reg].nextuse = 0;
  57
  58       value->resident = &c->pass2_grf[reg];
  59       value->hw_reg = brw_vec8_grf(reg*2, 0);
  60
  61       if (TEST_PAYLOAD_SPILLS)
  62          spill_value(c, value);
  63    }
  64 }
  65
  66
  67 /* Initialize all the register values.  Do the initial setup
  68  * calculations for interpolants.
  69  */
  70 static void init_registers( struct brw_wm_compile *c )
  71 {
  72    GLuint reg = 0;
  73    GLuint j;
  74
  75    for (j = 0; j < c->grf_limit; j++)
  76       c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
  77
  78    /* Pre-allocate incoming payload regs:
  79     */
  80    for (j = 0; j < c->key.nr_depth_regs; j++)
  81       prealloc_reg(c, &c->payload.depth[j], reg++);
  82
  83    for (j = 0; j < c->nr_creg; j++)
  84       prealloc_reg(c, &c->creg[j], reg++);
  85
  86    for (j = 0; j < c->key.vp_nr_outputs; j++)
  87       prealloc_reg(c, &c->payload.input_interp[j], reg++);
  88
  89    assert(c->key.vp_nr_outputs >= 1);
  90
  91    c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
  92    c->prog_data.urb_read_length = c->key.vp_nr_outputs * 2;
  93    c->prog_data.curb_read_length = c->nr_creg * 2;
  94
  95    /* Note this allocation:
  96     */
  97    c->max_wm_grf = reg * 2;
  98 }
  99
 100
 101 /* Update the nextuse value for each register in our file.
 102  */
 103 static void update_register_usage(struct brw_wm_compile *c,
 104                                   GLuint thisinsn)
 105 {
 106    GLuint i;
 107
 108    for (i = 1; i < c->grf_limit; i++) {
 109       struct brw_wm_grf *grf = &c->pass2_grf[i];
 110
 111       /* Only search those which can change:
 112        */
 113       if (grf->nextuse < thisinsn) {
 114          const struct brw_wm_ref *ref = grf->value->lastuse;
 115
 116          /* Has last use of value been passed?
 117           */
 118          if (ref->insn < thisinsn) {
 119             grf->value->resident = 0;
 120             grf->value = 0;
 121             grf->nextuse = BRW_WM_MAX_INSN;
 122          }
 123          else {
 124             /* Else loop through chain to update:
 125              */
 126             while (ref->prevuse && ref->prevuse->insn >= thisinsn)
 127                ref = ref->prevuse;
 128
 129             grf->nextuse = ref->insn;
 130          }
 131       }
 132    }
 133 }
 134
 135
 136 static void spill_value(struct brw_wm_compile *c,
 137                         struct brw_wm_value *value)
 138 {
 139    /* Allocate a spill slot.  Note that allocations start from 0x40 -
 140     * the first slot is reserved to mean "undef" in brw_wm_emit.c
 141     */
 142    if (!value->spill_slot) {
 143       c->last_scratch += 0x40;
 144       value->spill_slot = c->last_scratch;
 145    }
 146
 147    /* The spill will be done in brw_wm_emit.c immediately after the
 148     * value is calculated, so we can just take this reg without any
 149     * further work.
 150     */
 151    value->resident->value = NULL;
 152    value->resident->nextuse = BRW_WM_MAX_INSN;
 153    value->resident = NULL;
 154 }
 155
 156
 157
 158 /* Search for contiguous region with the most distant nearest
 159  * member.  Free regs count as very distant.
 160  *
 161  * TODO: implement spill-to-reg so that we can rearrange discontigous
 162  * free regs and then spill the oldest non-free regs in sequence.
 163  * This would mean inserting instructions in this pass.
 164  */
 165 static GLuint search_contiguous_regs(struct brw_wm_compile *c,
 166                                      GLuint nr,
 167                                      GLuint thisinsn)
 168 {
 169    struct brw_wm_grf *grf = c->pass2_grf;
 170    GLuint furthest = 0;
 171    GLuint reg = 0;
 172    GLuint i, j;
 173
 174    /* Start search at 1: r0 is special and can't be used or spilled.
 175     */
 176    for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) {
 177       GLuint group_nextuse = BRW_WM_MAX_INSN;
 178
 179       for (j = 0; j < nr; j++) {
 180          if (grf[i+j].nextuse < group_nextuse)
 181             group_nextuse = grf[i+j].nextuse;
 182       }
 183
 184       if (group_nextuse > furthest) {
 185          furthest = group_nextuse;
 186          reg = i;
 187       }
 188    }
 189
 190    assert(furthest != thisinsn);
 191
 192    /* Any non-empty regs will need to be spilled:
 193     */
 194    for (j = 0; j < nr; j++)
 195       if (grf[reg+j].value)
 196          spill_value(c, grf[reg+j].value);
 197
 198    return reg;
 199 }
 200
 201
 202 static void alloc_contiguous_dest(struct brw_wm_compile *c,
 203                                   struct brw_wm_value *dst[],
 204                                   GLuint nr,
 205                                   GLuint thisinsn)
 206 {
 207    GLuint reg = search_contiguous_regs(c, nr, thisinsn);
 208    GLuint i;
 209
 210    for (i = 0; i < nr; i++) {
 211       if (!dst[i]) {
 212          /* Need to grab a dummy value in TEX case.  Don't introduce
 213           * it into the tracking scheme.
 214           */
 215          dst[i] = &c->vreg[c->nr_vreg++];
 216       }
 217       else {
 218          assert(!dst[i]->resident);
 219          assert(c->pass2_grf[reg+i].nextuse != thisinsn);
 220
 221          c->pass2_grf[reg+i].value = dst[i];
 222          c->pass2_grf[reg+i].nextuse = thisinsn;
 223
 224          dst[i]->resident = &c->pass2_grf[reg+i];
 225       }
 226
 227       dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0);
 228    }
 229
 230    if ((reg+nr)*2 > c->max_wm_grf)
 231       c->max_wm_grf = (reg+nr) * 2;
 232 }
 233
 234
 235 static void load_args(struct brw_wm_compile *c,
 236                       struct brw_wm_instruction *inst)
 237 {
 238    GLuint thisinsn = inst - c->instruction;
 239    GLuint i,j;
 240
 241    for (i = 0; i < 3; i++) {
 242       for (j = 0; j < 4; j++) {
 243          struct brw_wm_ref *ref = inst->src[i][j];
 244
 245          if (ref) {
 246             if (!ref->value->resident) {
 247                /* Need to bring the value in from scratch space.  The code for
 248                 * this will be done in brw_wm_emit.c, here we just do the
 249                 * register allocation and mark the ref as requiring a fill.
 250                 */
 251                GLuint reg = search_contiguous_regs(c, 1, thisinsn);
 252
 253                c->pass2_grf[reg].value = ref->value;
 254                c->pass2_grf[reg].nextuse = thisinsn;
 255
 256                ref->value->resident = &c->pass2_grf[reg];
 257
 258                /* Note that a fill is required:
 259                 */
 260                ref->unspill_reg = reg*2;
 261             }
 262
 263             /* Adjust the hw_reg to point at the value's current location:
 264              */
 265             assert(ref->value == ref->value->resident->value);
 266             ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2;
 267          }
 268       }
 269    }
 270 }
 271
 272
 273
 274 /* Step 3: Work forwards once again.  Perform register allocations,
 275  * taking into account instructions like TEX which require contiguous
 276  * result registers.  Where necessary spill registers to scratch space
 277  * and reload later.
 278  */
 279 void brw_wm_pass2( struct brw_wm_compile *c )
 280 {
 281    GLuint insn;
 282    GLuint i;
 283
 284    init_registers(c);
 285
 286    for (insn = 0; insn < c->nr_insns; insn++) {
 287       struct brw_wm_instruction *inst = &c->instruction[insn];
 288
 289       /* Update registers' nextuse values:
 290        */
 291       update_register_usage(c, insn);
 292
 293       /* May need to unspill some args.
 294        */
 295       load_args(c, inst);
 296
 297       /* Allocate registers to hold results:
 298        */
 299       switch (inst->opcode) {
 300       case TGSI_OPCODE_TEX:
 301       case TGSI_OPCODE_TXB:
 302       case TGSI_OPCODE_TXP:
 303          alloc_contiguous_dest(c, inst->dst, 4, insn);
 304          break;
 305
 306       default:
 307          for (i = 0; i < 4; i++) {
 308             if (inst->writemask & (1<<i)) {
 309                assert(inst->dst[i]);
 310                alloc_contiguous_dest(c, &inst->dst[i], 1, insn);
 311             }
 312          }
 313          break;
 314       }
 315
 316       if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY) {
 317          for (i = 0; i < 4; i++)
 318             if (inst->dst[i])
 319                spill_value(c, inst->dst[i]);
 320       }
 321    }
 322
 323    if (BRW_DEBUG & DEBUG_WM) {
 324       brw_wm_print_program(c, "pass2");
 325    }
 326
 327    c->state = PASS2_DONE;
 328
 329    if (BRW_DEBUG & DEBUG_WM) {
 330        brw_wm_print_program(c, "pass2/done");
 331    }
 332 }