2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "util/u_math.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
38 #include "brw_debug.h"
39 #include "brw_pipe_rast.h"
41 /***********************************************************************
42 * WM unit - fragment programs and rasterization
45 struct brw_wm_unit_key
{
46 unsigned int total_grf
, total_scratch
;
47 unsigned int urb_entry_read_length
;
48 unsigned int curb_entry_read_length
;
49 unsigned int dispatch_grf_start_reg
;
51 unsigned int curbe_offset
;
52 unsigned int urb_size
;
54 unsigned int max_threads
;
56 unsigned int nr_surfaces
, sampler_count
;
57 GLboolean uses_depth
, computes_depth
, uses_kill
, has_flow_control
;
58 GLboolean polygon_stipple
, stats_wm
, line_stipple
, offset_enable
;
59 GLfloat offset_units
, offset_factor
;
63 wm_unit_populate_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
)
65 const struct brw_fragment_shader
*fp
= brw
->curr
.fragment_shader
;
67 memset(key
, 0, sizeof(*key
));
69 if (BRW_DEBUG
& DEBUG_SINGLE_THREAD
)
72 /* WM maximum threads is number of EUs times number of threads per EU. */
73 if (BRW_IS_IGDNG(brw
))
74 key
->max_threads
= 12 * 6;
75 else if (BRW_IS_G4X(brw
))
76 key
->max_threads
= 10 * 5;
78 key
->max_threads
= 8 * 4;
81 /* CACHE_NEW_WM_PROG */
82 key
->total_grf
= brw
->wm
.prog_data
->total_grf
;
83 key
->urb_entry_read_length
= brw
->wm
.prog_data
->urb_read_length
;
84 key
->curb_entry_read_length
= brw
->wm
.prog_data
->curb_read_length
;
85 key
->dispatch_grf_start_reg
= brw
->wm
.prog_data
->first_curbe_grf
;
86 key
->total_scratch
= align(brw
->wm
.prog_data
->total_scratch
, 1024);
88 /* BRW_NEW_URB_FENCE */
89 key
->urb_size
= brw
->urb
.vsize
;
91 /* BRW_NEW_CURBE_OFFSETS */
92 key
->curbe_offset
= brw
->curbe
.wm_start
;
94 /* BRW_NEW_NR_SURFACEs */
95 key
->nr_surfaces
= brw
->wm
.nr_surfaces
;
97 /* CACHE_NEW_SAMPLER */
98 key
->sampler_count
= brw
->wm
.sampler_count
;
101 key
->polygon_stipple
= brw
->curr
.rast
->templ
.poly_stipple_enable
;
103 /* PIPE_NEW_FRAGMENT_PROGRAM */
104 key
->uses_depth
= fp
->uses_depth
;
105 key
->computes_depth
= fp
->info
.writes_z
;
107 /* PIPE_NEW_DEPTH_BUFFER
109 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
112 if (brw
->curr
.fb
.zsbuf
== NULL
)
113 key
->computes_depth
= 0;
115 /* PIPE_NEW_DEPTH_STENCIL_ALPHA */
116 key
->uses_kill
= (fp
->info
.uses_kill
||
117 brw
->curr
.zstencil
->cc3
.alpha_test
);
119 key
->has_flow_control
= fp
->has_flow_control
;
121 /* temporary sanity check assertion */
122 assert(fp
->has_flow_control
== 0);
125 key
->stats_wm
= (brw
->query
.stats_wm
!= 0);
128 key
->line_stipple
= brw
->curr
.rast
->templ
.line_stipple_enable
;
131 key
->offset_enable
= (brw
->curr
.rast
->templ
.offset_point
||
132 brw
->curr
.rast
->templ
.offset_line
||
133 brw
->curr
.rast
->templ
.offset_tri
);
135 key
->offset_units
= brw
->curr
.rast
->templ
.offset_units
;
136 key
->offset_factor
= brw
->curr
.rast
->templ
.offset_scale
;
140 * Setup wm hardware state. See page 225 of Volume 2
142 static enum pipe_error
143 wm_unit_create_from_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
,
144 struct brw_winsys_reloc
*reloc
,
146 struct brw_winsys_buffer
**bo_out
)
148 struct brw_wm_unit_state wm
;
151 memset(&wm
, 0, sizeof(wm
));
153 wm
.thread0
.grf_reg_count
= align(key
->total_grf
, 16) / 16 - 1;
154 wm
.thread0
.kernel_start_pointer
= 0; /* reloc */
155 wm
.thread1
.depth_coef_urb_read_offset
= 1;
156 wm
.thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
158 if (BRW_IS_IGDNG(brw
))
159 wm
.thread1
.binding_table_entry_count
= 0; /* hardware requirement */
161 wm
.thread1
.binding_table_entry_count
= key
->nr_surfaces
;
163 if (key
->total_scratch
!= 0) {
164 wm
.thread2
.scratch_space_base_pointer
= 0; /* reloc */
165 wm
.thread2
.per_thread_scratch_space
= key
->total_scratch
/ 1024 - 1;
167 wm
.thread2
.scratch_space_base_pointer
= 0;
168 wm
.thread2
.per_thread_scratch_space
= 0;
171 wm
.thread3
.dispatch_grf_start_reg
= key
->dispatch_grf_start_reg
;
172 wm
.thread3
.urb_entry_read_length
= key
->urb_entry_read_length
;
173 wm
.thread3
.urb_entry_read_offset
= 0;
174 wm
.thread3
.const_urb_entry_read_length
= key
->curb_entry_read_length
;
175 wm
.thread3
.const_urb_entry_read_offset
= key
->curbe_offset
* 2;
177 if (BRW_IS_IGDNG(brw
))
178 wm
.wm4
.sampler_count
= 0; /* hardware requirement */
180 wm
.wm4
.sampler_count
= (key
->sampler_count
+ 1) / 4;
183 wm
.wm4
.sampler_state_pointer
= 0;
185 wm
.wm5
.program_uses_depth
= key
->uses_depth
;
186 wm
.wm5
.program_computes_depth
= key
->computes_depth
;
187 wm
.wm5
.program_uses_killpixel
= key
->uses_kill
;
189 if (key
->has_flow_control
)
190 wm
.wm5
.enable_8_pix
= 1;
192 wm
.wm5
.enable_16_pix
= 1;
194 wm
.wm5
.max_threads
= key
->max_threads
- 1;
195 wm
.wm5
.thread_dispatch_enable
= 1; /* AKA: color_write */
196 wm
.wm5
.legacy_line_rast
= 0;
197 wm
.wm5
.legacy_global_depth_bias
= 0;
198 wm
.wm5
.early_depth_test
= 1; /* never need to disable */
199 wm
.wm5
.line_aa_region_width
= 0;
200 wm
.wm5
.line_endcap_aa_region_width
= 1;
202 wm
.wm5
.polygon_stipple
= key
->polygon_stipple
;
204 if (key
->offset_enable
) {
205 wm
.wm5
.depth_offset
= 1;
206 /* Something wierd going on with legacy_global_depth_bias,
207 * offset_constant, scaling and MRD. This value passes glean
208 * but gives some odd results elsewere (eg. the
209 * quad-offset-units test).
211 wm
.global_depth_offset_constant
= key
->offset_units
* 2;
213 /* This is the only value that passes glean:
215 wm
.global_depth_offset_scale
= key
->offset_factor
;
218 wm
.wm5
.line_stipple
= key
->line_stipple
;
220 if ((BRW_DEBUG
& DEBUG_STATS
) || key
->stats_wm
)
221 wm
.wm4
.stats_enable
= 1;
223 ret
= brw_upload_cache(&brw
->cache
, BRW_WM_UNIT
,
236 static enum pipe_error
upload_wm_unit( struct brw_context
*brw
)
238 struct brw_wm_unit_key key
;
239 struct brw_winsys_reloc reloc
[3];
240 unsigned nr_reloc
= 0;
242 unsigned grf_reg_count
;
243 unsigned per_thread_scratch_space
;
244 unsigned stats_enable
;
245 unsigned sampler_count
;
247 wm_unit_populate_key(brw
, &key
);
250 /* Allocate the necessary scratch space if we haven't already. Don't
251 * bother reducing the allocation later, since we use scratch so
254 assert(key
.total_scratch
<= 12 * 1024);
255 if (key
.total_scratch
) {
256 GLuint total
= key
.total_scratch
* key
.max_threads
;
258 /* Do we need a new buffer:
260 if (brw
->wm
.scratch_bo
&& total
> brw
->wm
.scratch_bo
->size
)
261 bo_reference(&brw
->wm
.scratch_bo
, NULL
);
263 if (brw
->wm
.scratch_bo
== NULL
) {
264 ret
= brw
->sws
->bo_alloc(brw
->sws
,
265 BRW_BUFFER_TYPE_SHADER_SCRATCH
,
268 &brw
->wm
.scratch_bo
);
277 grf_reg_count
= (align(key
.total_grf
, 16) / 16 - 1);
278 per_thread_scratch_space
= key
.total_scratch
/ 1024 - 1;
279 stats_enable
= (BRW_DEBUG
& DEBUG_STATS
) || key
.stats_wm
;
280 sampler_count
= BRW_IS_IGDNG(brw
) ? 0 :(key
.sampler_count
+ 1) / 4;
282 /* Emit WM program relocation */
283 make_reloc(&reloc
[nr_reloc
++],
286 offsetof(struct brw_wm_unit_state
, thread0
),
289 /* Emit scratch space relocation */
290 if (key
.total_scratch
!= 0) {
291 make_reloc(&reloc
[nr_reloc
++],
293 per_thread_scratch_space
,
294 offsetof(struct brw_wm_unit_state
, thread2
),
298 /* Emit sampler state relocation */
299 if (key
.sampler_count
!= 0) {
300 make_reloc(&reloc
[nr_reloc
++],
302 stats_enable
| (sampler_count
<< 2),
303 offsetof(struct brw_wm_unit_state
, wm4
),
308 if (brw_search_cache(&brw
->cache
, BRW_WM_UNIT
,
315 ret
= wm_unit_create_from_key(brw
, &key
,
324 const struct brw_tracked_state brw_wm_unit
= {
326 .mesa
= (PIPE_NEW_FRAGMENT_SHADER
|
327 PIPE_NEW_DEPTH_BUFFER
|
329 PIPE_NEW_DEPTH_STENCIL_ALPHA
|
332 .brw
= (BRW_NEW_CURBE_OFFSETS
|
333 BRW_NEW_NR_WM_SURFACES
),
335 .cache
= (CACHE_NEW_WM_PROG
|
338 .prepare
= upload_wm_unit
,