i965g: make the winsys responsible for all buffer->offset handling
[mesa.git] / src / gallium / drivers / i965 / brw_wm_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "util/u_math.h"
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "brw_wm.h"
38 #include "brw_debug.h"
39 #include "brw_pipe_rast.h"
40
41 /***********************************************************************
42 * WM unit - fragment programs and rasterization
43 */
44
45 struct brw_wm_unit_key {
46 unsigned int total_grf, total_scratch;
47 unsigned int urb_entry_read_length;
48 unsigned int curb_entry_read_length;
49 unsigned int dispatch_grf_start_reg;
50
51 unsigned int curbe_offset;
52 unsigned int urb_size;
53
54 unsigned int max_threads;
55
56 unsigned int nr_surfaces, sampler_count;
57 GLboolean uses_depth, computes_depth, uses_kill, has_flow_control;
58 GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
59 GLfloat offset_units, offset_factor;
60 };
61
62 static void
63 wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
64 {
65 const struct brw_fragment_shader *fp = brw->curr.fragment_shader;
66
67 memset(key, 0, sizeof(*key));
68
69 if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
70 key->max_threads = 1;
71 else {
72 /* WM maximum threads is number of EUs times number of threads per EU. */
73 if (BRW_IS_IGDNG(brw))
74 key->max_threads = 12 * 6;
75 else if (BRW_IS_G4X(brw))
76 key->max_threads = 10 * 5;
77 else
78 key->max_threads = 8 * 4;
79 }
80
81 /* CACHE_NEW_WM_PROG */
82 key->total_grf = brw->wm.prog_data->total_grf;
83 key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
84 key->curb_entry_read_length = brw->wm.prog_data->curb_read_length;
85 key->dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
86 key->total_scratch = align(brw->wm.prog_data->total_scratch, 1024);
87
88 /* BRW_NEW_URB_FENCE */
89 key->urb_size = brw->urb.vsize;
90
91 /* BRW_NEW_CURBE_OFFSETS */
92 key->curbe_offset = brw->curbe.wm_start;
93
94 /* BRW_NEW_NR_SURFACEs */
95 key->nr_surfaces = brw->wm.nr_surfaces;
96
97 /* CACHE_NEW_SAMPLER */
98 key->sampler_count = brw->wm.sampler_count;
99
100 /* PIPE_NEW_RAST */
101 key->polygon_stipple = brw->curr.rast->templ.poly_stipple_enable;
102
103 /* PIPE_NEW_FRAGMENT_PROGRAM */
104 key->uses_depth = fp->uses_depth;
105 key->computes_depth = fp->info.writes_z;
106
107 /* PIPE_NEW_DEPTH_BUFFER
108 *
109 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
110 * Depth field.
111 */
112 if (brw->curr.fb.zsbuf == NULL)
113 key->computes_depth = 0;
114
115 /* PIPE_NEW_DEPTH_STENCIL_ALPHA */
116 key->uses_kill = (fp->info.uses_kill ||
117 brw->curr.zstencil->cc3.alpha_test);
118
119 key->has_flow_control = fp->has_flow_control;
120
121 /* temporary sanity check assertion */
122 assert(fp->has_flow_control == 0);
123
124 /* PIPE_NEW_QUERY */
125 key->stats_wm = (brw->query.stats_wm != 0);
126
127 /* PIPE_NEW_RAST */
128 key->line_stipple = brw->curr.rast->templ.line_stipple_enable;
129
130
131 key->offset_enable = (brw->curr.rast->templ.offset_cw ||
132 brw->curr.rast->templ.offset_ccw);
133
134 key->offset_units = brw->curr.rast->templ.offset_units;
135 key->offset_factor = brw->curr.rast->templ.offset_scale;
136 }
137
138 /**
139 * Setup wm hardware state. See page 225 of Volume 2
140 */
141 static enum pipe_error
142 wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
143 struct brw_winsys_buffer **reloc_bufs,
144 struct brw_winsys_buffer **bo_out)
145 {
146 struct brw_wm_unit_state wm;
147 enum pipe_error ret;
148
149 memset(&wm, 0, sizeof(wm));
150
151 wm.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
152 wm.thread0.kernel_start_pointer = 0; /* reloc */
153 wm.thread1.depth_coef_urb_read_offset = 1;
154 wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
155
156 if (BRW_IS_IGDNG(brw))
157 wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
158 else
159 wm.thread1.binding_table_entry_count = key->nr_surfaces;
160
161 if (key->total_scratch != 0) {
162 wm.thread2.scratch_space_base_pointer = 0; /* reloc */
163 wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1;
164 } else {
165 wm.thread2.scratch_space_base_pointer = 0;
166 wm.thread2.per_thread_scratch_space = 0;
167 }
168
169 wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg;
170 wm.thread3.urb_entry_read_length = key->urb_entry_read_length;
171 wm.thread3.urb_entry_read_offset = 0;
172 wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
173 wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
174
175 if (BRW_IS_IGDNG(brw))
176 wm.wm4.sampler_count = 0; /* hardware requirement */
177 else
178 wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
179
180 /* reloc */
181 wm.wm4.sampler_state_pointer = 0;
182
183 wm.wm5.program_uses_depth = key->uses_depth;
184 wm.wm5.program_computes_depth = key->computes_depth;
185 wm.wm5.program_uses_killpixel = key->uses_kill;
186
187 if (key->has_flow_control)
188 wm.wm5.enable_8_pix = 1;
189 else
190 wm.wm5.enable_16_pix = 1;
191
192 wm.wm5.max_threads = key->max_threads - 1;
193 wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */
194 wm.wm5.legacy_line_rast = 0;
195 wm.wm5.legacy_global_depth_bias = 0;
196 wm.wm5.early_depth_test = 1; /* never need to disable */
197 wm.wm5.line_aa_region_width = 0;
198 wm.wm5.line_endcap_aa_region_width = 1;
199
200 wm.wm5.polygon_stipple = key->polygon_stipple;
201
202 if (key->offset_enable) {
203 wm.wm5.depth_offset = 1;
204 /* Something wierd going on with legacy_global_depth_bias,
205 * offset_constant, scaling and MRD. This value passes glean
206 * but gives some odd results elsewere (eg. the
207 * quad-offset-units test).
208 */
209 wm.global_depth_offset_constant = key->offset_units * 2;
210
211 /* This is the only value that passes glean:
212 */
213 wm.global_depth_offset_scale = key->offset_factor;
214 }
215
216 wm.wm5.line_stipple = key->line_stipple;
217
218 if (BRW_DEBUG & DEBUG_STATS || key->stats_wm)
219 wm.wm4.stats_enable = 1;
220
221 ret = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
222 key, sizeof(*key),
223 reloc_bufs, 3,
224 &wm, sizeof(wm),
225 NULL, NULL,
226 bo_out);
227 if (ret)
228 return ret;
229
230 /* Emit WM program relocation */
231 ret = brw->sws->bo_emit_reloc(*bo_out,
232 BRW_USAGE_STATE,
233 wm.thread0.grf_reg_count << 1,
234 offsetof(struct brw_wm_unit_state, thread0),
235 brw->wm.prog_bo);
236 if (ret)
237 return ret;
238
239 /* Emit scratch space relocation */
240 if (key->total_scratch != 0) {
241 ret = brw->sws->bo_emit_reloc(*bo_out,
242 BRW_USAGE_SCRATCH,
243 wm.thread2.per_thread_scratch_space,
244 offsetof(struct brw_wm_unit_state, thread2),
245 brw->wm.scratch_bo);
246 if (ret)
247 return ret;
248 }
249
250 /* Emit sampler state relocation */
251 if (key->sampler_count != 0) {
252 ret = brw->sws->bo_emit_reloc(*bo_out,
253 BRW_USAGE_STATE,
254 wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
255 offsetof(struct brw_wm_unit_state, wm4),
256 brw->wm.sampler_bo);
257 if (ret)
258 return ret;
259 }
260
261 return PIPE_OK;
262 }
263
264
265 static enum pipe_error upload_wm_unit( struct brw_context *brw )
266 {
267 struct brw_wm_unit_key key;
268 struct brw_winsys_buffer *reloc_bufs[3];
269 enum pipe_error ret;
270
271 wm_unit_populate_key(brw, &key);
272
273 /* Allocate the necessary scratch space if we haven't already. Don't
274 * bother reducing the allocation later, since we use scratch so
275 * rarely.
276 */
277 assert(key.total_scratch <= 12 * 1024);
278 if (key.total_scratch) {
279 GLuint total = key.total_scratch * key.max_threads;
280
281 /* Do we need a new buffer:
282 */
283 if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size)
284 bo_reference(&brw->wm.scratch_bo, NULL);
285
286 if (brw->wm.scratch_bo == NULL) {
287 ret = brw->sws->bo_alloc(brw->sws,
288 BRW_BUFFER_TYPE_SHADER_SCRATCH,
289 total,
290 4096,
291 &brw->wm.scratch_bo);
292 if (ret)
293 return ret;
294 }
295 }
296
297 reloc_bufs[0] = brw->wm.prog_bo;
298 reloc_bufs[1] = brw->wm.scratch_bo;
299 reloc_bufs[2] = brw->wm.sampler_bo;
300
301 if (brw_search_cache(&brw->cache, BRW_WM_UNIT,
302 &key, sizeof(key),
303 reloc_bufs, 3,
304 NULL,
305 &brw->wm.state_bo))
306 return PIPE_OK;
307
308 ret = wm_unit_create_from_key(brw, &key, reloc_bufs,
309 &brw->wm.state_bo);
310 if (ret)
311 return ret;
312
313 return PIPE_OK;
314 }
315
316 const struct brw_tracked_state brw_wm_unit = {
317 .dirty = {
318 .mesa = (PIPE_NEW_FRAGMENT_SHADER |
319 PIPE_NEW_DEPTH_BUFFER |
320 PIPE_NEW_RAST |
321 PIPE_NEW_DEPTH_STENCIL_ALPHA |
322 PIPE_NEW_QUERY),
323
324 .brw = (BRW_NEW_CURBE_OFFSETS |
325 BRW_NEW_NR_WM_SURFACES),
326
327 .cache = (CACHE_NEW_WM_PROG |
328 CACHE_NEW_SAMPLER)
329 },
330 .prepare = upload_wm_unit,
331 };
332