1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "brw_batch.h"
32 #include "brw_defines.h"
33 #include "brw_context.h"
34 #include "brw_state.h"
37 struct brw_array_state
{
38 union header_union header
;
45 unsigned access_type
:1;
51 struct pipe_buffer
*buffer
;
55 unsigned instance_data_step_rate
;
62 unsigned brw_translate_surface_format( unsigned id
)
65 case PIPE_FORMAT_R64_FLOAT
:
66 return BRW_SURFACEFORMAT_R64_FLOAT
;
67 case PIPE_FORMAT_R64G64_FLOAT
:
68 return BRW_SURFACEFORMAT_R64G64_FLOAT
;
69 case PIPE_FORMAT_R64G64B64_FLOAT
:
70 return BRW_SURFACEFORMAT_R64G64B64_FLOAT
;
71 case PIPE_FORMAT_R64G64B64A64_FLOAT
:
72 return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
;
74 case PIPE_FORMAT_R32_FLOAT
:
75 return BRW_SURFACEFORMAT_R32_FLOAT
;
76 case PIPE_FORMAT_R32G32_FLOAT
:
77 return BRW_SURFACEFORMAT_R32G32_FLOAT
;
78 case PIPE_FORMAT_R32G32B32_FLOAT
:
79 return BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
80 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
81 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
83 case PIPE_FORMAT_R32_UNORM
:
84 return BRW_SURFACEFORMAT_R32_UNORM
;
85 case PIPE_FORMAT_R32G32_UNORM
:
86 return BRW_SURFACEFORMAT_R32G32_UNORM
;
87 case PIPE_FORMAT_R32G32B32_UNORM
:
88 return BRW_SURFACEFORMAT_R32G32B32_UNORM
;
89 case PIPE_FORMAT_R32G32B32A32_UNORM
:
90 return BRW_SURFACEFORMAT_R32G32B32A32_UNORM
;
92 case PIPE_FORMAT_R32_USCALED
:
93 return BRW_SURFACEFORMAT_R32_USCALED
;
94 case PIPE_FORMAT_R32G32_USCALED
:
95 return BRW_SURFACEFORMAT_R32G32_USCALED
;
96 case PIPE_FORMAT_R32G32B32_USCALED
:
97 return BRW_SURFACEFORMAT_R32G32B32_USCALED
;
98 case PIPE_FORMAT_R32G32B32A32_USCALED
:
99 return BRW_SURFACEFORMAT_R32G32B32A32_USCALED
;
101 case PIPE_FORMAT_R32_SNORM
:
102 return BRW_SURFACEFORMAT_R32_SNORM
;
103 case PIPE_FORMAT_R32G32_SNORM
:
104 return BRW_SURFACEFORMAT_R32G32_SNORM
;
105 case PIPE_FORMAT_R32G32B32_SNORM
:
106 return BRW_SURFACEFORMAT_R32G32B32_SNORM
;
107 case PIPE_FORMAT_R32G32B32A32_SNORM
:
108 return BRW_SURFACEFORMAT_R32G32B32A32_SNORM
;
110 case PIPE_FORMAT_R32_SSCALED
:
111 return BRW_SURFACEFORMAT_R32_SSCALED
;
112 case PIPE_FORMAT_R32G32_SSCALED
:
113 return BRW_SURFACEFORMAT_R32G32_SSCALED
;
114 case PIPE_FORMAT_R32G32B32_SSCALED
:
115 return BRW_SURFACEFORMAT_R32G32B32_SSCALED
;
116 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
117 return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
;
119 case PIPE_FORMAT_R16_UNORM
:
120 return BRW_SURFACEFORMAT_R16_UNORM
;
121 case PIPE_FORMAT_R16G16_UNORM
:
122 return BRW_SURFACEFORMAT_R16G16_UNORM
;
123 case PIPE_FORMAT_R16G16B16_UNORM
:
124 return BRW_SURFACEFORMAT_R16G16B16_UNORM
;
125 case PIPE_FORMAT_R16G16B16A16_UNORM
:
126 return BRW_SURFACEFORMAT_R16G16B16A16_UNORM
;
128 case PIPE_FORMAT_R16_USCALED
:
129 return BRW_SURFACEFORMAT_R16_USCALED
;
130 case PIPE_FORMAT_R16G16_USCALED
:
131 return BRW_SURFACEFORMAT_R16G16_USCALED
;
132 case PIPE_FORMAT_R16G16B16_USCALED
:
133 return BRW_SURFACEFORMAT_R16G16B16_USCALED
;
134 case PIPE_FORMAT_R16G16B16A16_USCALED
:
135 return BRW_SURFACEFORMAT_R16G16B16A16_USCALED
;
137 case PIPE_FORMAT_R16_SNORM
:
138 return BRW_SURFACEFORMAT_R16_SNORM
;
139 case PIPE_FORMAT_R16G16_SNORM
:
140 return BRW_SURFACEFORMAT_R16G16_SNORM
;
141 case PIPE_FORMAT_R16G16B16_SNORM
:
142 return BRW_SURFACEFORMAT_R16G16B16_SNORM
;
143 case PIPE_FORMAT_R16G16B16A16_SNORM
:
144 return BRW_SURFACEFORMAT_R16G16B16A16_SNORM
;
146 case PIPE_FORMAT_R16_SSCALED
:
147 return BRW_SURFACEFORMAT_R16_SSCALED
;
148 case PIPE_FORMAT_R16G16_SSCALED
:
149 return BRW_SURFACEFORMAT_R16G16_SSCALED
;
150 case PIPE_FORMAT_R16G16B16_SSCALED
:
151 return BRW_SURFACEFORMAT_R16G16B16_SSCALED
;
152 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
153 return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
;
155 case PIPE_FORMAT_R8_UNORM
:
156 return BRW_SURFACEFORMAT_R8_UNORM
;
157 case PIPE_FORMAT_R8G8_UNORM
:
158 return BRW_SURFACEFORMAT_R8G8_UNORM
;
159 case PIPE_FORMAT_R8G8B8_UNORM
:
160 return BRW_SURFACEFORMAT_R8G8B8_UNORM
;
161 case PIPE_FORMAT_R8G8B8A8_UNORM
:
162 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
164 case PIPE_FORMAT_R8_USCALED
:
165 return BRW_SURFACEFORMAT_R8_USCALED
;
166 case PIPE_FORMAT_R8G8_USCALED
:
167 return BRW_SURFACEFORMAT_R8G8_USCALED
;
168 case PIPE_FORMAT_R8G8B8_USCALED
:
169 return BRW_SURFACEFORMAT_R8G8B8_USCALED
;
170 case PIPE_FORMAT_R8G8B8A8_USCALED
:
171 return BRW_SURFACEFORMAT_R8G8B8A8_USCALED
;
173 case PIPE_FORMAT_R8_SNORM
:
174 return BRW_SURFACEFORMAT_R8_SNORM
;
175 case PIPE_FORMAT_R8G8_SNORM
:
176 return BRW_SURFACEFORMAT_R8G8_SNORM
;
177 case PIPE_FORMAT_R8G8B8_SNORM
:
178 return BRW_SURFACEFORMAT_R8G8B8_SNORM
;
179 case PIPE_FORMAT_R8G8B8A8_SNORM
:
180 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM
;
182 case PIPE_FORMAT_R8_SSCALED
:
183 return BRW_SURFACEFORMAT_R8_SSCALED
;
184 case PIPE_FORMAT_R8G8_SSCALED
:
185 return BRW_SURFACEFORMAT_R8G8_SSCALED
;
186 case PIPE_FORMAT_R8G8B8_SSCALED
:
187 return BRW_SURFACEFORMAT_R8G8B8_SSCALED
;
188 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
189 return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
;
197 static unsigned get_index_type(int type
)
200 case 1: return BRW_INDEX_BYTE
;
201 case 2: return BRW_INDEX_WORD
;
202 case 4: return BRW_INDEX_DWORD
;
203 default: assert(0); return 0;
208 boolean
brw_upload_vertex_buffers( struct brw_context
*brw
)
210 struct brw_array_state vbp
;
211 unsigned nr_enabled
= 0;
214 memset(&vbp
, 0, sizeof(vbp
));
216 /* This is a hardware limit:
219 for (i
= 0; i
< BRW_VEP_MAX
; i
++)
221 if (brw
->vb
.vbo_array
[i
] == NULL
) {
226 vbp
.vb
[i
].vb0
.bits
.pitch
= brw
->vb
.vbo_array
[i
]->stride
;
227 vbp
.vb
[i
].vb0
.bits
.pad
= 0;
228 vbp
.vb
[i
].vb0
.bits
.access_type
= BRW_VERTEXBUFFER_ACCESS_VERTEXDATA
;
229 vbp
.vb
[i
].vb0
.bits
.vb_index
= i
;
230 vbp
.vb
[i
].offset
= brw
->vb
.vbo_array
[i
]->buffer_offset
;
231 vbp
.vb
[i
].buffer
= brw
->vb
.vbo_array
[i
]->buffer
;
232 vbp
.vb
[i
].max_index
= brw
->vb
.vbo_array
[i
]->max_index
;
236 vbp
.header
.bits
.length
= (1 + nr_enabled
* 4) - 2;
237 vbp
.header
.bits
.opcode
= CMD_VERTEX_BUFFER
;
239 BEGIN_BATCH(vbp
.header
.bits
.length
+2, 0);
240 OUT_BATCH( vbp
.header
.dword
);
242 for (i
= 0; i
< nr_enabled
; i
++) {
243 OUT_BATCH( vbp
.vb
[i
].vb0
.dword
);
244 OUT_RELOC( vbp
.vb
[i
].buffer
, PIPE_BUFFER_USAGE_GPU_READ
,
246 OUT_BATCH( vbp
.vb
[i
].max_index
);
247 OUT_BATCH( vbp
.vb
[i
].instance_data_step_rate
);
255 boolean
brw_upload_vertex_elements( struct brw_context
*brw
)
257 struct brw_vertex_element_packet vep
;
260 unsigned nr_enabled
= brw
->attribs
.VertexProgram
->info
.num_inputs
;
262 memset(&vep
, 0, sizeof(vep
));
264 for (i
= 0; i
< nr_enabled
; i
++)
265 vep
.ve
[i
] = brw
->vb
.inputs
[i
];
268 vep
.header
.length
= (1 + nr_enabled
* sizeof(vep
.ve
[0])/4) - 2;
269 vep
.header
.opcode
= CMD_VERTEX_ELEMENT
;
270 brw_cached_batch_struct(brw
, &vep
, 4 + nr_enabled
* sizeof(vep
.ve
[0]));
275 boolean
brw_upload_indices( struct brw_context
*brw
,
276 const struct pipe_buffer
*index_buffer
,
277 int ib_size
, int start
, int count
)
279 /* Emit the indexbuffer packet:
282 struct brw_indexbuffer ib
;
284 memset(&ib
, 0, sizeof(ib
));
286 ib
.header
.bits
.opcode
= CMD_INDEX_BUFFER
;
287 ib
.header
.bits
.length
= sizeof(ib
)/4 - 2;
288 ib
.header
.bits
.index_format
= get_index_type(ib_size
);
289 ib
.header
.bits
.cut_index_enable
= 0;
293 OUT_BATCH( ib
.header
.dword
);
294 OUT_RELOC( index_buffer
, PIPE_BUFFER_USAGE_GPU_READ
, start
);
295 OUT_RELOC( index_buffer
, PIPE_BUFFER_USAGE_GPU_READ
, start
+ count
);