src/gallium/drivers/i965simple/brw_draw_upload.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdlib.h>
  29
  30 #include "brw_batch.h"
  31 #include "brw_draw.h"
  32 #include "brw_defines.h"
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35
  36 struct brw_array_state {
  37    union header_union header;
  38
  39    struct {
  40       union {
  41          struct {
  42             unsigned pitch:11;
  43             unsigned pad:15;
  44             unsigned access_type:1;
  45             unsigned vb_index:5;
  46          } bits;
  47          unsigned dword;
  48       } vb0;
  49
  50       struct pipe_buffer *buffer;
  51       unsigned offset;
  52
  53       unsigned max_index;
  54       unsigned instance_data_step_rate;
  55
  56    } vb[BRW_VBP_MAX];
  57 };
  58
  59
  60
  61 unsigned brw_translate_surface_format( unsigned id )
  62 {
  63    switch (id) {
  64    case PIPE_FORMAT_R64_FLOAT:
  65       return BRW_SURFACEFORMAT_R64_FLOAT;
  66    case PIPE_FORMAT_R64G64_FLOAT:
  67       return BRW_SURFACEFORMAT_R64G64_FLOAT;
  68    case PIPE_FORMAT_R64G64B64_FLOAT:
  69       return BRW_SURFACEFORMAT_R64G64B64_FLOAT;
  70    case PIPE_FORMAT_R64G64B64A64_FLOAT:
  71       return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT;
  72
  73    case PIPE_FORMAT_R32_FLOAT:
  74       return BRW_SURFACEFORMAT_R32_FLOAT;
  75    case PIPE_FORMAT_R32G32_FLOAT:
  76       return BRW_SURFACEFORMAT_R32G32_FLOAT;
  77    case PIPE_FORMAT_R32G32B32_FLOAT:
  78       return BRW_SURFACEFORMAT_R32G32B32_FLOAT;
  79    case PIPE_FORMAT_R32G32B32A32_FLOAT:
  80       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
  81
  82    case PIPE_FORMAT_R32_UNORM:
  83       return BRW_SURFACEFORMAT_R32_UNORM;
  84    case PIPE_FORMAT_R32G32_UNORM:
  85       return BRW_SURFACEFORMAT_R32G32_UNORM;
  86    case PIPE_FORMAT_R32G32B32_UNORM:
  87       return BRW_SURFACEFORMAT_R32G32B32_UNORM;
  88    case PIPE_FORMAT_R32G32B32A32_UNORM:
  89       return BRW_SURFACEFORMAT_R32G32B32A32_UNORM;
  90
  91    case PIPE_FORMAT_R32_USCALED:
  92       return BRW_SURFACEFORMAT_R32_USCALED;
  93    case PIPE_FORMAT_R32G32_USCALED:
  94       return BRW_SURFACEFORMAT_R32G32_USCALED;
  95    case PIPE_FORMAT_R32G32B32_USCALED:
  96       return BRW_SURFACEFORMAT_R32G32B32_USCALED;
  97    case PIPE_FORMAT_R32G32B32A32_USCALED:
  98       return BRW_SURFACEFORMAT_R32G32B32A32_USCALED;
  99
 100    case PIPE_FORMAT_R32_SNORM:
 101       return BRW_SURFACEFORMAT_R32_SNORM;
 102    case PIPE_FORMAT_R32G32_SNORM:
 103       return BRW_SURFACEFORMAT_R32G32_SNORM;
 104    case PIPE_FORMAT_R32G32B32_SNORM:
 105       return BRW_SURFACEFORMAT_R32G32B32_SNORM;
 106    case PIPE_FORMAT_R32G32B32A32_SNORM:
 107       return BRW_SURFACEFORMAT_R32G32B32A32_SNORM;
 108
 109    case PIPE_FORMAT_R32_SSCALED:
 110       return BRW_SURFACEFORMAT_R32_SSCALED;
 111    case PIPE_FORMAT_R32G32_SSCALED:
 112       return BRW_SURFACEFORMAT_R32G32_SSCALED;
 113    case PIPE_FORMAT_R32G32B32_SSCALED:
 114       return BRW_SURFACEFORMAT_R32G32B32_SSCALED;
 115    case PIPE_FORMAT_R32G32B32A32_SSCALED:
 116       return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED;
 117
 118    case PIPE_FORMAT_R16_UNORM:
 119       return BRW_SURFACEFORMAT_R16_UNORM;
 120    case PIPE_FORMAT_R16G16_UNORM:
 121       return BRW_SURFACEFORMAT_R16G16_UNORM;
 122    case PIPE_FORMAT_R16G16B16_UNORM:
 123       return BRW_SURFACEFORMAT_R16G16B16_UNORM;
 124    case PIPE_FORMAT_R16G16B16A16_UNORM:
 125       return BRW_SURFACEFORMAT_R16G16B16A16_UNORM;
 126
 127    case PIPE_FORMAT_R16_USCALED:
 128       return BRW_SURFACEFORMAT_R16_USCALED;
 129    case PIPE_FORMAT_R16G16_USCALED:
 130       return BRW_SURFACEFORMAT_R16G16_USCALED;
 131    case PIPE_FORMAT_R16G16B16_USCALED:
 132       return BRW_SURFACEFORMAT_R16G16B16_USCALED;
 133    case PIPE_FORMAT_R16G16B16A16_USCALED:
 134       return BRW_SURFACEFORMAT_R16G16B16A16_USCALED;
 135
 136    case PIPE_FORMAT_R16_SNORM:
 137       return BRW_SURFACEFORMAT_R16_SNORM;
 138    case PIPE_FORMAT_R16G16_SNORM:
 139       return BRW_SURFACEFORMAT_R16G16_SNORM;
 140    case PIPE_FORMAT_R16G16B16_SNORM:
 141       return BRW_SURFACEFORMAT_R16G16B16_SNORM;
 142    case PIPE_FORMAT_R16G16B16A16_SNORM:
 143       return BRW_SURFACEFORMAT_R16G16B16A16_SNORM;
 144
 145    case PIPE_FORMAT_R16_SSCALED:
 146       return BRW_SURFACEFORMAT_R16_SSCALED;
 147    case PIPE_FORMAT_R16G16_SSCALED:
 148       return BRW_SURFACEFORMAT_R16G16_SSCALED;
 149    case PIPE_FORMAT_R16G16B16_SSCALED:
 150       return BRW_SURFACEFORMAT_R16G16B16_SSCALED;
 151    case PIPE_FORMAT_R16G16B16A16_SSCALED:
 152       return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED;
 153
 154    case PIPE_FORMAT_R8_UNORM:
 155       return BRW_SURFACEFORMAT_R8_UNORM;
 156    case PIPE_FORMAT_R8G8_UNORM:
 157       return BRW_SURFACEFORMAT_R8G8_UNORM;
 158    case PIPE_FORMAT_R8G8B8_UNORM:
 159       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
 160    case PIPE_FORMAT_R8G8B8A8_UNORM:
 161       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 162
 163    case PIPE_FORMAT_R8_USCALED:
 164       return BRW_SURFACEFORMAT_R8_USCALED;
 165    case PIPE_FORMAT_R8G8_USCALED:
 166       return BRW_SURFACEFORMAT_R8G8_USCALED;
 167    case PIPE_FORMAT_R8G8B8_USCALED:
 168       return BRW_SURFACEFORMAT_R8G8B8_USCALED;
 169    case PIPE_FORMAT_R8G8B8A8_USCALED:
 170       return BRW_SURFACEFORMAT_R8G8B8A8_USCALED;
 171
 172    case PIPE_FORMAT_R8_SNORM:
 173       return BRW_SURFACEFORMAT_R8_SNORM;
 174    case PIPE_FORMAT_R8G8_SNORM:
 175       return BRW_SURFACEFORMAT_R8G8_SNORM;
 176    case PIPE_FORMAT_R8G8B8_SNORM:
 177       return BRW_SURFACEFORMAT_R8G8B8_SNORM;
 178    case PIPE_FORMAT_R8G8B8A8_SNORM:
 179       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 180
 181    case PIPE_FORMAT_R8_SSCALED:
 182       return BRW_SURFACEFORMAT_R8_SSCALED;
 183    case PIPE_FORMAT_R8G8_SSCALED:
 184       return BRW_SURFACEFORMAT_R8G8_SSCALED;
 185    case PIPE_FORMAT_R8G8B8_SSCALED:
 186       return BRW_SURFACEFORMAT_R8G8B8_SSCALED;
 187    case PIPE_FORMAT_R8G8B8A8_SSCALED:
 188       return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED;
 189
 190    default:
 191       assert(0);
 192       return 0;
 193    }
 194 }
 195
 196 static unsigned get_index_type(int type)
 197 {
 198    switch (type) {
 199    case 1: return BRW_INDEX_BYTE;
 200    case 2: return BRW_INDEX_WORD;
 201    case 4: return BRW_INDEX_DWORD;
 202    default: assert(0); return 0;
 203    }
 204 }
 205
 206
 207 boolean brw_upload_vertex_buffers( struct brw_context *brw )
 208 {
 209    struct brw_array_state vbp;
 210    unsigned nr_enabled = 0;
 211    unsigned i;
 212
 213    memset(&vbp, 0, sizeof(vbp));
 214
 215    /* This is a hardware limit:
 216     */
 217
 218    for (i = 0; i < BRW_VEP_MAX; i++)
 219    {
 220       if (brw->vb.vbo_array[i] == NULL) {
 221          nr_enabled = i;
 222          break;
 223       }
 224
 225       vbp.vb[i].vb0.bits.pitch = brw->vb.vbo_array[i]->pitch;
 226       vbp.vb[i].vb0.bits.pad = 0;
 227       vbp.vb[i].vb0.bits.access_type = BRW_VERTEXBUFFER_ACCESS_VERTEXDATA;
 228       vbp.vb[i].vb0.bits.vb_index = i;
 229       vbp.vb[i].offset = brw->vb.vbo_array[i]->buffer_offset;
 230       vbp.vb[i].buffer = brw->vb.vbo_array[i]->buffer;
 231       vbp.vb[i].max_index = brw->vb.vbo_array[i]->max_index;
 232    }
 233
 234
 235    vbp.header.bits.length = (1 + nr_enabled * 4) - 2;
 236    vbp.header.bits.opcode = CMD_VERTEX_BUFFER;
 237
 238    BEGIN_BATCH(vbp.header.bits.length+2, 0);
 239    OUT_BATCH( vbp.header.dword );
 240
 241    for (i = 0; i < nr_enabled; i++) {
 242       OUT_BATCH( vbp.vb[i].vb0.dword );
 243       OUT_RELOC( vbp.vb[i].buffer,  PIPE_BUFFER_USAGE_GPU_READ,
 244                  vbp.vb[i].offset);
 245       OUT_BATCH( vbp.vb[i].max_index );
 246       OUT_BATCH( vbp.vb[i].instance_data_step_rate );
 247    }
 248    ADVANCE_BATCH();
 249    return TRUE;
 250 }
 251
 252
 253
 254 boolean brw_upload_vertex_elements( struct brw_context *brw )
 255 {
 256    struct brw_vertex_element_packet vep;
 257
 258    unsigned i;
 259    unsigned nr_enabled = brw->attribs.VertexProgram->info.num_inputs;
 260
 261    memset(&vep, 0, sizeof(vep));
 262
 263    for (i = 0; i < nr_enabled; i++)
 264       vep.ve[i] = brw->vb.inputs[i];
 265
 266
 267    vep.header.length = (1 + nr_enabled * sizeof(vep.ve[0])/4) - 2;
 268    vep.header.opcode = CMD_VERTEX_ELEMENT;
 269    brw_cached_batch_struct(brw, &vep, 4 + nr_enabled * sizeof(vep.ve[0]));
 270
 271    return TRUE;
 272 }
 273
 274 boolean brw_upload_indices( struct brw_context *brw,
 275                             const struct pipe_buffer *index_buffer,
 276                             int ib_size, int start, int count)
 277 {
 278    /* Emit the indexbuffer packet:
 279     */
 280    {
 281       struct brw_indexbuffer ib;
 282
 283       memset(&ib, 0, sizeof(ib));
 284
 285       ib.header.bits.opcode = CMD_INDEX_BUFFER;
 286       ib.header.bits.length = sizeof(ib)/4 - 2;
 287       ib.header.bits.index_format = get_index_type(ib_size);
 288       ib.header.bits.cut_index_enable = 0;
 289
 290
 291       BEGIN_BATCH(4, 0);
 292       OUT_BATCH( ib.header.dword );
 293       OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start);
 294       OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start + count);
 295       OUT_BATCH( 0 );
 296       ADVANCE_BATCH();
 297    }
 298    return TRUE;
 299 }