src/gallium/drivers/i965simple/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include "brw_structs.h"
  37 #include "brw_defines.h"
  38
  39 #include "pipe/p_compiler.h"
  40 #include "pipe/p_shader_tokens.h"
  41
  42 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
  43 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
  44
  45 #define BRW_SWIZZLE_NOOP      BRW_SWIZZLE4(0,1,2,3)
  46 #define BRW_SWIZZLE_XYZW      BRW_SWIZZLE4(0,1,2,3)
  47 #define BRW_SWIZZLE_XXXX      BRW_SWIZZLE4(0,0,0,0)
  48 #define BRW_SWIZZLE_XYXY      BRW_SWIZZLE4(0,1,0,1)
  49
  50
  51 #define REG_SIZE (8*4)
  52
  53
  54 /* These aren't hardware structs, just something useful for us to pass around:
  55  *
  56  * Align1 operation has a lot of control over input ranges.  Used in
  57  * WM programs to implement shaders decomposed into "channel serial"
  58  * or "structure of array" form:
  59  */
  60 struct brw_reg
  61 {
  62    unsigned type:4;
  63    unsigned file:2;
  64    unsigned nr:8;
  65    unsigned subnr:5;            /* :1 in align16 */
  66    unsigned negate:1;           /* source only */
  67    unsigned abs:1;              /* source only */
  68    unsigned vstride:4;          /* source only */
  69    unsigned width:3;            /* src only, align1 only */
  70    unsigned hstride:2;                  /* src only, align1 only */
  71    unsigned address_mode:1;     /* relative addressing, hopefully! */
  72    unsigned pad0:1;
  73
  74    union {
  75       struct {
  76          unsigned swizzle:8;            /* src only, align16 only */
  77          unsigned writemask:4;          /* dest only, align16 only */
  78          int  indirect_offset:10;       /* relative addressing offset */
  79          unsigned pad1:10;              /* two dwords total */
  80       } bits;
  81
  82       float f;
  83       int   d;
  84       unsigned ud;
  85    } dw1;
  86 };
  87
  88
  89 struct brw_indirect {
  90    unsigned addr_subnr:4;
  91    int addr_offset:10;
  92    unsigned pad:18;
  93 };
  94
  95
  96 #define BRW_EU_MAX_INSN_STACK 5
  97 #define BRW_EU_MAX_INSN 1200
  98
  99 struct brw_compile {
 100    struct brw_instruction store[BRW_EU_MAX_INSN];
 101    unsigned nr_insn;
 102
 103    /* Allow clients to push/pop instruction state:
 104     */
 105    struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
 106    struct brw_instruction *current;
 107
 108    unsigned flag_value;
 109    boolean single_program_flow;
 110 };
 111
 112
 113
 114 static __inline int type_sz( unsigned type )
 115 {
 116    switch( type ) {
 117    case BRW_REGISTER_TYPE_UD:
 118    case BRW_REGISTER_TYPE_D:
 119    case BRW_REGISTER_TYPE_F:
 120       return 4;
 121    case BRW_REGISTER_TYPE_HF:
 122    case BRW_REGISTER_TYPE_UW:
 123    case BRW_REGISTER_TYPE_W:
 124       return 2;
 125    case BRW_REGISTER_TYPE_UB:
 126    case BRW_REGISTER_TYPE_B:
 127       return 1;
 128    default:
 129       return 0;
 130    }
 131 }
 132
 133 static __inline struct brw_reg brw_reg( unsigned file,
 134                                         unsigned nr,
 135                                         unsigned subnr,
 136                                         unsigned type,
 137                                         unsigned vstride,
 138                                         unsigned width,
 139                                         unsigned hstride,
 140                                         unsigned swizzle,
 141                                         unsigned writemask)
 142 {
 143
 144    struct brw_reg reg;
 145    reg.type = type;
 146    reg.file = file;
 147    reg.nr = nr;
 148    reg.subnr = subnr * type_sz(type);
 149    reg.negate = 0;
 150    reg.abs = 0;
 151    reg.vstride = vstride;
 152    reg.width = width;
 153    reg.hstride = hstride;
 154    reg.address_mode = BRW_ADDRESS_DIRECT;
 155    reg.pad0 = 0;
 156
 157    /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
 158     * set swizzle and writemask to W, as the lower bits of subnr will
 159     * be lost when converted to align16.  This is probably too much to
 160     * keep track of as you'd want it adjusted by suboffset(), etc.
 161     * Perhaps fix up when converting to align16?
 162     */
 163    reg.dw1.bits.swizzle = swizzle;
 164    reg.dw1.bits.writemask = writemask;
 165    reg.dw1.bits.indirect_offset = 0;
 166    reg.dw1.bits.pad1 = 0;
 167    return reg;
 168 }
 169
 170 static __inline struct brw_reg brw_vec16_reg( unsigned file,
 171                                               unsigned nr,
 172                                               unsigned subnr )
 173 {
 174    return brw_reg(file,
 175                   nr,
 176                   subnr,
 177                   BRW_REGISTER_TYPE_F,
 178                   BRW_VERTICAL_STRIDE_16,
 179                   BRW_WIDTH_16,
 180                   BRW_HORIZONTAL_STRIDE_1,
 181                   BRW_SWIZZLE_XYZW,
 182                   TGSI_WRITEMASK_XYZW);
 183 }
 184
 185 static __inline struct brw_reg brw_vec8_reg( unsigned file,
 186                                              unsigned nr,
 187                                              unsigned subnr )
 188 {
 189    return brw_reg(file,
 190                   nr,
 191                   subnr,
 192                   BRW_REGISTER_TYPE_F,
 193                   BRW_VERTICAL_STRIDE_8,
 194                   BRW_WIDTH_8,
 195                   BRW_HORIZONTAL_STRIDE_1,
 196                   BRW_SWIZZLE_XYZW,
 197                   TGSI_WRITEMASK_XYZW);
 198 }
 199
 200
 201 static __inline struct brw_reg brw_vec4_reg( unsigned file,
 202                                               unsigned nr,
 203                                               unsigned subnr )
 204 {
 205    return brw_reg(file,
 206                   nr,
 207                   subnr,
 208                   BRW_REGISTER_TYPE_F,
 209                   BRW_VERTICAL_STRIDE_4,
 210                   BRW_WIDTH_4,
 211                   BRW_HORIZONTAL_STRIDE_1,
 212                   BRW_SWIZZLE_XYZW,
 213                   TGSI_WRITEMASK_XYZW);
 214 }
 215
 216
 217 static __inline struct brw_reg brw_vec2_reg( unsigned file,
 218                                               unsigned nr,
 219                                               unsigned subnr )
 220 {
 221    return brw_reg(file,
 222                   nr,
 223                   subnr,
 224                   BRW_REGISTER_TYPE_F,
 225                   BRW_VERTICAL_STRIDE_2,
 226                   BRW_WIDTH_2,
 227                   BRW_HORIZONTAL_STRIDE_1,
 228                   BRW_SWIZZLE_XYXY,
 229                   TGSI_WRITEMASK_XY);
 230 }
 231
 232 static __inline struct brw_reg brw_vec1_reg( unsigned file,
 233                                              unsigned nr,
 234                                              unsigned subnr )
 235 {
 236    return brw_reg(file,
 237                   nr,
 238                   subnr,
 239                   BRW_REGISTER_TYPE_F,
 240                   BRW_VERTICAL_STRIDE_0,
 241                   BRW_WIDTH_1,
 242                   BRW_HORIZONTAL_STRIDE_0,
 243                   BRW_SWIZZLE_XXXX,
 244                   TGSI_WRITEMASK_X);
 245 }
 246
 247
 248 static __inline struct brw_reg retype( struct brw_reg reg,
 249                                        unsigned type )
 250 {
 251    reg.type = type;
 252    return reg;
 253 }
 254
 255 static __inline struct brw_reg suboffset( struct brw_reg reg,
 256                                           unsigned delta )
 257 {
 258    reg.subnr += delta * type_sz(reg.type);
 259    return reg;
 260 }
 261
 262
 263 static __inline struct brw_reg offset( struct brw_reg reg,
 264                                        unsigned delta )
 265 {
 266    reg.nr += delta;
 267    return reg;
 268 }
 269
 270
 271 static __inline struct brw_reg byte_offset( struct brw_reg reg,
 272                                             unsigned bytes )
 273 {
 274    unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
 275    reg.nr = newoffset / REG_SIZE;
 276    reg.subnr = newoffset % REG_SIZE;
 277    return reg;
 278 }
 279
 280
 281 static __inline struct brw_reg brw_uw16_reg( unsigned file,
 282                                              unsigned nr,
 283                                              unsigned subnr )
 284 {
 285    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 286 }
 287
 288 static __inline struct brw_reg brw_uw8_reg( unsigned file,
 289                                             unsigned nr,
 290                                             unsigned subnr )
 291 {
 292    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 293 }
 294
 295 static __inline struct brw_reg brw_uw1_reg( unsigned file,
 296                                             unsigned nr,
 297                                             unsigned subnr )
 298 {
 299    return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 300 }
 301
 302 static __inline struct brw_reg brw_imm_reg( unsigned type )
 303 {
 304    return brw_reg( BRW_IMMEDIATE_VALUE,
 305                    0,
 306                    0,
 307                    type,
 308                    BRW_VERTICAL_STRIDE_0,
 309                    BRW_WIDTH_1,
 310                    BRW_HORIZONTAL_STRIDE_0,
 311                    0,
 312                    0);
 313 }
 314
 315 static __inline struct brw_reg brw_imm_f( float f )
 316 {
 317    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
 318    imm.dw1.f = f;
 319    return imm;
 320 }
 321
 322 static __inline struct brw_reg brw_imm_d( int d )
 323 {
 324    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
 325    imm.dw1.d = d;
 326    return imm;
 327 }
 328
 329 static __inline struct brw_reg brw_imm_ud( unsigned ud )
 330 {
 331    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
 332    imm.dw1.ud = ud;
 333    return imm;
 334 }
 335
 336 static __inline struct brw_reg brw_imm_uw( ushort uw )
 337 {
 338    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
 339    imm.dw1.ud = uw;
 340    return imm;
 341 }
 342
 343 static __inline struct brw_reg brw_imm_w( short w )
 344 {
 345    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
 346    imm.dw1.d = w;
 347    return imm;
 348 }
 349
 350 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
 351  * numbers alias with _V and _VF below:
 352  */
 353
 354 /* Vector of eight signed half-byte values:
 355  */
 356 static __inline struct brw_reg brw_imm_v( unsigned v )
 357 {
 358    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
 359    imm.vstride = BRW_VERTICAL_STRIDE_0;
 360    imm.width = BRW_WIDTH_8;
 361    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 362    imm.dw1.ud = v;
 363    return imm;
 364 }
 365
 366 /* Vector of four 8-bit float values:
 367  */
 368 static __inline struct brw_reg brw_imm_vf( unsigned v )
 369 {
 370    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 371    imm.vstride = BRW_VERTICAL_STRIDE_0;
 372    imm.width = BRW_WIDTH_4;
 373    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 374    imm.dw1.ud = v;
 375    return imm;
 376 }
 377
 378 #define VF_ZERO 0x0
 379 #define VF_ONE  0x30
 380 #define VF_NEG  (1<<7)
 381
 382 static __inline struct brw_reg brw_imm_vf4( unsigned v0,
 383                                             unsigned v1,
 384                                             unsigned v2,
 385                                             unsigned v3)
 386 {
 387    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 388    imm.vstride = BRW_VERTICAL_STRIDE_0;
 389    imm.width = BRW_WIDTH_4;
 390    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 391    imm.dw1.ud = ((v0 << 0) |
 392                  (v1 << 8) |
 393                  (v2 << 16) |
 394                  (v3 << 24));
 395    return imm;
 396 }
 397
 398
 399 static __inline struct brw_reg brw_address( struct brw_reg reg )
 400 {
 401    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
 402 }
 403
 404
 405 static __inline struct brw_reg brw_vec1_grf( unsigned nr,
 406                                                unsigned subnr )
 407 {
 408    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 409 }
 410
 411 static __inline struct brw_reg brw_vec8_grf( unsigned nr,
 412                                              unsigned subnr )
 413 {
 414    return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 415 }
 416
 417 static __inline struct brw_reg brw_vec4_grf( unsigned nr,
 418                                              unsigned subnr )
 419 {
 420    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 421 }
 422
 423
 424 static __inline struct brw_reg brw_vec2_grf( unsigned nr,
 425                                              unsigned subnr )
 426 {
 427    return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 428 }
 429
 430 static __inline struct brw_reg brw_uw8_grf( unsigned nr,
 431                                             unsigned subnr )
 432 {
 433    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 434 }
 435
 436 static __inline struct brw_reg brw_null_reg( void )
 437 {
 438    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 439                        BRW_ARF_NULL,
 440                        0);
 441 }
 442
 443 static __inline struct brw_reg brw_address_reg( unsigned subnr )
 444 {
 445    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 446                       BRW_ARF_ADDRESS,
 447                       subnr);
 448 }
 449
 450 /* If/else instructions break in align16 mode if writemask & swizzle
 451  * aren't xyzw.  This goes against the convention for other scalar
 452  * regs:
 453  */
 454 static __inline struct brw_reg brw_ip_reg( void )
 455 {
 456    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 457                   BRW_ARF_IP,
 458                   0,
 459                   BRW_REGISTER_TYPE_UD,
 460                   BRW_VERTICAL_STRIDE_4, /* ? */
 461                   BRW_WIDTH_1,
 462                   BRW_HORIZONTAL_STRIDE_0,
 463                   BRW_SWIZZLE_XYZW, /* NOTE! */
 464                   TGSI_WRITEMASK_XYZW); /* NOTE! */
 465 }
 466
 467 static __inline struct brw_reg brw_acc_reg( void )
 468 {
 469    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 470                        BRW_ARF_ACCUMULATOR,
 471                        0);
 472 }
 473
 474
 475 static __inline struct brw_reg brw_flag_reg( void )
 476 {
 477    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 478                       BRW_ARF_FLAG,
 479                       0);
 480 }
 481
 482
 483 static __inline struct brw_reg brw_mask_reg( unsigned subnr )
 484 {
 485    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 486                       BRW_ARF_MASK,
 487                       subnr);
 488 }
 489
 490 static __inline struct brw_reg brw_message_reg( unsigned nr )
 491 {
 492    return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE,
 493                        nr,
 494                        0);
 495 }
 496
 497
 498
 499
 500 /* This is almost always called with a numeric constant argument, so
 501  * make things easy to evaluate at compile time:
 502  */
 503 static __inline unsigned cvt( unsigned val )
 504 {
 505    switch (val) {
 506    case 0: return 0;
 507    case 1: return 1;
 508    case 2: return 2;
 509    case 4: return 3;
 510    case 8: return 4;
 511    case 16: return 5;
 512    case 32: return 6;
 513    }
 514    return 0;
 515 }
 516
 517 static __inline struct brw_reg stride( struct brw_reg reg,
 518                                        unsigned vstride,
 519                                        unsigned width,
 520                                        unsigned hstride )
 521 {
 522
 523    reg.vstride = cvt(vstride);
 524    reg.width = cvt(width) - 1;
 525    reg.hstride = cvt(hstride);
 526    return reg;
 527 }
 528
 529 static __inline struct brw_reg vec16( struct brw_reg reg )
 530 {
 531    return stride(reg, 16,16,1);
 532 }
 533
 534 static __inline struct brw_reg vec8( struct brw_reg reg )
 535 {
 536    return stride(reg, 8,8,1);
 537 }
 538
 539 static __inline struct brw_reg vec4( struct brw_reg reg )
 540 {
 541    return stride(reg, 4,4,1);
 542 }
 543
 544 static __inline struct brw_reg vec2( struct brw_reg reg )
 545 {
 546    return stride(reg, 2,2,1);
 547 }
 548
 549 static __inline struct brw_reg vec1( struct brw_reg reg )
 550 {
 551    return stride(reg, 0,1,0);
 552 }
 553
 554 static __inline struct brw_reg get_element( struct brw_reg reg, unsigned elt )
 555 {
 556    return vec1(suboffset(reg, elt));
 557 }
 558
 559 static __inline struct brw_reg get_element_ud( struct brw_reg reg, unsigned elt )
 560 {
 561    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
 562 }
 563
 564
 565 static __inline struct brw_reg brw_swizzle( struct brw_reg reg,
 566                                             unsigned x,
 567                                             unsigned y,
 568                                             unsigned z,
 569                                             unsigned w)
 570 {
 571    reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
 572                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
 573                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
 574                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
 575    return reg;
 576 }
 577
 578
 579 static __inline struct brw_reg brw_swizzle1( struct brw_reg reg,
 580                                              unsigned x )
 581 {
 582    return brw_swizzle(reg, x, x, x, x);
 583 }
 584
 585 static __inline struct brw_reg brw_writemask( struct brw_reg reg,
 586                                               unsigned mask )
 587 {
 588    reg.dw1.bits.writemask &= mask;
 589    return reg;
 590 }
 591
 592 static __inline struct brw_reg brw_set_writemask( struct brw_reg reg,
 593                                                   unsigned mask )
 594 {
 595    reg.dw1.bits.writemask = mask;
 596    return reg;
 597 }
 598
 599 static __inline struct brw_reg negate( struct brw_reg reg )
 600 {
 601    reg.negate ^= 1;
 602    return reg;
 603 }
 604
 605 static __inline struct brw_reg brw_abs( struct brw_reg reg )
 606 {
 607    reg.abs = 1;
 608    return reg;
 609 }
 610
 611 /***********************************************************************
 612  */
 613 static __inline struct brw_reg brw_vec4_indirect( unsigned subnr,
 614                                                   int offset )
 615 {
 616    struct brw_reg reg =  brw_vec4_grf(0, 0);
 617    reg.subnr = subnr;
 618    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 619    reg.dw1.bits.indirect_offset = offset;
 620    return reg;
 621 }
 622
 623 static __inline struct brw_reg brw_vec1_indirect( unsigned subnr,
 624                                                   int offset )
 625 {
 626    struct brw_reg reg =  brw_vec1_grf(0, 0);
 627    reg.subnr = subnr;
 628    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 629    reg.dw1.bits.indirect_offset = offset;
 630    return reg;
 631 }
 632
 633 static __inline struct brw_reg deref_4f(struct brw_indirect ptr, int offset)
 634 {
 635    return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 636 }
 637
 638 static __inline struct brw_reg deref_1f(struct brw_indirect ptr, int offset)
 639 {
 640    return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 641 }
 642
 643 static __inline struct brw_reg deref_4b(struct brw_indirect ptr, int offset)
 644 {
 645    return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
 646 }
 647
 648 static __inline struct brw_reg deref_1uw(struct brw_indirect ptr, int offset)
 649 {
 650    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
 651 }
 652
 653 static __inline struct brw_reg deref_1ud(struct brw_indirect ptr, int offset)
 654 {
 655    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
 656 }
 657
 658 static __inline struct brw_reg get_addr_reg(struct brw_indirect ptr)
 659 {
 660    return brw_address_reg(ptr.addr_subnr);
 661 }
 662
 663 static __inline struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, int offset )
 664 {
 665    ptr.addr_offset += offset;
 666    return ptr;
 667 }
 668
 669 static __inline struct brw_indirect brw_indirect( unsigned addr_subnr, int offset )
 670 {
 671    struct brw_indirect ptr;
 672    ptr.addr_subnr = addr_subnr;
 673    ptr.addr_offset = offset;
 674    ptr.pad = 0;
 675    return ptr;
 676 }
 677
 678 static __inline struct brw_instruction *current_insn( struct brw_compile *p)
 679 {
 680         return &p->store[p->nr_insn];
 681 }
 682
 683 void brw_pop_insn_state( struct brw_compile *p );
 684 void brw_push_insn_state( struct brw_compile *p );
 685 void brw_set_mask_control( struct brw_compile *p, unsigned value );
 686 void brw_set_saturate( struct brw_compile *p, unsigned value );
 687 void brw_set_access_mode( struct brw_compile *p, unsigned access_mode );
 688 void brw_set_compression_control( struct brw_compile *p, boolean control );
 689 void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value );
 690 void brw_set_predicate_control( struct brw_compile *p, unsigned pc );
 691 void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional );
 692
 693 void brw_init_compile( struct brw_compile *p );
 694 const unsigned *brw_get_program( struct brw_compile *p, unsigned *sz );
 695
 696
 697 struct brw_instruction *brw_alu1( struct brw_compile *p,
 698                                   unsigned opcode,
 699                                   struct brw_reg dest,
 700                                   struct brw_reg src );
 701
 702 struct brw_instruction *brw_alu2(struct brw_compile *p,
 703                                  unsigned opcode,
 704                                  struct brw_reg dest,
 705                                  struct brw_reg src0,
 706                                  struct brw_reg src1 );
 707
 708 /* Helpers for regular instructions:
 709  */
 710 #define ALU1(OP)                                        \
 711 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 712               struct brw_reg dest,                      \
 713               struct brw_reg src0);
 714
 715 #define ALU2(OP)                                        \
 716 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 717               struct brw_reg dest,                      \
 718               struct brw_reg src0,                      \
 719               struct brw_reg src1);
 720
 721 ALU1(MOV)
 722 ALU2(SEL)
 723 ALU1(NOT)
 724 ALU2(AND)
 725 ALU2(OR)
 726 ALU2(XOR)
 727 ALU2(SHR)
 728 ALU2(SHL)
 729 ALU2(RSR)
 730 ALU2(RSL)
 731 ALU2(ASR)
 732 ALU2(JMPI)
 733 ALU2(ADD)
 734 ALU2(MUL)
 735 ALU1(FRC)
 736 ALU1(RNDD)
 737 ALU2(MAC)
 738 ALU2(MACH)
 739 ALU1(LZD)
 740 ALU2(DP4)
 741 ALU2(DPH)
 742 ALU2(DP3)
 743 ALU2(DP2)
 744 ALU2(LINE)
 745
 746 #undef ALU1
 747 #undef ALU2
 748
 749
 750
 751 /* Helpers for SEND instruction:
 752  */
 753 void brw_urb_WRITE(struct brw_compile *p,
 754                    struct brw_reg dest,
 755                    unsigned msg_reg_nr,
 756                    struct brw_reg src0,
 757                    boolean allocate,
 758                    boolean used,
 759                    unsigned msg_length,
 760                    unsigned response_length,
 761                    boolean eot,
 762                    boolean writes_complete,
 763                    unsigned offset,
 764                    unsigned swizzle);
 765
 766 void brw_fb_WRITE(struct brw_compile *p,
 767                    struct brw_reg dest,
 768                    unsigned msg_reg_nr,
 769                    struct brw_reg src0,
 770                    unsigned binding_table_index,
 771                    unsigned msg_length,
 772                    unsigned response_length,
 773                    boolean eot);
 774
 775 void brw_SAMPLE(struct brw_compile *p,
 776                 struct brw_reg dest,
 777                 unsigned msg_reg_nr,
 778                 struct brw_reg src0,
 779                 unsigned binding_table_index,
 780                 unsigned sampler,
 781                 unsigned writemask,
 782                 unsigned msg_type,
 783                 unsigned response_length,
 784                 unsigned msg_length,
 785                 boolean eot);
 786
 787 void brw_math_16( struct brw_compile *p,
 788                   struct brw_reg dest,
 789                   unsigned function,
 790                   unsigned saturate,
 791                   unsigned msg_reg_nr,
 792                   struct brw_reg src,
 793                   unsigned precision );
 794
 795 void brw_math( struct brw_compile *p,
 796                struct brw_reg dest,
 797                unsigned function,
 798                unsigned saturate,
 799                unsigned msg_reg_nr,
 800                struct brw_reg src,
 801                unsigned data_type,
 802                unsigned precision );
 803
 804 void brw_dp_READ_16( struct brw_compile *p,
 805                      struct brw_reg dest,
 806                      unsigned msg_reg_nr,
 807                      unsigned scratch_offset );
 808
 809 void brw_dp_WRITE_16( struct brw_compile *p,
 810                       struct brw_reg src,
 811                       unsigned msg_reg_nr,
 812                       unsigned scratch_offset );
 813
 814 /* If/else/endif.  Works by manipulating the execution flags on each
 815  * channel.
 816  */
 817 struct brw_instruction *brw_IF(struct brw_compile *p,
 818                                unsigned execute_size);
 819
 820 struct brw_instruction *brw_ELSE(struct brw_compile *p,
 821                                  struct brw_instruction *if_insn);
 822
 823 void brw_ENDIF(struct brw_compile *p,
 824                struct brw_instruction *if_or_else_insn);
 825
 826
 827 /* DO/WHILE loops:
 828  */
 829 struct brw_instruction *brw_DO(struct brw_compile *p,
 830                                unsigned execute_size);
 831
 832 struct brw_instruction *brw_WHILE(struct brw_compile *p,
 833                struct brw_instruction *patch_insn);
 834
 835 struct brw_instruction *brw_BREAK(struct brw_compile *p);
 836 struct brw_instruction *brw_CONT(struct brw_compile *p);
 837 /* Forward jumps:
 838  */
 839 void brw_land_fwd_jump(struct brw_compile *p,
 840                        struct brw_instruction *jmp_insn);
 841
 842
 843
 844 void brw_NOP(struct brw_compile *p);
 845
 846 /* Special case: there is never a destination, execution size will be
 847  * taken from src0:
 848  */
 849 void brw_CMP(struct brw_compile *p,
 850              struct brw_reg dest,
 851              unsigned conditional,
 852              struct brw_reg src0,
 853              struct brw_reg src1);
 854
 855 void brw_print_reg( struct brw_reg reg );
 856
 857
 858 /***********************************************************************
 859  * brw_eu_util.c:
 860  */
 861
 862 void brw_copy_indirect_to_indirect(struct brw_compile *p,
 863                                    struct brw_indirect dst_ptr,
 864                                    struct brw_indirect src_ptr,
 865                                    unsigned count);
 866
 867 void brw_copy_from_indirect(struct brw_compile *p,
 868                             struct brw_reg dst,
 869                             struct brw_indirect ptr,
 870                             unsigned count);
 871
 872 void brw_copy4(struct brw_compile *p,
 873                struct brw_reg dst,
 874                struct brw_reg src,
 875                unsigned count);
 876
 877 void brw_copy8(struct brw_compile *p,
 878                struct brw_reg dst,
 879                struct brw_reg src,
 880                unsigned count);
 881
 882 void brw_math_invert( struct brw_compile *p,
 883                       struct brw_reg dst,
 884                       struct brw_reg src);
 885
 886 void brw_set_src1( struct brw_instruction *insn,
 887                           struct brw_reg reg );
 888 #endif