src/gallium/drivers/i965simple/brw_urb.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 //#include "brw_state.h"
  35 #include "brw_batch.h"
  36 #include "brw_defines.h"
  37
  38 #define VS 0
  39 #define GS 1
  40 #define CLP 2
  41 #define SF 3
  42 #define CS 4
  43
  44 /* XXX: Are the min_entry_size numbers useful?
  45  * XXX: Verify min_nr_entries, esp for VS.
  46  * XXX: Verify SF min_entry_size.
  47  */
  48 static const struct {
  49    unsigned min_nr_entries;
  50    unsigned preferred_nr_entries;
  51    unsigned min_entry_size;
  52    unsigned max_entry_size;
  53 } limits[CS+1] = {
  54    { 8, 32, 1, 5 },                     /* vs */
  55    { 4, 8,  1, 5 },                     /* gs */
  56    { 6, 8,  1, 5 },                     /* clp */
  57    { 1, 8,  1, 12 },                    /* sf */
  58    { 1, 4,  1, 32 }                     /* cs */
  59 };
  60
  61
  62 static boolean check_urb_layout( struct brw_context *brw )
  63 {
  64    brw->urb.vs_start = 0;
  65    brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize;
  66    brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize;
  67    brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize;
  68    brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize;
  69
  70    return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= 256;
  71 }
  72
  73 /* Most minimal update, forces re-emit of URB fence packet after GS
  74  * unit turned on/off.
  75  */
  76 static void recalculate_urb_fence( struct brw_context *brw )
  77 {
  78    unsigned csize = brw->curbe.total_size;
  79    unsigned vsize = brw->vs.prog_data->urb_entry_size;
  80    unsigned sfsize = brw->sf.prog_data->urb_entry_size;
  81
  82    if (csize < limits[CS].min_entry_size)
  83       csize = limits[CS].min_entry_size;
  84
  85    if (vsize < limits[VS].min_entry_size)
  86       vsize = limits[VS].min_entry_size;
  87
  88    if (sfsize < limits[SF].min_entry_size)
  89       sfsize = limits[SF].min_entry_size;
  90
  91    if (brw->urb.vsize < vsize ||
  92        brw->urb.sfsize < sfsize ||
  93        brw->urb.csize < csize ||
  94        (brw->urb.constrained && (brw->urb.vsize > brw->urb.vsize ||
  95                                  brw->urb.sfsize > brw->urb.sfsize ||
  96                                  brw->urb.csize > brw->urb.csize))) {
  97
  98
  99       brw->urb.csize = csize;
 100       brw->urb.sfsize = sfsize;
 101       brw->urb.vsize = vsize;
 102
 103       brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 104       brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries;
 105       brw->urb.nr_clip_entries = limits[CLP].preferred_nr_entries;
 106       brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
 107       brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries;
 108
 109       if (!check_urb_layout(brw)) {
 110          brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
 111          brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
 112          brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
 113          brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
 114          brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
 115
 116          brw->urb.constrained = 1;
 117
 118          if (!check_urb_layout(brw)) {
 119             /* This is impossible, given the maximal sizes of urb
 120              * entries and the values for minimum nr of entries
 121              * provided above.
 122              */
 123             debug_printf("couldn't calculate URB layout!\n");
 124             exit(1);
 125          }
 126
 127          if (BRW_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS))
 128             debug_printf("URB CONSTRAINED\n");
 129       }
 130       else
 131          brw->urb.constrained = 0;
 132
 133       if (BRW_DEBUG & DEBUG_URB)
 134          debug_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
 135                       brw->urb.vs_start,
 136                       brw->urb.gs_start,
 137                       brw->urb.clip_start,
 138                       brw->urb.sf_start,
 139                       brw->urb.cs_start,
 140                       256);
 141
 142       brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
 143    }
 144 }
 145
 146
 147 const struct brw_tracked_state brw_recalculate_urb_fence = {
 148    .dirty = {
 149       .brw = BRW_NEW_CURBE_OFFSETS,
 150       .cache = (CACHE_NEW_VS_PROG |
 151                 CACHE_NEW_SF_PROG)
 152    },
 153    .update = recalculate_urb_fence
 154 };
 155
 156
 157
 158
 159
 160 void brw_upload_urb_fence(struct brw_context *brw)
 161 {
 162    struct brw_urb_fence uf;
 163    memset(&uf, 0, sizeof(uf));
 164
 165    uf.header.opcode = CMD_URB_FENCE;
 166    uf.header.length = sizeof(uf)/4-2;
 167    uf.header.vs_realloc = 1;
 168    uf.header.gs_realloc = 1;
 169    uf.header.clp_realloc = 1;
 170    uf.header.sf_realloc = 1;
 171    uf.header.vfe_realloc = 1;
 172    uf.header.cs_realloc = 1;
 173
 174    /* The ordering below is correct, not the layout in the
 175     * instruction.
 176     *
 177     * There are 256 urb reg pairs in total.
 178     */
 179    uf.bits0.vs_fence  = brw->urb.gs_start;
 180    uf.bits0.gs_fence  = brw->urb.clip_start;
 181    uf.bits0.clp_fence = brw->urb.sf_start;
 182    uf.bits1.sf_fence  = brw->urb.cs_start;
 183    uf.bits1.cs_fence  = 256;
 184
 185    BRW_BATCH_STRUCT(brw, &uf);
 186 }