Merge remote branch 'origin/master' into radeon-rewrite
[mesa.git] / src / gallium / drivers / i965simple / brw_wm_sampler_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "brw_defines.h"
36
37 #include "util/u_math.h"
38 #include "util/u_memory.h"
39
40
41 #define COMPAREFUNC_ALWAYS 0
42 #define COMPAREFUNC_NEVER 0x1
43 #define COMPAREFUNC_LESS 0x2
44 #define COMPAREFUNC_EQUAL 0x3
45 #define COMPAREFUNC_LEQUAL 0x4
46 #define COMPAREFUNC_GREATER 0x5
47 #define COMPAREFUNC_NOTEQUAL 0x6
48 #define COMPAREFUNC_GEQUAL 0x7
49
50 /* Samplers aren't strictly wm state from the hardware's perspective,
51 * but that is the only situation in which we use them in this driver.
52 */
53
54 static int intel_translate_shadow_compare_func(unsigned func)
55 {
56 switch(func) {
57 case PIPE_FUNC_NEVER:
58 return COMPAREFUNC_ALWAYS;
59 case PIPE_FUNC_LESS:
60 return COMPAREFUNC_LEQUAL;
61 case PIPE_FUNC_LEQUAL:
62 return COMPAREFUNC_LESS;
63 case PIPE_FUNC_GREATER:
64 return COMPAREFUNC_GEQUAL;
65 case PIPE_FUNC_GEQUAL:
66 return COMPAREFUNC_GREATER;
67 case PIPE_FUNC_NOTEQUAL:
68 return COMPAREFUNC_EQUAL;
69 case PIPE_FUNC_EQUAL:
70 return COMPAREFUNC_NOTEQUAL;
71 case PIPE_FUNC_ALWAYS:
72 return COMPAREFUNC_NEVER;
73 }
74
75 debug_printf("Unknown value in %s: %x\n", __FUNCTION__, func);
76 return COMPAREFUNC_NEVER;
77 }
78
79 /* The brw (and related graphics cores) do not support GL_CLAMP. The
80 * Intel drivers for "other operating systems" implement GL_CLAMP as
81 * GL_CLAMP_TO_EDGE, so the same is done here.
82 */
83 static unsigned translate_wrap_mode( int wrap )
84 {
85 switch( wrap ) {
86 case PIPE_TEX_WRAP_REPEAT:
87 return BRW_TEXCOORDMODE_WRAP;
88 case PIPE_TEX_WRAP_CLAMP:
89 return BRW_TEXCOORDMODE_CLAMP;
90 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
91 return BRW_TEXCOORDMODE_CLAMP; /* conform likes it this way */
92 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
93 return BRW_TEXCOORDMODE_CLAMP_BORDER;
94 case PIPE_TEX_WRAP_MIRROR_REPEAT:
95 return BRW_TEXCOORDMODE_MIRROR;
96 default:
97 return BRW_TEXCOORDMODE_WRAP;
98 }
99 }
100
101
102 static unsigned U_FIXED(float value, unsigned frac_bits)
103 {
104 value *= (1<<frac_bits);
105 return value < 0 ? 0 : value;
106 }
107
108 static int S_FIXED(float value, unsigned frac_bits)
109 {
110 return value * (1<<frac_bits);
111 }
112
113
114 static unsigned upload_default_color( struct brw_context *brw,
115 const float *color )
116 {
117 struct brw_sampler_default_color sdc;
118
119 COPY_4V(sdc.color, color);
120
121 return brw_cache_data( &brw->cache[BRW_SAMPLER_DEFAULT_COLOR], &sdc );
122 }
123
124
125 /*
126 */
127 static void brw_update_sampler_state( const struct pipe_sampler_state *pipe_sampler,
128 unsigned sdc_gs_offset,
129 struct brw_sampler_state *sampler)
130 {
131 memset(sampler, 0, sizeof(*sampler));
132
133 switch (pipe_sampler->min_mip_filter) {
134 case PIPE_TEX_FILTER_NEAREST:
135 sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
136 break;
137 case PIPE_TEX_FILTER_LINEAR:
138 sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
139 break;
140 case PIPE_TEX_FILTER_ANISO:
141 sampler->ss0.min_filter = BRW_MAPFILTER_ANISOTROPIC;
142 break;
143 default:
144 break;
145 }
146
147 switch (pipe_sampler->min_mip_filter) {
148 case PIPE_TEX_MIPFILTER_NEAREST:
149 sampler->ss0.mip_filter = BRW_MIPFILTER_NEAREST;
150 break;
151 case PIPE_TEX_MIPFILTER_LINEAR:
152 sampler->ss0.mip_filter = BRW_MIPFILTER_LINEAR;
153 break;
154 case PIPE_TEX_MIPFILTER_NONE:
155 sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
156 break;
157 default:
158 break;
159 }
160 /* Set Anisotropy:
161 */
162 switch (pipe_sampler->mag_img_filter) {
163 case PIPE_TEX_FILTER_NEAREST:
164 sampler->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
165 break;
166 case PIPE_TEX_FILTER_LINEAR:
167 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
168 break;
169 case PIPE_TEX_FILTER_ANISO:
170 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
171 break;
172 default:
173 break;
174 }
175
176 if (pipe_sampler->max_anisotropy > 2.0) {
177 sampler->ss3.max_aniso = MAX2((pipe_sampler->max_anisotropy - 2) / 2,
178 BRW_ANISORATIO_16);
179 }
180
181 sampler->ss1.s_wrap_mode = translate_wrap_mode(pipe_sampler->wrap_s);
182 sampler->ss1.r_wrap_mode = translate_wrap_mode(pipe_sampler->wrap_r);
183 sampler->ss1.t_wrap_mode = translate_wrap_mode(pipe_sampler->wrap_t);
184
185 /* Fulsim complains if I don't do this. Hardware doesn't mind:
186 */
187 #if 0
188 if (texObj->Target == GL_TEXTURE_CUBE_MAP_ARB) {
189 sampler->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CUBE;
190 sampler->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CUBE;
191 sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CUBE;
192 }
193 #endif
194
195 /* Set shadow function:
196 */
197 if (pipe_sampler->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
198 /* Shadowing is "enabled" by emitting a particular sampler
199 * message (sample_c). So need to recompile WM program when
200 * shadow comparison is enabled on each/any texture unit.
201 */
202 sampler->ss0.shadow_function = intel_translate_shadow_compare_func(pipe_sampler->compare_func);
203 }
204
205 /* Set LOD bias:
206 */
207 sampler->ss0.lod_bias = S_FIXED(CLAMP(pipe_sampler->lod_bias, -16, 15), 6);
208
209 sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
210 sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
211
212 /* Set BaseMipLevel, MaxLOD, MinLOD:
213 *
214 * XXX: I don't think that using firstLevel, lastLevel works,
215 * because we always setup the surface state as if firstLevel ==
216 * level zero. Probably have to subtract firstLevel from each of
217 * these:
218 */
219 sampler->ss0.base_level = U_FIXED(0, 1);
220
221 sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(pipe_sampler->max_lod, 0), 13), 6);
222 sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(pipe_sampler->min_lod, 0), 13), 6);
223
224 sampler->ss2.default_color_pointer = sdc_gs_offset >> 5;
225 }
226
227
228
229 /* All samplers must be uploaded in a single contiguous array, which
230 * complicates various things. However, this is still too confusing -
231 * FIXME: simplify all the different new texture state flags.
232 */
233 static void upload_wm_samplers(struct brw_context *brw)
234 {
235 unsigned unit;
236 unsigned sampler_count = 0;
237
238 /* BRW_NEW_SAMPLER */
239 for (unit = 0; unit < brw->num_textures && unit < brw->num_samplers;
240 unit++) {
241 /* determine unit enable/disable by looking for a bound texture */
242 if (brw->attribs.Texture[unit]) {
243 const struct pipe_sampler_state *sampler = brw->attribs.Samplers[unit];
244 unsigned sdc_gs_offset = upload_default_color(brw, sampler->border_color);
245
246 brw_update_sampler_state(sampler,
247 sdc_gs_offset,
248 &brw->wm.sampler[unit]);
249
250 sampler_count = unit + 1;
251 }
252 }
253
254 if (brw->wm.sampler_count != sampler_count) {
255 brw->wm.sampler_count = sampler_count;
256 brw->state.dirty.cache |= CACHE_NEW_SAMPLER;
257 }
258
259 brw->wm.sampler_gs_offset = 0;
260
261 if (brw->wm.sampler_count)
262 brw->wm.sampler_gs_offset =
263 brw_cache_data_sz(&brw->cache[BRW_SAMPLER],
264 brw->wm.sampler,
265 sizeof(struct brw_sampler_state) * brw->wm.sampler_count);
266 }
267
268 const struct brw_tracked_state brw_wm_samplers = {
269 .dirty = {
270 .brw = BRW_NEW_SAMPLER,
271 .cache = 0
272 },
273 .update = upload_wm_samplers
274 };
275