src/gallium/drivers/i965simple/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35 #include "brw_defines.h"
  36 #include "brw_wm.h"
  37 #include "util/u_math.h"
  38 #include "util/u_memory.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43 static void upload_wm_unit(struct brw_context *brw )
  44 {
  45    struct brw_wm_unit_state wm;
  46    unsigned max_threads;
  47    unsigned per_thread;
  48
  49    if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
  50       max_threads = 0;
  51    else
  52       max_threads = 31;
  53
  54
  55    memset(&wm, 0, sizeof(wm));
  56
  57    /* CACHE_NEW_WM_PROG */
  58    wm.thread0.grf_reg_count = align(brw->wm.prog_data->total_grf, 16) / 16 - 1;
  59    wm.thread0.kernel_start_pointer = brw->wm.prog_gs_offset >> 6;
  60    wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  61    wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  62    wm.thread3.const_urb_entry_read_length = brw->wm.prog_data->curb_read_length;
  63
  64    wm.wm5.max_threads = max_threads;
  65
  66    per_thread = align(brw->wm.prog_data->total_scratch, 1024);
  67    assert(per_thread <= 12 * 1024);
  68
  69 #if 0
  70    if (brw->wm.prog_data->total_scratch) {
  71       unsigned total = per_thread * (max_threads + 1);
  72
  73       /* Scratch space -- just have to make sure there is sufficient
  74        * allocated for the active program and current number of threads.
  75        */
  76       brw->wm.scratch_buffer_size = total;
  77       if (brw->wm.scratch_buffer &&
  78           brw->wm.scratch_buffer_size > brw->wm.scratch_buffer->size) {
  79          dri_bo_unreference(brw->wm.scratch_buffer);
  80          brw->wm.scratch_buffer = NULL;
  81       }
  82       if (!brw->wm.scratch_buffer) {
  83          brw->wm.scratch_buffer = dri_bo_alloc(intel->intelScreen->bufmgr,
  84                                                "wm scratch",
  85                                                brw->wm.scratch_buffer_size,
  86                                                4096, DRM_BO_FLAG_MEM_TT);
  87       }
  88    }
  89    /* XXX: Scratch buffers are not implemented correectly.
  90     *
  91     * The scratch offset to be programmed into wm is relative to the general
  92     * state base address.  However, using dri_bo_alloc/dri_bo_emit_reloc (or
  93     * the previous bmGenBuffers scheme), we get an offset relative to the
  94     * start of framebuffer.  Even before then, it was broken in other ways,
  95     * so just fail for now if we hit that path.
  96     */
  97    assert(brw->wm.prog_data->total_scratch == 0);
  98 #endif
  99
 100    /* CACHE_NEW_SURFACE */
 101    wm.thread1.binding_table_entry_count = brw->wm.nr_surfaces;
 102
 103    /* BRW_NEW_CURBE_OFFSETS */
 104    wm.thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 105
 106    wm.thread3.urb_entry_read_offset = 0;
 107    wm.thread1.depth_coef_urb_read_offset = 1;
 108    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 109
 110    /* CACHE_NEW_SAMPLER */
 111    wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
 112    wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5;
 113
 114    /* BRW_NEW_FRAGMENT_PROGRAM */
 115    {
 116       const struct brw_fragment_program *fp = brw->attribs.FragmentProgram;
 117
 118       if (fp->UsesDepth)
 119          wm.wm5.program_uses_depth = 1; /* as far as we can tell */
 120
 121       if (fp->info.writes_z)
 122          wm.wm5.program_computes_depth = 1;
 123
 124       /* BRW_NEW_ALPHA_TEST */
 125       if (fp->info.uses_kill ||
 126           brw->attribs.DepthStencil->alpha.enabled)
 127          wm.wm5.program_uses_killpixel = 1;
 128
 129       wm.wm5.enable_8_pix = 1;
 130    }
 131
 132    wm.wm5.thread_dispatch_enable = 1;   /* AKA: color_write */
 133    wm.wm5.legacy_line_rast = 0;
 134    wm.wm5.legacy_global_depth_bias = 0;
 135    wm.wm5.early_depth_test = 1;         /* never need to disable */
 136    wm.wm5.line_aa_region_width = 0;
 137    wm.wm5.line_endcap_aa_region_width = 1;
 138
 139    /* BRW_NEW_RASTERIZER */
 140    if (brw->attribs.Raster->poly_stipple_enable)
 141       wm.wm5.polygon_stipple = 1;
 142
 143 #if 0
 144    if (brw->attribs.Polygon->OffsetFill) {
 145       wm.wm5.depth_offset = 1;
 146       /* Something wierd going on with legacy_global_depth_bias,
 147        * offset_constant, scaling and MRD.  This value passes glean
 148        * but gives some odd results elsewere (eg. the
 149        * quad-offset-units test).
 150        */
 151       wm.global_depth_offset_constant = brw->attribs.Polygon->OffsetUnits * 2;
 152
 153       /* This is the only value that passes glean:
 154        */
 155       wm.global_depth_offset_scale = brw->attribs.Polygon->OffsetFactor;
 156    }
 157 #endif
 158
 159    if (brw->attribs.Raster->line_stipple_enable) {
 160       wm.wm5.line_stipple = 1;
 161    }
 162
 163    if (BRW_DEBUG & DEBUG_STATS)
 164       wm.wm4.stats_enable = 1;
 165
 166    brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
 167
 168    if (brw->wm.prog_data->total_scratch) {
 169       /*
 170       dri_emit_reloc(brw->cache[BRW_WM_UNIT].pool->buffer,
 171                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
 172                      (per_thread / 1024) - 1,
 173                      brw->wm.state_gs_offset +
 174                      ((char *)&wm.thread2 - (char *)&wm),
 175                      brw->wm.scratch_buffer);
 176       */
 177    } else {
 178       wm.thread2.scratch_space_base_pointer = 0;
 179    }
 180 }
 181
 182 const struct brw_tracked_state brw_wm_unit = {
 183    .dirty = {
 184       .brw = (BRW_NEW_RASTERIZER |
 185               BRW_NEW_ALPHA_TEST |
 186               BRW_NEW_FS |
 187               BRW_NEW_CURBE_OFFSETS),
 188
 189       .cache = (CACHE_NEW_SURFACE |
 190                 CACHE_NEW_WM_PROG |
 191                 CACHE_NEW_SAMPLER)
 192    },
 193    .update = upload_wm_unit
 194 };
 195