src/gallium/drivers/ilo/core/ilo_dev.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "genhw/genhw.h"
  29 #include "intel_winsys.h"
  30
  31 #include "ilo_debug.h"
  32 #include "ilo_dev.h"
  33
  34 /**
  35  * Initialize the \p dev from \p winsys.  \p winsys is considered owned by \p
  36  * dev and will be destroyed in \p ilo_dev_cleanup().
  37  */
  38 bool
  39 ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys)
  40 {
  41    const struct intel_winsys_info *info;
  42
  43    assert(ilo_is_zeroed(dev, sizeof(*dev)));
  44
  45    info = intel_winsys_get_info(winsys);
  46
  47    dev->winsys = winsys;
  48    dev->devid = info->devid;
  49    dev->aperture_total = info->aperture_total;
  50    dev->aperture_mappable = info->aperture_mappable;
  51    dev->has_llc = info->has_llc;
  52    dev->has_address_swizzling = info->has_address_swizzling;
  53    dev->has_logical_context = info->has_logical_context;
  54    dev->has_ppgtt = info->has_ppgtt;
  55    dev->has_timestamp = info->has_timestamp;
  56    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
  57
  58    if (!dev->has_logical_context) {
  59       ilo_err("missing hardware logical context support\n");
  60       return false;
  61    }
  62
  63    /*
  64     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
  65     * writes on GEN6.
  66     *
  67     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
  68     *
  69     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
  70     *      code is in a secure environment, independent of address space.
  71     *      Under this condition, this bit only specifies the address space
  72     *      (GGTT or PPGTT). All commands are executed "as-is""
  73     *
  74     * We need PPGTT to be enabled on GEN6 too.
  75     */
  76    if (!dev->has_ppgtt) {
  77       /* experiments show that it does not really matter... */
  78       ilo_warn("PPGTT disabled\n");
  79    }
  80
  81    if (gen_is_bdw(info->devid) || gen_is_chv(info->devid)) {
  82       dev->gen_opaque = ILO_GEN(8);
  83       dev->gt = (gen_is_bdw(info->devid)) ? gen_get_bdw_gt(info->devid) : 1;
  84       /* XXX random values */
  85       if (dev->gt == 3) {
  86          dev->eu_count = 48;
  87          dev->thread_count = 336;
  88          dev->urb_size = 384 * 1024;
  89       } else if (dev->gt == 2) {
  90          dev->eu_count = 24;
  91          dev->thread_count = 168;
  92          dev->urb_size = 384 * 1024;
  93       } else {
  94          dev->eu_count = 12;
  95          dev->thread_count = 84;
  96          dev->urb_size = 192 * 1024;
  97       }
  98    } else if (gen_is_hsw(info->devid)) {
  99       /*
 100        * From the Haswell PRM, volume 4, page 8:
 101        *
 102        *     "Description                    GT3      GT2      GT1.5    GT1
 103        *      (...)
 104        *      EUs (Total)                    40       20       12       10
 105        *      Threads (Total)                280      140      84       70
 106        *      (...)
 107        *      URB Size (max, within L3$)     512KB    256KB    256KB    128KB
 108        */
 109       dev->gen_opaque = ILO_GEN(7.5);
 110       dev->gt = gen_get_hsw_gt(info->devid);
 111       if (dev->gt == 3) {
 112          dev->eu_count = 40;
 113          dev->thread_count = 280;
 114          dev->urb_size = 512 * 1024;
 115       } else if (dev->gt == 2) {
 116          dev->eu_count = 20;
 117          dev->thread_count = 140;
 118          dev->urb_size = 256 * 1024;
 119       } else {
 120          dev->eu_count = 10;
 121          dev->thread_count = 70;
 122          dev->urb_size = 128 * 1024;
 123       }
 124    } else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
 125       /*
 126        * From the Ivy Bridge PRM, volume 1 part 1, page 18:
 127        *
 128        *     "Device             # of EUs        #Threads/EU
 129        *      Ivy Bridge (GT2)   16              8
 130        *      Ivy Bridge (GT1)   6               6"
 131        *
 132        * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 133        *
 134        *     "URB Size    URB Rows    URB Rows when SLM Enabled
 135        *      128k        4096        2048
 136        *      256k        8096        4096"
 137        */
 138       dev->gen_opaque = ILO_GEN(7);
 139       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
 140       if (dev->gt == 2) {
 141          dev->eu_count = 16;
 142          dev->thread_count = 128;
 143          dev->urb_size = 256 * 1024;
 144       } else {
 145          dev->eu_count = 6;
 146          dev->thread_count = 36;
 147          dev->urb_size = 128 * 1024;
 148       }
 149    } else if (gen_is_snb(info->devid)) {
 150       /*
 151        * From the Sandy Bridge PRM, volume 1 part 1, page 22:
 152        *
 153        *     "Device             # of EUs        #Threads/EU
 154        *      SNB GT2            12              5
 155        *      SNB GT1            6               4"
 156        *
 157        * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 158        *
 159        *     "[DevSNB]: The GT1 product's URB provides 32KB of storage,
 160        *      arranged as 1024 256-bit rows. The GT2 product's URB provides
 161        *      64KB of storage, arranged as 2048 256-bit rows. A row
 162        *      corresponds in size to an EU GRF register. Read/write access to
 163        *      the URB is generally supported on a row-granular basis."
 164        */
 165       dev->gen_opaque = ILO_GEN(6);
 166       dev->gt = gen_get_snb_gt(info->devid);
 167       if (dev->gt == 2) {
 168          dev->eu_count = 12;
 169          dev->thread_count = 60;
 170          dev->urb_size = 64 * 1024;
 171       } else {
 172          dev->eu_count = 6;
 173          dev->thread_count = 24;
 174          dev->urb_size = 32 * 1024;
 175       }
 176    } else {
 177       ilo_err("unknown GPU generation\n");
 178       return false;
 179    }
 180
 181    return true;
 182 }
 183
 184 void
 185 ilo_dev_cleanup(struct ilo_dev *dev)
 186 {
 187    intel_winsys_destroy(dev->winsys);
 188 }