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31d9a203c5a25902bddfcc2e12669029d3171a6e
[mesa.git] / src / gallium / drivers / ilo / core / ilo_state_3d_bottom.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2012-2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_half.h"
32
33 #include "ilo_format.h"
34 #include "ilo_image.h"
35 #include "ilo_state_3d.h"
36 #include "../ilo_shader.h"
37
38 static void
39 rasterizer_init_clip(const struct ilo_dev *dev,
40 const struct pipe_rasterizer_state *state,
41 struct ilo_rasterizer_clip *clip)
42 {
43 uint32_t dw1, dw2, dw3;
44
45 ILO_DEV_ASSERT(dev, 6, 8);
46
47 dw1 = GEN6_CLIP_DW1_STATISTICS;
48
49 if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
50 /*
51 * From the Ivy Bridge PRM, volume 2 part 1, page 219:
52 *
53 * "Workaround : Due to Hardware issue "EarlyCull" needs to be
54 * enabled only for the cases where the incoming primitive topology
55 * into the clipper guaranteed to be Trilist."
56 *
57 * What does this mean?
58 */
59 dw1 |= 0 << 19 |
60 GEN7_CLIP_DW1_EARLY_CULL_ENABLE;
61
62 if (ilo_dev_gen(dev) < ILO_GEN(8)) {
63 if (state->front_ccw)
64 dw1 |= GEN6_FRONTWINDING_CCW << 20;
65
66 switch (state->cull_face) {
67 case PIPE_FACE_NONE:
68 dw1 |= GEN6_CULLMODE_NONE << 16;
69 break;
70 case PIPE_FACE_FRONT:
71 dw1 |= GEN6_CULLMODE_FRONT << 16;
72 break;
73 case PIPE_FACE_BACK:
74 dw1 |= GEN6_CULLMODE_BACK << 16;
75 break;
76 case PIPE_FACE_FRONT_AND_BACK:
77 dw1 |= GEN6_CULLMODE_BOTH << 16;
78 break;
79 }
80 }
81 }
82
83 dw2 = GEN6_CLIP_DW2_CLIP_ENABLE |
84 GEN6_CLIP_DW2_XY_TEST_ENABLE |
85 state->clip_plane_enable << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
86 GEN6_CLIPMODE_NORMAL << 13;
87
88 if (state->clip_halfz)
89 dw2 |= GEN6_CLIP_DW2_APIMODE_D3D;
90 else
91 dw2 |= GEN6_CLIP_DW2_APIMODE_OGL;
92
93 if (ilo_dev_gen(dev) < ILO_GEN(8) && state->depth_clip)
94 dw2 |= GEN6_CLIP_DW2_Z_TEST_ENABLE;
95
96 if (state->flatshade_first) {
97 dw2 |= 0 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
98 0 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
99 1 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
100 }
101 else {
102 dw2 |= 2 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
103 1 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
104 2 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
105 }
106
107 dw3 = 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT |
108 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT;
109
110 clip->payload[0] = dw1;
111 clip->payload[1] = dw2;
112 clip->payload[2] = dw3;
113
114 clip->can_enable_guardband = true;
115
116 /*
117 * There are several reasons that guard band test should be disabled
118 *
119 * - GL wide points (to avoid partially visibie object)
120 * - GL wide or AA lines (to avoid partially visibie object)
121 */
122 if (state->point_size_per_vertex || state->point_size > 1.0f)
123 clip->can_enable_guardband = false;
124 if (state->line_smooth || state->line_width > 1.0f)
125 clip->can_enable_guardband = false;
126 }
127
128 static void
129 rasterizer_init_sf_depth_offset_gen6(const struct ilo_dev *dev,
130 const struct pipe_rasterizer_state *state,
131 struct ilo_rasterizer_sf *sf)
132 {
133 ILO_DEV_ASSERT(dev, 6, 8);
134
135 /*
136 * Scale the constant term. The minimum representable value used by the HW
137 * is not large enouch to be the minimum resolvable difference.
138 */
139 sf->dw_depth_offset_const = fui(state->offset_units * 2.0f);
140 sf->dw_depth_offset_scale = fui(state->offset_scale);
141 sf->dw_depth_offset_clamp = fui(state->offset_clamp);
142 }
143
144 static void
145 rasterizer_init_sf_gen6(const struct ilo_dev *dev,
146 const struct pipe_rasterizer_state *state,
147 struct ilo_rasterizer_sf *sf)
148 {
149 int line_width, point_width;
150 uint32_t dw1, dw2, dw3;
151
152 ILO_DEV_ASSERT(dev, 6, 7.5);
153
154 /*
155 * From the Sandy Bridge PRM, volume 2 part 1, page 248:
156 *
157 * "This bit (Statistics Enable) should be set whenever clipping is
158 * enabled and the Statistics Enable bit is set in CLIP_STATE. It
159 * should be cleared if clipping is disabled or Statistics Enable in
160 * CLIP_STATE is clear."
161 */
162 dw1 = GEN7_SF_DW1_STATISTICS |
163 GEN7_SF_DW1_VIEWPORT_TRANSFORM;
164
165 /* XXX GEN6 path seems to work fine for GEN7 */
166 if (false && ilo_dev_gen(dev) >= ILO_GEN(7)) {
167 /*
168 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
169 *
170 * "This bit (Legacy Global Depth Bias Enable, Global Depth Offset
171 * Enable Solid , Global Depth Offset Enable Wireframe, and Global
172 * Depth Offset Enable Point) should be set whenever non zero depth
173 * bias (Slope, Bias) values are used. Setting this bit may have
174 * some degradation of performance for some workloads."
175 */
176 if (state->offset_tri || state->offset_line || state->offset_point) {
177 /* XXX need to scale offset_const according to the depth format */
178 dw1 |= GEN7_SF_DW1_LEGACY_DEPTH_OFFSET;
179
180 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID |
181 GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME |
182 GEN7_SF_DW1_DEPTH_OFFSET_POINT;
183 }
184 } else {
185 if (state->offset_tri)
186 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID;
187 if (state->offset_line)
188 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME;
189 if (state->offset_point)
190 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_POINT;
191 }
192
193 switch (state->fill_front) {
194 case PIPE_POLYGON_MODE_FILL:
195 dw1 |= GEN6_FILLMODE_SOLID << 5;
196 break;
197 case PIPE_POLYGON_MODE_LINE:
198 dw1 |= GEN6_FILLMODE_WIREFRAME << 5;
199 break;
200 case PIPE_POLYGON_MODE_POINT:
201 dw1 |= GEN6_FILLMODE_POINT << 5;
202 break;
203 }
204
205 switch (state->fill_back) {
206 case PIPE_POLYGON_MODE_FILL:
207 dw1 |= GEN6_FILLMODE_SOLID << 3;
208 break;
209 case PIPE_POLYGON_MODE_LINE:
210 dw1 |= GEN6_FILLMODE_WIREFRAME << 3;
211 break;
212 case PIPE_POLYGON_MODE_POINT:
213 dw1 |= GEN6_FILLMODE_POINT << 3;
214 break;
215 }
216
217 if (state->front_ccw)
218 dw1 |= GEN6_FRONTWINDING_CCW;
219
220 dw2 = 0;
221
222 if (state->line_smooth) {
223 /*
224 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
225 *
226 * "This field (Anti-aliasing Enable) must be disabled if any of the
227 * render targets have integer (UINT or SINT) surface format."
228 *
229 * From the Sandy Bridge PRM, volume 2 part 1, page 317:
230 *
231 * "This field (Hierarchical Depth Buffer Enable) must be disabled
232 * if Anti-aliasing Enable in 3DSTATE_SF is enabled.
233 *
234 * TODO We do not check those yet.
235 */
236 dw2 |= GEN7_SF_DW2_AA_LINE_ENABLE |
237 GEN7_SF_DW2_AA_LINE_CAP_1_0;
238 }
239
240 switch (state->cull_face) {
241 case PIPE_FACE_NONE:
242 dw2 |= GEN6_CULLMODE_NONE << 29;
243 break;
244 case PIPE_FACE_FRONT:
245 dw2 |= GEN6_CULLMODE_FRONT << 29;
246 break;
247 case PIPE_FACE_BACK:
248 dw2 |= GEN6_CULLMODE_BACK << 29;
249 break;
250 case PIPE_FACE_FRONT_AND_BACK:
251 dw2 |= GEN6_CULLMODE_BOTH << 29;
252 break;
253 }
254
255 /*
256 * Smooth lines should intersect ceil(line_width) or (ceil(line_width) + 1)
257 * pixels in the minor direction. We have to make the lines slightly
258 * thicker, 0.5 pixel on both sides, so that they intersect that many
259 * pixels are considered into the lines.
260 *
261 * Line width is in U3.7.
262 */
263 line_width = (int)
264 ((state->line_width + (float) state->line_smooth) * 128.0f + 0.5f);
265 line_width = CLAMP(line_width, 0, 1023);
266
267 /* use GIQ rules */
268 if (line_width == 128 && !state->line_smooth)
269 line_width = 0;
270
271 dw2 |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
272
273 if (ilo_dev_gen(dev) == ILO_GEN(7.5) && state->line_stipple_enable)
274 dw2 |= GEN75_SF_DW2_LINE_STIPPLE_ENABLE;
275
276 if (state->scissor)
277 dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
278
279 dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
280 GEN7_SF_DW3_SUBPIXEL_8BITS;
281
282 if (state->line_last_pixel)
283 dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
284
285 if (state->flatshade_first) {
286 dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
287 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
288 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
289 } else {
290 dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
291 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
292 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
293 }
294
295 if (!state->point_size_per_vertex)
296 dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH;
297
298 /* in U8.3 */
299 point_width = (int) (state->point_size * 8.0f + 0.5f);
300 point_width = CLAMP(point_width, 1, 2047);
301
302 dw3 |= point_width;
303
304 STATIC_ASSERT(Elements(sf->payload) >= 3);
305 sf->payload[0] = dw1;
306 sf->payload[1] = dw2;
307 sf->payload[2] = dw3;
308
309 if (state->multisample) {
310 sf->dw_msaa = GEN6_MSRASTMODE_ON_PATTERN << 8;
311
312 /*
313 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
314 *
315 * "Software must not program a value of 0.0 when running in
316 * MSRASTMODE_ON_xxx modes - zero-width lines are not available
317 * when multisampling rasterization is enabled."
318 */
319 if (!line_width) {
320 line_width = 128; /* 1.0f */
321
322 sf->dw_msaa |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
323 }
324 } else {
325 sf->dw_msaa = 0;
326 }
327
328 rasterizer_init_sf_depth_offset_gen6(dev, state, sf);
329 /* 3DSTATE_RASTER is Gen8+ only */
330 sf->dw_raster = 0;
331 }
332
333 static uint32_t
334 rasterizer_get_sf_raster_gen8(const struct ilo_dev *dev,
335 const struct pipe_rasterizer_state *state)
336 {
337 uint32_t dw = 0;
338
339 ILO_DEV_ASSERT(dev, 8, 8);
340
341 if (state->front_ccw)
342 dw |= GEN6_FRONTWINDING_CCW << 21;
343
344 switch (state->cull_face) {
345 case PIPE_FACE_NONE:
346 dw |= GEN6_CULLMODE_NONE << 16;
347 break;
348 case PIPE_FACE_FRONT:
349 dw |= GEN6_CULLMODE_FRONT << 16;
350 break;
351 case PIPE_FACE_BACK:
352 dw |= GEN6_CULLMODE_BACK << 16;
353 break;
354 case PIPE_FACE_FRONT_AND_BACK:
355 dw |= GEN6_CULLMODE_BOTH << 16;
356 break;
357 }
358
359 if (state->point_smooth)
360 dw |= GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE;
361
362 if (state->multisample)
363 dw |= GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE;
364
365 if (state->offset_tri)
366 dw|= GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID;
367 if (state->offset_line)
368 dw|= GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME;
369 if (state->offset_point)
370 dw|= GEN8_RASTER_DW1_DEPTH_OFFSET_POINT;
371
372 switch (state->fill_front) {
373 case PIPE_POLYGON_MODE_FILL:
374 dw |= GEN6_FILLMODE_SOLID << 5;
375 break;
376 case PIPE_POLYGON_MODE_LINE:
377 dw |= GEN6_FILLMODE_WIREFRAME << 5;
378 break;
379 case PIPE_POLYGON_MODE_POINT:
380 dw |= GEN6_FILLMODE_POINT << 5;
381 break;
382 }
383
384 switch (state->fill_back) {
385 case PIPE_POLYGON_MODE_FILL:
386 dw |= GEN6_FILLMODE_SOLID << 3;
387 break;
388 case PIPE_POLYGON_MODE_LINE:
389 dw |= GEN6_FILLMODE_WIREFRAME << 3;
390 break;
391 case PIPE_POLYGON_MODE_POINT:
392 dw |= GEN6_FILLMODE_POINT << 3;
393 break;
394 }
395
396 if (state->line_smooth)
397 dw |= GEN8_RASTER_DW1_AA_LINE_ENABLE;
398
399 if (state->scissor)
400 dw |= GEN8_RASTER_DW1_SCISSOR_ENABLE;
401
402 if (state->depth_clip)
403 dw |= GEN8_RASTER_DW1_Z_TEST_ENABLE;
404
405 return dw;
406 }
407
408 static void
409 rasterizer_init_sf_gen8(const struct ilo_dev *dev,
410 const struct pipe_rasterizer_state *state,
411 struct ilo_rasterizer_sf *sf)
412 {
413 int line_width, point_width;
414 uint32_t dw1, dw2, dw3;
415
416 ILO_DEV_ASSERT(dev, 8, 8);
417
418 /* in U3.7 */
419 line_width = (int)
420 ((state->line_width + (float) state->line_smooth) * 128.0f + 0.5f);
421 line_width = CLAMP(line_width, 0, 1023);
422
423 /* use GIQ rules */
424 if (line_width == 128 && !state->line_smooth)
425 line_width = 0;
426
427 /* in U8.3 */
428 point_width = (int) (state->point_size * 8.0f + 0.5f);
429 point_width = CLAMP(point_width, 1, 2047);
430
431 dw1 = GEN7_SF_DW1_STATISTICS |
432 GEN7_SF_DW1_VIEWPORT_TRANSFORM;
433
434 dw2 = line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
435 if (state->line_smooth)
436 dw2 |= GEN7_SF_DW2_AA_LINE_CAP_1_0;
437
438 dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
439 GEN7_SF_DW3_SUBPIXEL_8BITS |
440 point_width;
441
442 if (state->line_last_pixel)
443 dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
444
445 if (state->flatshade_first) {
446 dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
447 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
448 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
449 } else {
450 dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
451 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
452 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
453 }
454
455 if (!state->point_size_per_vertex)
456 dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH;
457
458 dw3 |= point_width;
459
460 STATIC_ASSERT(Elements(sf->payload) >= 3);
461 sf->payload[0] = dw1;
462 sf->payload[1] = dw2;
463 sf->payload[2] = dw3;
464
465 rasterizer_init_sf_depth_offset_gen6(dev, state, sf);
466
467 sf->dw_msaa = 0;
468 sf->dw_raster = rasterizer_get_sf_raster_gen8(dev, state);
469 }
470
471 static void
472 rasterizer_init_wm_gen6(const struct ilo_dev *dev,
473 const struct pipe_rasterizer_state *state,
474 struct ilo_rasterizer_wm *wm)
475 {
476 uint32_t dw5, dw6;
477
478 ILO_DEV_ASSERT(dev, 6, 6);
479
480 /* only the FF unit states are set, as in GEN7 */
481
482 dw5 = GEN6_WM_DW5_AA_LINE_WIDTH_2_0;
483
484 /* same value as in 3DSTATE_SF */
485 if (state->line_smooth)
486 dw5 |= GEN6_WM_DW5_AA_LINE_CAP_1_0;
487
488 if (state->poly_stipple_enable)
489 dw5 |= GEN6_WM_DW5_POLY_STIPPLE_ENABLE;
490 if (state->line_stipple_enable)
491 dw5 |= GEN6_WM_DW5_LINE_STIPPLE_ENABLE;
492
493 /*
494 * assertion that makes sure
495 *
496 * dw6 |= wm->dw_msaa_rast | wm->dw_msaa_disp;
497 *
498 * is valid
499 */
500 STATIC_ASSERT(GEN6_MSRASTMODE_OFF_PIXEL == 0 &&
501 GEN6_WM_DW6_MSDISPMODE_PERSAMPLE == 0);
502 dw6 = GEN6_ZW_INTERP_PIXEL << GEN6_WM_DW6_ZW_INTERP__SHIFT;
503
504 if (state->bottom_edge_rule)
505 dw6 |= GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT;
506
507 wm->dw_msaa_rast =
508 (state->multisample) ? (GEN6_MSRASTMODE_ON_PATTERN << 1) : 0;
509 wm->dw_msaa_disp = GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
510
511 STATIC_ASSERT(Elements(wm->payload) >= 2);
512 wm->payload[0] = dw5;
513 wm->payload[1] = dw6;
514 }
515
516 static void
517 rasterizer_init_wm_gen7(const struct ilo_dev *dev,
518 const struct pipe_rasterizer_state *state,
519 struct ilo_rasterizer_wm *wm)
520 {
521 uint32_t dw1, dw2;
522
523 ILO_DEV_ASSERT(dev, 7, 7.5);
524
525 /*
526 * assertion that makes sure
527 *
528 * dw1 |= wm->dw_msaa_rast;
529 * dw2 |= wm->dw_msaa_disp;
530 *
531 * is valid
532 */
533 STATIC_ASSERT(GEN6_MSRASTMODE_OFF_PIXEL == 0 &&
534 GEN7_WM_DW2_MSDISPMODE_PERSAMPLE == 0);
535 dw1 = GEN6_ZW_INTERP_PIXEL << GEN7_WM_DW1_ZW_INTERP__SHIFT |
536 GEN7_WM_DW1_AA_LINE_WIDTH_2_0;
537 dw2 = 0;
538
539 /* same value as in 3DSTATE_SF */
540 if (state->line_smooth)
541 dw1 |= GEN7_WM_DW1_AA_LINE_CAP_1_0;
542
543 if (state->poly_stipple_enable)
544 dw1 |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
545 if (state->line_stipple_enable)
546 dw1 |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
547
548 if (state->bottom_edge_rule)
549 dw1 |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
550
551 wm->dw_msaa_rast =
552 (state->multisample) ? GEN6_MSRASTMODE_ON_PATTERN : 0;
553 wm->dw_msaa_disp = GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
554
555 STATIC_ASSERT(Elements(wm->payload) >= 2);
556 wm->payload[0] = dw1;
557 wm->payload[1] = dw2;
558 }
559
560 static uint32_t
561 rasterizer_get_wm_gen8(const struct ilo_dev *dev,
562 const struct pipe_rasterizer_state *state)
563 {
564 uint32_t dw;
565
566 ILO_DEV_ASSERT(dev, 8, 8);
567
568 dw = GEN6_ZW_INTERP_PIXEL << GEN7_WM_DW1_ZW_INTERP__SHIFT |
569 GEN7_WM_DW1_AA_LINE_WIDTH_2_0;
570
571 /* same value as in 3DSTATE_SF */
572 if (state->line_smooth)
573 dw |= GEN7_WM_DW1_AA_LINE_CAP_1_0;
574
575 if (state->poly_stipple_enable)
576 dw |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
577 if (state->line_stipple_enable)
578 dw |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
579
580 if (state->bottom_edge_rule)
581 dw |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
582
583 return dw;
584 }
585
586 void
587 ilo_gpe_init_rasterizer(const struct ilo_dev *dev,
588 const struct pipe_rasterizer_state *state,
589 struct ilo_rasterizer_state *rasterizer)
590 {
591 rasterizer_init_clip(dev, state, &rasterizer->clip);
592
593 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
594 memset(&rasterizer->wm, 0, sizeof(rasterizer->wm));
595 rasterizer->wm.payload[0] = rasterizer_get_wm_gen8(dev, state);
596
597 rasterizer_init_sf_gen8(dev, state, &rasterizer->sf);
598 } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
599 rasterizer_init_wm_gen7(dev, state, &rasterizer->wm);
600 rasterizer_init_sf_gen6(dev, state, &rasterizer->sf);
601 } else {
602 rasterizer_init_wm_gen6(dev, state, &rasterizer->wm);
603 rasterizer_init_sf_gen6(dev, state, &rasterizer->sf);
604 }
605 }
606
607 static void
608 fs_init_cso_gen6(const struct ilo_dev *dev,
609 const struct ilo_shader_state *fs,
610 struct ilo_shader_cso *cso)
611 {
612 int start_grf, input_count, sampler_count, interps, max_threads;
613 uint32_t dw2, dw4, dw5, dw6;
614
615 ILO_DEV_ASSERT(dev, 6, 6);
616
617 start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
618 input_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT);
619 sampler_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_SAMPLER_COUNT);
620 interps = ilo_shader_get_kernel_param(fs,
621 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS);
622
623 /* see brwCreateContext() */
624 max_threads = (dev->gt == 2) ? 80 : 40;
625
626 dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
627 dw2 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
628
629 dw4 = start_grf << GEN6_WM_DW4_URB_GRF_START0__SHIFT |
630 0 << GEN6_WM_DW4_URB_GRF_START1__SHIFT |
631 0 << GEN6_WM_DW4_URB_GRF_START2__SHIFT;
632
633 dw5 = (max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT;
634
635 /*
636 * From the Sandy Bridge PRM, volume 2 part 1, page 275:
637 *
638 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that the
639 * PS kernel or color calculator has the ability to kill (discard)
640 * pixels or samples, other than due to depth or stencil testing.
641 * This bit is required to be ENABLED in the following situations:
642 *
643 * The API pixel shader program contains "killpix" or "discard"
644 * instructions, or other code in the pixel shader kernel that can
645 * cause the final pixel mask to differ from the pixel mask received
646 * on dispatch.
647 *
648 * A sampler with chroma key enabled with kill pixel mode is used by
649 * the pixel shader.
650 *
651 * Any render target has Alpha Test Enable or AlphaToCoverage Enable
652 * enabled.
653 *
654 * The pixel shader kernel generates and outputs oMask.
655 *
656 * Note: As ClipDistance clipping is fully supported in hardware and
657 * therefore not via PS instructions, there should be no need to
658 * ENABLE this bit due to ClipDistance clipping."
659 */
660 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
661 dw5 |= GEN6_WM_DW5_PS_KILL_PIXEL;
662
663 /*
664 * From the Sandy Bridge PRM, volume 2 part 1, page 275:
665 *
666 * "If a NULL Depth Buffer is selected, the Pixel Shader Computed Depth
667 * field must be set to disabled."
668 *
669 * TODO This is not checked yet.
670 */
671 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
672 dw5 |= GEN6_WM_DW5_PS_COMPUTE_DEPTH;
673
674 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
675 dw5 |= GEN6_WM_DW5_PS_USE_DEPTH;
676
677 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
678 dw5 |= GEN6_WM_DW5_PS_USE_W;
679
680 /*
681 * TODO set this bit only when
682 *
683 * a) fs writes colors and color is not masked, or
684 * b) fs writes depth, or
685 * c) fs or cc kills
686 */
687 if (true)
688 dw5 |= GEN6_WM_DW5_PS_DISPATCH_ENABLE;
689
690 assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
691 dw5 |= GEN6_PS_DISPATCH_8 << GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT;
692
693 dw6 = input_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
694 GEN6_POSOFFSET_NONE << GEN6_WM_DW6_PS_POSOFFSET__SHIFT |
695 interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT;
696
697 STATIC_ASSERT(Elements(cso->payload) >= 4);
698 cso->payload[0] = dw2;
699 cso->payload[1] = dw4;
700 cso->payload[2] = dw5;
701 cso->payload[3] = dw6;
702 }
703
704 static uint32_t
705 fs_get_wm_gen7(const struct ilo_dev *dev,
706 const struct ilo_shader_state *fs)
707 {
708 uint32_t dw;
709
710 ILO_DEV_ASSERT(dev, 7, 7.5);
711
712 dw = ilo_shader_get_kernel_param(fs,
713 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) <<
714 GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT;
715
716 /*
717 * TODO set this bit only when
718 *
719 * a) fs writes colors and color is not masked, or
720 * b) fs writes depth, or
721 * c) fs or cc kills
722 */
723 dw |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
724
725 /*
726 * From the Ivy Bridge PRM, volume 2 part 1, page 278:
727 *
728 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that
729 * the PS kernel or color calculator has the ability to kill
730 * (discard) pixels or samples, other than due to depth or stencil
731 * testing. This bit is required to be ENABLED in the following
732 * situations:
733 *
734 * - The API pixel shader program contains "killpix" or "discard"
735 * instructions, or other code in the pixel shader kernel that
736 * can cause the final pixel mask to differ from the pixel mask
737 * received on dispatch.
738 *
739 * - A sampler with chroma key enabled with kill pixel mode is used
740 * by the pixel shader.
741 *
742 * - Any render target has Alpha Test Enable or AlphaToCoverage
743 * Enable enabled.
744 *
745 * - The pixel shader kernel generates and outputs oMask.
746 *
747 * Note: As ClipDistance clipping is fully supported in hardware
748 * and therefore not via PS instructions, there should be no need
749 * to ENABLE this bit due to ClipDistance clipping."
750 */
751 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
752 dw |= GEN7_WM_DW1_PS_KILL_PIXEL;
753
754 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
755 dw |= GEN7_PSCDEPTH_ON << GEN7_WM_DW1_PSCDEPTH__SHIFT;
756
757 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
758 dw |= GEN7_WM_DW1_PS_USE_DEPTH;
759
760 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
761 dw |= GEN7_WM_DW1_PS_USE_W;
762
763 return dw;
764 }
765
766 static void
767 fs_init_cso_gen7(const struct ilo_dev *dev,
768 const struct ilo_shader_state *fs,
769 struct ilo_shader_cso *cso)
770 {
771 int start_grf, sampler_count, max_threads;
772 uint32_t dw2, dw4, dw5;
773
774 ILO_DEV_ASSERT(dev, 7, 7.5);
775
776 start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
777 sampler_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_SAMPLER_COUNT);
778
779 dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
780 dw2 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
781
782 dw4 = GEN6_POSOFFSET_NONE << GEN7_PS_DW4_POSOFFSET__SHIFT;
783
784 /* see brwCreateContext() */
785 switch (ilo_dev_gen(dev)) {
786 case ILO_GEN(7.5):
787 max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
788 dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
789 dw4 |= 1 << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
790 break;
791 case ILO_GEN(7):
792 default:
793 max_threads = (dev->gt == 2) ? 172 : 48;
794 dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
795 break;
796 }
797
798 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE))
799 dw4 |= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE;
800
801 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT))
802 dw4 |= GEN7_PS_DW4_ATTR_ENABLE;
803
804 assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
805 dw4 |= GEN6_PS_DISPATCH_8 << GEN7_PS_DW4_DISPATCH_MODE__SHIFT;
806
807 dw5 = start_grf << GEN7_PS_DW5_URB_GRF_START0__SHIFT |
808 0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT |
809 0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT;
810
811 STATIC_ASSERT(Elements(cso->payload) >= 4);
812 cso->payload[0] = dw2;
813 cso->payload[1] = dw4;
814 cso->payload[2] = dw5;
815 cso->payload[3] = fs_get_wm_gen7(dev, fs);
816 }
817
818 static uint32_t
819 fs_get_psx_gen8(const struct ilo_dev *dev,
820 const struct ilo_shader_state *fs)
821 {
822 uint32_t dw;
823
824 ILO_DEV_ASSERT(dev, 8, 8);
825
826 dw = GEN8_PSX_DW1_VALID;
827
828 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
829 dw |= GEN8_PSX_DW1_KILL_PIXEL;
830 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
831 dw |= GEN7_PSCDEPTH_ON << GEN8_PSX_DW1_PSCDEPTH__SHIFT;
832 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
833 dw |= GEN8_PSX_DW1_USE_DEPTH;
834 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
835 dw |= GEN8_PSX_DW1_USE_W;
836 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT))
837 dw |= GEN8_PSX_DW1_ATTR_ENABLE;
838
839 return dw;
840 }
841
842 static uint32_t
843 fs_get_wm_gen8(const struct ilo_dev *dev,
844 const struct ilo_shader_state *fs)
845 {
846 ILO_DEV_ASSERT(dev, 8, 8);
847
848 return ilo_shader_get_kernel_param(fs,
849 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) <<
850 GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT;
851 }
852
853 static void
854 fs_init_cso_gen8(const struct ilo_dev *dev,
855 const struct ilo_shader_state *fs,
856 struct ilo_shader_cso *cso)
857 {
858 int start_grf, sampler_count;
859 uint32_t dw3, dw6, dw7;
860
861 ILO_DEV_ASSERT(dev, 8, 8);
862
863 start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
864 sampler_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_SAMPLER_COUNT);
865
866 dw3 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
867 dw3 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
868
869 /* always 64? */
870 dw6 = (64 - 2) << GEN8_PS_DW6_MAX_THREADS__SHIFT |
871 GEN6_POSOFFSET_NONE << GEN8_PS_DW6_POSOFFSET__SHIFT;
872 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE))
873 dw6 |= GEN8_PS_DW6_PUSH_CONSTANT_ENABLE;
874
875 assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
876 dw6 |= GEN6_PS_DISPATCH_8 << GEN8_PS_DW6_DISPATCH_MODE__SHIFT;
877
878 dw7 = start_grf << GEN8_PS_DW7_URB_GRF_START0__SHIFT |
879 0 << GEN8_PS_DW7_URB_GRF_START1__SHIFT |
880 0 << GEN8_PS_DW7_URB_GRF_START2__SHIFT;
881
882 STATIC_ASSERT(Elements(cso->payload) >= 5);
883 cso->payload[0] = dw3;
884 cso->payload[1] = dw6;
885 cso->payload[2] = dw7;
886 cso->payload[3] = fs_get_psx_gen8(dev, fs);
887 cso->payload[4] = fs_get_wm_gen8(dev, fs);
888 }
889
890 void
891 ilo_gpe_init_fs_cso(const struct ilo_dev *dev,
892 const struct ilo_shader_state *fs,
893 struct ilo_shader_cso *cso)
894 {
895 if (ilo_dev_gen(dev) >= ILO_GEN(8))
896 fs_init_cso_gen8(dev, fs, cso);
897 else if (ilo_dev_gen(dev) >= ILO_GEN(7))
898 fs_init_cso_gen7(dev, fs, cso);
899 else
900 fs_init_cso_gen6(dev, fs, cso);
901 }
902
903 static void
904 viewport_get_guardband(const struct ilo_dev *dev,
905 int center_x, int center_y,
906 int *min_gbx, int *max_gbx,
907 int *min_gby, int *max_gby)
908 {
909 /*
910 * From the Sandy Bridge PRM, volume 2 part 1, page 234:
911 *
912 * "Per-Device Guardband Extents
913 *
914 * - Supported X,Y ScreenSpace "Guardband" Extent: [-16K,16K-1]
915 * - Maximum Post-Clamp Delta (X or Y): 16K"
916 *
917 * "In addition, in order to be correctly rendered, objects must have a
918 * screenspace bounding box not exceeding 8K in the X or Y direction.
919 * This additional restriction must also be comprehended by software,
920 * i.e., enforced by use of clipping."
921 *
922 * From the Ivy Bridge PRM, volume 2 part 1, page 248:
923 *
924 * "Per-Device Guardband Extents
925 *
926 * - Supported X,Y ScreenSpace "Guardband" Extent: [-32K,32K-1]
927 * - Maximum Post-Clamp Delta (X or Y): N/A"
928 *
929 * "In addition, in order to be correctly rendered, objects must have a
930 * screenspace bounding box not exceeding 8K in the X or Y direction.
931 * This additional restriction must also be comprehended by software,
932 * i.e., enforced by use of clipping."
933 *
934 * Combined, the bounding box of any object can not exceed 8K in both
935 * width and height.
936 *
937 * Below we set the guardband as a squre of length 8K, centered at where
938 * the viewport is. This makes sure all objects passing the GB test are
939 * valid to the renderer, and those failing the XY clipping have a
940 * better chance of passing the GB test.
941 */
942 const int max_extent = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 32768 : 16384;
943 const int half_len = 8192 / 2;
944
945 /* make sure the guardband is within the valid range */
946 if (center_x - half_len < -max_extent)
947 center_x = -max_extent + half_len;
948 else if (center_x + half_len > max_extent - 1)
949 center_x = max_extent - half_len;
950
951 if (center_y - half_len < -max_extent)
952 center_y = -max_extent + half_len;
953 else if (center_y + half_len > max_extent - 1)
954 center_y = max_extent - half_len;
955
956 *min_gbx = (float) (center_x - half_len);
957 *max_gbx = (float) (center_x + half_len);
958 *min_gby = (float) (center_y - half_len);
959 *max_gby = (float) (center_y + half_len);
960 }
961
962 void
963 ilo_gpe_set_viewport_cso(const struct ilo_dev *dev,
964 const struct pipe_viewport_state *state,
965 struct ilo_viewport_cso *vp)
966 {
967 const float scale_x = fabs(state->scale[0]);
968 const float scale_y = fabs(state->scale[1]);
969 const float scale_z = fabs(state->scale[2]);
970 int min_gbx, max_gbx, min_gby, max_gby;
971
972 ILO_DEV_ASSERT(dev, 6, 8);
973
974 viewport_get_guardband(dev,
975 (int) state->translate[0],
976 (int) state->translate[1],
977 &min_gbx, &max_gbx, &min_gby, &max_gby);
978
979 /* matrix form */
980 vp->m00 = state->scale[0];
981 vp->m11 = state->scale[1];
982 vp->m22 = state->scale[2];
983 vp->m30 = state->translate[0];
984 vp->m31 = state->translate[1];
985 vp->m32 = state->translate[2];
986
987 /* guardband in NDC space */
988 vp->min_gbx = ((float) min_gbx - state->translate[0]) / scale_x;
989 vp->max_gbx = ((float) max_gbx - state->translate[0]) / scale_x;
990 vp->min_gby = ((float) min_gby - state->translate[1]) / scale_y;
991 vp->max_gby = ((float) max_gby - state->translate[1]) / scale_y;
992
993 /* viewport in screen space */
994 vp->min_x = scale_x * -1.0f + state->translate[0];
995 vp->max_x = scale_x * 1.0f + state->translate[0];
996 vp->min_y = scale_y * -1.0f + state->translate[1];
997 vp->max_y = scale_y * 1.0f + state->translate[1];
998 vp->min_z = scale_z * -1.0f + state->translate[2];
999 vp->max_z = scale_z * 1.0f + state->translate[2];
1000 }
1001
1002 /**
1003 * Translate a pipe logicop to the matching hardware logicop.
1004 */
1005 static int
1006 gen6_translate_pipe_logicop(unsigned logicop)
1007 {
1008 switch (logicop) {
1009 case PIPE_LOGICOP_CLEAR: return GEN6_LOGICOP_CLEAR;
1010 case PIPE_LOGICOP_NOR: return GEN6_LOGICOP_NOR;
1011 case PIPE_LOGICOP_AND_INVERTED: return GEN6_LOGICOP_AND_INVERTED;
1012 case PIPE_LOGICOP_COPY_INVERTED: return GEN6_LOGICOP_COPY_INVERTED;
1013 case PIPE_LOGICOP_AND_REVERSE: return GEN6_LOGICOP_AND_REVERSE;
1014 case PIPE_LOGICOP_INVERT: return GEN6_LOGICOP_INVERT;
1015 case PIPE_LOGICOP_XOR: return GEN6_LOGICOP_XOR;
1016 case PIPE_LOGICOP_NAND: return GEN6_LOGICOP_NAND;
1017 case PIPE_LOGICOP_AND: return GEN6_LOGICOP_AND;
1018 case PIPE_LOGICOP_EQUIV: return GEN6_LOGICOP_EQUIV;
1019 case PIPE_LOGICOP_NOOP: return GEN6_LOGICOP_NOOP;
1020 case PIPE_LOGICOP_OR_INVERTED: return GEN6_LOGICOP_OR_INVERTED;
1021 case PIPE_LOGICOP_COPY: return GEN6_LOGICOP_COPY;
1022 case PIPE_LOGICOP_OR_REVERSE: return GEN6_LOGICOP_OR_REVERSE;
1023 case PIPE_LOGICOP_OR: return GEN6_LOGICOP_OR;
1024 case PIPE_LOGICOP_SET: return GEN6_LOGICOP_SET;
1025 default:
1026 assert(!"unknown logicop function");
1027 return GEN6_LOGICOP_CLEAR;
1028 }
1029 }
1030
1031 /**
1032 * Translate a pipe blend function to the matching hardware blend function.
1033 */
1034 static int
1035 gen6_translate_pipe_blend(unsigned blend)
1036 {
1037 switch (blend) {
1038 case PIPE_BLEND_ADD: return GEN6_BLENDFUNCTION_ADD;
1039 case PIPE_BLEND_SUBTRACT: return GEN6_BLENDFUNCTION_SUBTRACT;
1040 case PIPE_BLEND_REVERSE_SUBTRACT: return GEN6_BLENDFUNCTION_REVERSE_SUBTRACT;
1041 case PIPE_BLEND_MIN: return GEN6_BLENDFUNCTION_MIN;
1042 case PIPE_BLEND_MAX: return GEN6_BLENDFUNCTION_MAX;
1043 default:
1044 assert(!"unknown blend function");
1045 return GEN6_BLENDFUNCTION_ADD;
1046 };
1047 }
1048
1049 /**
1050 * Translate a pipe blend factor to the matching hardware blend factor.
1051 */
1052 static int
1053 gen6_translate_pipe_blendfactor(unsigned blendfactor)
1054 {
1055 switch (blendfactor) {
1056 case PIPE_BLENDFACTOR_ONE: return GEN6_BLENDFACTOR_ONE;
1057 case PIPE_BLENDFACTOR_SRC_COLOR: return GEN6_BLENDFACTOR_SRC_COLOR;
1058 case PIPE_BLENDFACTOR_SRC_ALPHA: return GEN6_BLENDFACTOR_SRC_ALPHA;
1059 case PIPE_BLENDFACTOR_DST_ALPHA: return GEN6_BLENDFACTOR_DST_ALPHA;
1060 case PIPE_BLENDFACTOR_DST_COLOR: return GEN6_BLENDFACTOR_DST_COLOR;
1061 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE;
1062 case PIPE_BLENDFACTOR_CONST_COLOR: return GEN6_BLENDFACTOR_CONST_COLOR;
1063 case PIPE_BLENDFACTOR_CONST_ALPHA: return GEN6_BLENDFACTOR_CONST_ALPHA;
1064 case PIPE_BLENDFACTOR_SRC1_COLOR: return GEN6_BLENDFACTOR_SRC1_COLOR;
1065 case PIPE_BLENDFACTOR_SRC1_ALPHA: return GEN6_BLENDFACTOR_SRC1_ALPHA;
1066 case PIPE_BLENDFACTOR_ZERO: return GEN6_BLENDFACTOR_ZERO;
1067 case PIPE_BLENDFACTOR_INV_SRC_COLOR: return GEN6_BLENDFACTOR_INV_SRC_COLOR;
1068 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return GEN6_BLENDFACTOR_INV_SRC_ALPHA;
1069 case PIPE_BLENDFACTOR_INV_DST_ALPHA: return GEN6_BLENDFACTOR_INV_DST_ALPHA;
1070 case PIPE_BLENDFACTOR_INV_DST_COLOR: return GEN6_BLENDFACTOR_INV_DST_COLOR;
1071 case PIPE_BLENDFACTOR_INV_CONST_COLOR: return GEN6_BLENDFACTOR_INV_CONST_COLOR;
1072 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: return GEN6_BLENDFACTOR_INV_CONST_ALPHA;
1073 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: return GEN6_BLENDFACTOR_INV_SRC1_COLOR;
1074 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: return GEN6_BLENDFACTOR_INV_SRC1_ALPHA;
1075 default:
1076 assert(!"unknown blend factor");
1077 return GEN6_BLENDFACTOR_ONE;
1078 };
1079 }
1080
1081 /**
1082 * Translate a pipe stencil op to the matching hardware stencil op.
1083 */
1084 static int
1085 gen6_translate_pipe_stencil_op(unsigned stencil_op)
1086 {
1087 switch (stencil_op) {
1088 case PIPE_STENCIL_OP_KEEP: return GEN6_STENCILOP_KEEP;
1089 case PIPE_STENCIL_OP_ZERO: return GEN6_STENCILOP_ZERO;
1090 case PIPE_STENCIL_OP_REPLACE: return GEN6_STENCILOP_REPLACE;
1091 case PIPE_STENCIL_OP_INCR: return GEN6_STENCILOP_INCRSAT;
1092 case PIPE_STENCIL_OP_DECR: return GEN6_STENCILOP_DECRSAT;
1093 case PIPE_STENCIL_OP_INCR_WRAP: return GEN6_STENCILOP_INCR;
1094 case PIPE_STENCIL_OP_DECR_WRAP: return GEN6_STENCILOP_DECR;
1095 case PIPE_STENCIL_OP_INVERT: return GEN6_STENCILOP_INVERT;
1096 default:
1097 assert(!"unknown stencil op");
1098 return GEN6_STENCILOP_KEEP;
1099 }
1100 }
1101
1102 static int
1103 gen6_blend_factor_dst_alpha_forced_one(int factor)
1104 {
1105 switch (factor) {
1106 case GEN6_BLENDFACTOR_DST_ALPHA:
1107 return GEN6_BLENDFACTOR_ONE;
1108 case GEN6_BLENDFACTOR_INV_DST_ALPHA:
1109 case GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE:
1110 return GEN6_BLENDFACTOR_ZERO;
1111 default:
1112 return factor;
1113 }
1114 }
1115
1116 static uint32_t
1117 blend_get_rt_blend_enable_gen6(const struct ilo_dev *dev,
1118 const struct pipe_rt_blend_state *rt,
1119 bool dst_alpha_forced_one)
1120 {
1121 int rgb_src, rgb_dst, a_src, a_dst;
1122 uint32_t dw;
1123
1124 ILO_DEV_ASSERT(dev, 6, 7.5);
1125
1126 if (!rt->blend_enable)
1127 return 0;
1128
1129 rgb_src = gen6_translate_pipe_blendfactor(rt->rgb_src_factor);
1130 rgb_dst = gen6_translate_pipe_blendfactor(rt->rgb_dst_factor);
1131 a_src = gen6_translate_pipe_blendfactor(rt->alpha_src_factor);
1132 a_dst = gen6_translate_pipe_blendfactor(rt->alpha_dst_factor);
1133
1134 if (dst_alpha_forced_one) {
1135 rgb_src = gen6_blend_factor_dst_alpha_forced_one(rgb_src);
1136 rgb_dst = gen6_blend_factor_dst_alpha_forced_one(rgb_dst);
1137 a_src = gen6_blend_factor_dst_alpha_forced_one(a_src);
1138 a_dst = gen6_blend_factor_dst_alpha_forced_one(a_dst);
1139 }
1140
1141 dw = GEN6_RT_DW0_BLEND_ENABLE |
1142 gen6_translate_pipe_blend(rt->alpha_func) << 26 |
1143 a_src << 20 |
1144 a_dst << 15 |
1145 gen6_translate_pipe_blend(rt->rgb_func) << 11 |
1146 rgb_src << 5 |
1147 rgb_dst;
1148
1149 if (rt->rgb_func != rt->alpha_func ||
1150 rgb_src != a_src || rgb_dst != a_dst)
1151 dw |= GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE;
1152
1153 return dw;
1154 }
1155
1156 static uint32_t
1157 blend_get_rt_blend_enable_gen8(const struct ilo_dev *dev,
1158 const struct pipe_rt_blend_state *rt,
1159 bool dst_alpha_forced_one,
1160 bool *independent_alpha)
1161 {
1162 int rgb_src, rgb_dst, a_src, a_dst;
1163 uint32_t dw;
1164
1165 ILO_DEV_ASSERT(dev, 8, 8);
1166
1167 if (!rt->blend_enable) {
1168 *independent_alpha = false;
1169 return 0;
1170 }
1171
1172 rgb_src = gen6_translate_pipe_blendfactor(rt->rgb_src_factor);
1173 rgb_dst = gen6_translate_pipe_blendfactor(rt->rgb_dst_factor);
1174 a_src = gen6_translate_pipe_blendfactor(rt->alpha_src_factor);
1175 a_dst = gen6_translate_pipe_blendfactor(rt->alpha_dst_factor);
1176
1177 if (dst_alpha_forced_one) {
1178 rgb_src = gen6_blend_factor_dst_alpha_forced_one(rgb_src);
1179 rgb_dst = gen6_blend_factor_dst_alpha_forced_one(rgb_dst);
1180 a_src = gen6_blend_factor_dst_alpha_forced_one(a_src);
1181 a_dst = gen6_blend_factor_dst_alpha_forced_one(a_dst);
1182 }
1183
1184 dw = GEN8_RT_DW0_BLEND_ENABLE |
1185 rgb_src << 26 |
1186 rgb_dst << 21 |
1187 gen6_translate_pipe_blend(rt->rgb_func) << 18 |
1188 a_src << 13 |
1189 a_dst << 8 |
1190 gen6_translate_pipe_blend(rt->alpha_func) << 5;
1191
1192 *independent_alpha = (rt->rgb_func != rt->alpha_func ||
1193 rgb_src != a_src ||
1194 rgb_dst != a_dst);
1195
1196 return dw;
1197 }
1198
1199 static void
1200 blend_init_cso_gen6(const struct ilo_dev *dev,
1201 const struct pipe_blend_state *state,
1202 struct ilo_blend_state *blend,
1203 unsigned index)
1204 {
1205 const struct pipe_rt_blend_state *rt = &state->rt[index];
1206 struct ilo_blend_cso *cso = &blend->cso[index];
1207
1208 ILO_DEV_ASSERT(dev, 6, 7.5);
1209
1210 cso->payload[0] = 0;
1211 cso->payload[1] = GEN6_RT_DW1_COLORCLAMP_RTFORMAT |
1212 GEN6_RT_DW1_PRE_BLEND_CLAMP |
1213 GEN6_RT_DW1_POST_BLEND_CLAMP;
1214
1215 if (!(rt->colormask & PIPE_MASK_A))
1216 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_A;
1217 if (!(rt->colormask & PIPE_MASK_R))
1218 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_R;
1219 if (!(rt->colormask & PIPE_MASK_G))
1220 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_G;
1221 if (!(rt->colormask & PIPE_MASK_B))
1222 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_B;
1223
1224 /*
1225 * From the Sandy Bridge PRM, volume 2 part 1, page 365:
1226 *
1227 * "Color Buffer Blending and Logic Ops must not be enabled
1228 * simultaneously, or behavior is UNDEFINED."
1229 *
1230 * Since state->logicop_enable takes precedence over rt->blend_enable,
1231 * no special care is needed.
1232 */
1233 if (state->logicop_enable) {
1234 cso->dw_blend = 0;
1235 cso->dw_blend_dst_alpha_forced_one = 0;
1236 } else {
1237 cso->dw_blend = blend_get_rt_blend_enable_gen6(dev, rt, false);
1238 cso->dw_blend_dst_alpha_forced_one =
1239 blend_get_rt_blend_enable_gen6(dev, rt, true);
1240 }
1241 }
1242
1243 static bool
1244 blend_init_cso_gen8(const struct ilo_dev *dev,
1245 const struct pipe_blend_state *state,
1246 struct ilo_blend_state *blend,
1247 unsigned index)
1248 {
1249 const struct pipe_rt_blend_state *rt = &state->rt[index];
1250 struct ilo_blend_cso *cso = &blend->cso[index];
1251 bool independent_alpha = false;
1252
1253 ILO_DEV_ASSERT(dev, 8, 8);
1254
1255 cso->payload[0] = 0;
1256 cso->payload[1] = GEN8_RT_DW1_COLORCLAMP_RTFORMAT |
1257 GEN8_RT_DW1_PRE_BLEND_CLAMP |
1258 GEN8_RT_DW1_POST_BLEND_CLAMP;
1259
1260 if (!(rt->colormask & PIPE_MASK_A))
1261 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_A;
1262 if (!(rt->colormask & PIPE_MASK_R))
1263 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_R;
1264 if (!(rt->colormask & PIPE_MASK_G))
1265 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_G;
1266 if (!(rt->colormask & PIPE_MASK_B))
1267 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_B;
1268
1269 if (state->logicop_enable) {
1270 cso->dw_blend = 0;
1271 cso->dw_blend_dst_alpha_forced_one = 0;
1272 } else {
1273 bool tmp[2];
1274
1275 cso->dw_blend = blend_get_rt_blend_enable_gen8(dev, rt, false, &tmp[0]);
1276 cso->dw_blend_dst_alpha_forced_one =
1277 blend_get_rt_blend_enable_gen8(dev, rt, true, &tmp[1]);
1278
1279 if (tmp[0] || tmp[1])
1280 independent_alpha = true;
1281 }
1282
1283 return independent_alpha;
1284 }
1285
1286 static uint32_t
1287 blend_get_logicop_enable_gen6(const struct ilo_dev *dev,
1288 const struct pipe_blend_state *state)
1289 {
1290 ILO_DEV_ASSERT(dev, 6, 7.5);
1291
1292 if (!state->logicop_enable)
1293 return 0;
1294
1295 return GEN6_RT_DW1_LOGICOP_ENABLE |
1296 gen6_translate_pipe_logicop(state->logicop_func) << 18;
1297 }
1298
1299 static uint32_t
1300 blend_get_logicop_enable_gen8(const struct ilo_dev *dev,
1301 const struct pipe_blend_state *state)
1302 {
1303 ILO_DEV_ASSERT(dev, 8, 8);
1304
1305 if (!state->logicop_enable)
1306 return 0;
1307
1308 return GEN8_RT_DW1_LOGICOP_ENABLE |
1309 gen6_translate_pipe_logicop(state->logicop_func) << 27;
1310 }
1311
1312 static uint32_t
1313 blend_get_alpha_mod_gen6(const struct ilo_dev *dev,
1314 const struct pipe_blend_state *state,
1315 bool dual_blend)
1316 {
1317 uint32_t dw = 0;
1318
1319 ILO_DEV_ASSERT(dev, 6, 7.5);
1320
1321 if (state->alpha_to_coverage) {
1322 dw |= GEN6_RT_DW1_ALPHA_TO_COVERAGE;
1323 if (ilo_dev_gen(dev) >= ILO_GEN(7))
1324 dw |= GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER;
1325 }
1326 /*
1327 * From the Sandy Bridge PRM, volume 2 part 1, page 378:
1328 *
1329 * "If Dual Source Blending is enabled, this bit (AlphaToOne Enable)
1330 * must be disabled."
1331 */
1332 if (state->alpha_to_one && !dual_blend)
1333 dw |= GEN6_RT_DW1_ALPHA_TO_ONE;
1334
1335 return dw;
1336 }
1337
1338 static uint32_t
1339 blend_get_alpha_mod_gen8(const struct ilo_dev *dev,
1340 const struct pipe_blend_state *state,
1341 bool dual_blend)
1342 {
1343 uint32_t dw = 0;
1344
1345 ILO_DEV_ASSERT(dev, 8, 8);
1346
1347 if (state->alpha_to_coverage) {
1348 dw |= GEN8_BLEND_DW0_ALPHA_TO_COVERAGE |
1349 GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER;
1350 }
1351
1352 if (state->alpha_to_one && !dual_blend)
1353 dw |= GEN8_BLEND_DW0_ALPHA_TO_ONE;
1354
1355 return dw;
1356 }
1357
1358 static uint32_t
1359 blend_get_ps_blend_gen8(const struct ilo_dev *dev, uint32_t rt_dw0)
1360 {
1361 int rgb_src, rgb_dst, a_src, a_dst;
1362 uint32_t dw;
1363
1364 ILO_DEV_ASSERT(dev, 8, 8);
1365
1366 if (!(rt_dw0 & GEN8_RT_DW0_BLEND_ENABLE))
1367 return 0;
1368
1369 a_src = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_SRC_ALPHA_FACTOR);
1370 a_dst = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_DST_ALPHA_FACTOR);
1371 rgb_src = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_SRC_COLOR_FACTOR);
1372 rgb_dst = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_DST_COLOR_FACTOR);
1373
1374 dw = GEN8_PS_BLEND_DW1_BLEND_ENABLE;
1375 dw |= GEN_SHIFT32(a_src, GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR);
1376 dw |= GEN_SHIFT32(a_dst, GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR);
1377 dw |= GEN_SHIFT32(rgb_src, GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR);
1378 dw |= GEN_SHIFT32(rgb_dst, GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR);
1379
1380 if (a_src != rgb_src || a_dst != rgb_dst)
1381 dw |= GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE;
1382
1383 return dw;
1384 }
1385
1386 void
1387 ilo_gpe_init_blend(const struct ilo_dev *dev,
1388 const struct pipe_blend_state *state,
1389 struct ilo_blend_state *blend)
1390 {
1391 unsigned i;
1392
1393 ILO_DEV_ASSERT(dev, 6, 8);
1394
1395 blend->dual_blend = (util_blend_state_is_dual(state, 0) &&
1396 state->rt[0].blend_enable &&
1397 !state->logicop_enable);
1398 blend->alpha_to_coverage = state->alpha_to_coverage;
1399
1400 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1401 bool independent_alpha;
1402
1403 blend->dw_alpha_mod =
1404 blend_get_alpha_mod_gen8(dev, state, blend->dual_blend);
1405 blend->dw_logicop = blend_get_logicop_enable_gen8(dev, state);
1406 blend->dw_shared = (state->dither) ? GEN8_BLEND_DW0_DITHER_ENABLE : 0;
1407
1408 independent_alpha = blend_init_cso_gen8(dev, state, blend, 0);
1409 if (independent_alpha)
1410 blend->dw_shared |= GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE;
1411
1412 blend->dw_ps_blend = blend_get_ps_blend_gen8(dev,
1413 blend->cso[0].dw_blend);
1414 blend->dw_ps_blend_dst_alpha_forced_one = blend_get_ps_blend_gen8(dev,
1415 blend->cso[0].dw_blend_dst_alpha_forced_one);
1416
1417 if (state->independent_blend_enable) {
1418 for (i = 1; i < Elements(blend->cso); i++) {
1419 independent_alpha = blend_init_cso_gen8(dev, state, blend, i);
1420 if (independent_alpha)
1421 blend->dw_shared |= GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE;
1422 }
1423 } else {
1424 for (i = 1; i < Elements(blend->cso); i++)
1425 blend->cso[i] = blend->cso[0];
1426 }
1427 } else {
1428 blend->dw_alpha_mod =
1429 blend_get_alpha_mod_gen6(dev, state, blend->dual_blend);
1430 blend->dw_logicop = blend_get_logicop_enable_gen6(dev, state);
1431 blend->dw_shared = (state->dither) ? GEN6_RT_DW1_DITHER_ENABLE : 0;
1432
1433 blend->dw_ps_blend = 0;
1434 blend->dw_ps_blend_dst_alpha_forced_one = 0;
1435
1436 blend_init_cso_gen6(dev, state, blend, 0);
1437 if (state->independent_blend_enable) {
1438 for (i = 1; i < Elements(blend->cso); i++)
1439 blend_init_cso_gen6(dev, state, blend, i);
1440 } else {
1441 for (i = 1; i < Elements(blend->cso); i++)
1442 blend->cso[i] = blend->cso[0];
1443 }
1444 }
1445 }
1446
1447 /**
1448 * Translate a pipe DSA test function to the matching hardware compare
1449 * function.
1450 */
1451 static int
1452 gen6_translate_dsa_func(unsigned func)
1453 {
1454 switch (func) {
1455 case PIPE_FUNC_NEVER: return GEN6_COMPAREFUNCTION_NEVER;
1456 case PIPE_FUNC_LESS: return GEN6_COMPAREFUNCTION_LESS;
1457 case PIPE_FUNC_EQUAL: return GEN6_COMPAREFUNCTION_EQUAL;
1458 case PIPE_FUNC_LEQUAL: return GEN6_COMPAREFUNCTION_LEQUAL;
1459 case PIPE_FUNC_GREATER: return GEN6_COMPAREFUNCTION_GREATER;
1460 case PIPE_FUNC_NOTEQUAL: return GEN6_COMPAREFUNCTION_NOTEQUAL;
1461 case PIPE_FUNC_GEQUAL: return GEN6_COMPAREFUNCTION_GEQUAL;
1462 case PIPE_FUNC_ALWAYS: return GEN6_COMPAREFUNCTION_ALWAYS;
1463 default:
1464 assert(!"unknown depth/stencil/alpha test function");
1465 return GEN6_COMPAREFUNCTION_NEVER;
1466 }
1467 }
1468
1469 static uint32_t
1470 dsa_get_stencil_enable_gen6(const struct ilo_dev *dev,
1471 const struct pipe_stencil_state *stencil0,
1472 const struct pipe_stencil_state *stencil1)
1473 {
1474 uint32_t dw;
1475
1476 ILO_DEV_ASSERT(dev, 6, 7.5);
1477
1478 if (!stencil0->enabled)
1479 return 0;
1480
1481 /*
1482 * From the Sandy Bridge PRM, volume 2 part 1, page 359:
1483 *
1484 * "If the Depth Buffer is either undefined or does not have a surface
1485 * format of D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT and separate
1486 * stencil buffer is disabled, Stencil Test Enable must be DISABLED"
1487 *
1488 * From the Sandy Bridge PRM, volume 2 part 1, page 370:
1489 *
1490 * "This field (Stencil Test Enable) cannot be enabled if
1491 * Surface Format in 3DSTATE_DEPTH_BUFFER is set to D16_UNORM."
1492 *
1493 * TODO We do not check these yet.
1494 */
1495 dw = GEN6_ZS_DW0_STENCIL_TEST_ENABLE |
1496 gen6_translate_dsa_func(stencil0->func) << 28 |
1497 gen6_translate_pipe_stencil_op(stencil0->fail_op) << 25 |
1498 gen6_translate_pipe_stencil_op(stencil0->zfail_op) << 22 |
1499 gen6_translate_pipe_stencil_op(stencil0->zpass_op) << 19;
1500 if (stencil0->writemask)
1501 dw |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
1502
1503 if (stencil1->enabled) {
1504 dw |= GEN6_ZS_DW0_STENCIL1_ENABLE |
1505 gen6_translate_dsa_func(stencil1->func) << 12 |
1506 gen6_translate_pipe_stencil_op(stencil1->fail_op) << 9 |
1507 gen6_translate_pipe_stencil_op(stencil1->zfail_op) << 6 |
1508 gen6_translate_pipe_stencil_op(stencil1->zpass_op) << 3;
1509 if (stencil1->writemask)
1510 dw |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
1511 }
1512
1513 return dw;
1514 }
1515
1516 static uint32_t
1517 dsa_get_stencil_enable_gen8(const struct ilo_dev *dev,
1518 const struct pipe_stencil_state *stencil0,
1519 const struct pipe_stencil_state *stencil1)
1520 {
1521 uint32_t dw;
1522
1523 ILO_DEV_ASSERT(dev, 8, 8);
1524
1525 if (!stencil0->enabled)
1526 return 0;
1527
1528 dw = gen6_translate_pipe_stencil_op(stencil0->fail_op) << 29 |
1529 gen6_translate_pipe_stencil_op(stencil0->zfail_op) << 26 |
1530 gen6_translate_pipe_stencil_op(stencil0->zpass_op) << 23 |
1531 gen6_translate_dsa_func(stencil0->func) << 8 |
1532 GEN8_ZS_DW1_STENCIL_TEST_ENABLE;
1533 if (stencil0->writemask)
1534 dw |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
1535
1536 if (stencil1->enabled) {
1537 dw |= gen6_translate_dsa_func(stencil1->func) << 20 |
1538 gen6_translate_pipe_stencil_op(stencil1->fail_op) << 17 |
1539 gen6_translate_pipe_stencil_op(stencil1->zfail_op) << 14 |
1540 gen6_translate_pipe_stencil_op(stencil1->zpass_op) << 11 |
1541 GEN8_ZS_DW1_STENCIL1_ENABLE;
1542 if (stencil1->writemask)
1543 dw |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
1544 }
1545
1546 return dw;
1547 }
1548
1549 static uint32_t
1550 dsa_get_depth_enable_gen6(const struct ilo_dev *dev,
1551 const struct pipe_depth_state *state)
1552 {
1553 uint32_t dw;
1554
1555 ILO_DEV_ASSERT(dev, 6, 7.5);
1556
1557 /*
1558 * From the Sandy Bridge PRM, volume 2 part 1, page 360:
1559 *
1560 * "Enabling the Depth Test function without defining a Depth Buffer is
1561 * UNDEFINED."
1562 *
1563 * From the Sandy Bridge PRM, volume 2 part 1, page 375:
1564 *
1565 * "A Depth Buffer must be defined before enabling writes to it, or
1566 * operation is UNDEFINED."
1567 *
1568 * TODO We do not check these yet.
1569 */
1570 if (state->enabled) {
1571 dw = GEN6_ZS_DW2_DEPTH_TEST_ENABLE |
1572 gen6_translate_dsa_func(state->func) << 27;
1573 } else {
1574 dw = GEN6_COMPAREFUNCTION_ALWAYS << 27;
1575 }
1576
1577 if (state->writemask)
1578 dw |= GEN6_ZS_DW2_DEPTH_WRITE_ENABLE;
1579
1580 return dw;
1581 }
1582
1583 static uint32_t
1584 dsa_get_depth_enable_gen8(const struct ilo_dev *dev,
1585 const struct pipe_depth_state *state)
1586 {
1587 uint32_t dw;
1588
1589 ILO_DEV_ASSERT(dev, 8, 8);
1590
1591 if (state->enabled) {
1592 dw = GEN8_ZS_DW1_DEPTH_TEST_ENABLE |
1593 gen6_translate_dsa_func(state->func) << 5;
1594 } else {
1595 dw = GEN6_COMPAREFUNCTION_ALWAYS << 5;
1596 }
1597
1598 if (state->writemask)
1599 dw |= GEN8_ZS_DW1_DEPTH_WRITE_ENABLE;
1600
1601 return dw;
1602 }
1603
1604 static uint32_t
1605 dsa_get_alpha_enable_gen6(const struct ilo_dev *dev,
1606 const struct pipe_alpha_state *state)
1607 {
1608 uint32_t dw;
1609
1610 ILO_DEV_ASSERT(dev, 6, 7.5);
1611
1612 if (!state->enabled)
1613 return 0;
1614
1615 /* this will be ORed to BLEND_STATE */
1616 dw = GEN6_RT_DW1_ALPHA_TEST_ENABLE |
1617 gen6_translate_dsa_func(state->func) << 13;
1618
1619 return dw;
1620 }
1621
1622 static uint32_t
1623 dsa_get_alpha_enable_gen8(const struct ilo_dev *dev,
1624 const struct pipe_alpha_state *state)
1625 {
1626 uint32_t dw;
1627
1628 ILO_DEV_ASSERT(dev, 8, 8);
1629
1630 if (!state->enabled)
1631 return 0;
1632
1633 /* this will be ORed to BLEND_STATE */
1634 dw = GEN8_BLEND_DW0_ALPHA_TEST_ENABLE |
1635 gen6_translate_dsa_func(state->func) << 24;
1636
1637 return dw;
1638 }
1639
1640 void
1641 ilo_gpe_init_dsa(const struct ilo_dev *dev,
1642 const struct pipe_depth_stencil_alpha_state *state,
1643 struct ilo_dsa_state *dsa)
1644 {
1645 ILO_DEV_ASSERT(dev, 6, 8);
1646
1647 STATIC_ASSERT(Elements(dsa->payload) >= 3);
1648
1649 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1650 const uint32_t dw_stencil = dsa_get_stencil_enable_gen8(dev,
1651 &state->stencil[0], &state->stencil[1]);
1652 const uint32_t dw_depth = dsa_get_depth_enable_gen8(dev, &state->depth);
1653
1654 assert(!(dw_stencil & dw_depth));
1655 dsa->payload[0] = dw_stencil | dw_depth;
1656
1657 dsa->dw_blend_alpha = dsa_get_alpha_enable_gen8(dev, &state->alpha);
1658 dsa->dw_ps_blend_alpha = (state->alpha.enabled) ?
1659 GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE : 0;
1660 } else {
1661 dsa->payload[0] = dsa_get_stencil_enable_gen6(dev,
1662 &state->stencil[0], &state->stencil[1]);
1663 dsa->payload[2] = dsa_get_depth_enable_gen6(dev, &state->depth);
1664
1665 dsa->dw_blend_alpha = dsa_get_alpha_enable_gen6(dev, &state->alpha);
1666 dsa->dw_ps_blend_alpha = 0;
1667 }
1668
1669 dsa->payload[1] = state->stencil[0].valuemask << 24 |
1670 state->stencil[0].writemask << 16 |
1671 state->stencil[1].valuemask << 8 |
1672 state->stencil[1].writemask;
1673
1674 dsa->alpha_ref = float_to_ubyte(state->alpha.ref_value);
1675 }
1676
1677 void
1678 ilo_gpe_set_scissor(const struct ilo_dev *dev,
1679 unsigned start_slot,
1680 unsigned num_states,
1681 const struct pipe_scissor_state *states,
1682 struct ilo_scissor_state *scissor)
1683 {
1684 unsigned i;
1685
1686 ILO_DEV_ASSERT(dev, 6, 8);
1687
1688 for (i = 0; i < num_states; i++) {
1689 uint16_t min_x, min_y, max_x, max_y;
1690
1691 /* both max and min are inclusive in SCISSOR_RECT */
1692 if (states[i].minx < states[i].maxx &&
1693 states[i].miny < states[i].maxy) {
1694 min_x = states[i].minx;
1695 min_y = states[i].miny;
1696 max_x = states[i].maxx - 1;
1697 max_y = states[i].maxy - 1;
1698 }
1699 else {
1700 /* we have to make min greater than max */
1701 min_x = 1;
1702 min_y = 1;
1703 max_x = 0;
1704 max_y = 0;
1705 }
1706
1707 scissor->payload[(start_slot + i) * 2 + 0] = min_y << 16 | min_x;
1708 scissor->payload[(start_slot + i) * 2 + 1] = max_y << 16 | max_x;
1709 }
1710
1711 if (!start_slot && num_states)
1712 scissor->scissor0 = states[0];
1713 }
1714
1715 void
1716 ilo_gpe_set_scissor_null(const struct ilo_dev *dev,
1717 struct ilo_scissor_state *scissor)
1718 {
1719 unsigned i;
1720
1721 for (i = 0; i < Elements(scissor->payload); i += 2) {
1722 scissor->payload[i + 0] = 1 << 16 | 1;
1723 scissor->payload[i + 1] = 0;
1724 }
1725 }
1726
1727 static void
1728 fb_set_blend_caps(const struct ilo_dev *dev,
1729 enum pipe_format format,
1730 struct ilo_fb_blend_caps *caps)
1731 {
1732 const struct util_format_description *desc =
1733 util_format_description(format);
1734 const int ch = util_format_get_first_non_void_channel(format);
1735
1736 memset(caps, 0, sizeof(*caps));
1737
1738 if (format == PIPE_FORMAT_NONE || desc->is_mixed)
1739 return;
1740
1741 /*
1742 * From the Sandy Bridge PRM, volume 2 part 1, page 365:
1743 *
1744 * "Logic Ops are only supported on *_UNORM surfaces (excluding _SRGB
1745 * variants), otherwise Logic Ops must be DISABLED."
1746 *
1747 * According to the classic driver, this is lifted on Gen8+.
1748 */
1749 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1750 caps->can_logicop = true;
1751 } else {
1752 caps->can_logicop = (ch >= 0 && desc->channel[ch].normalized &&
1753 desc->channel[ch].type == UTIL_FORMAT_TYPE_UNSIGNED &&
1754 desc->colorspace == UTIL_FORMAT_COLORSPACE_RGB);
1755 }
1756
1757 /* no blending for pure integer formats */
1758 caps->can_blend = !util_format_is_pure_integer(format);
1759
1760 /*
1761 * From the Sandy Bridge PRM, volume 2 part 1, page 382:
1762 *
1763 * "Alpha Test can only be enabled if Pixel Shader outputs a float
1764 * alpha value."
1765 */
1766 caps->can_alpha_test = !util_format_is_pure_integer(format);
1767
1768 caps->dst_alpha_forced_one =
1769 (ilo_format_translate_render(dev, format) !=
1770 ilo_format_translate_color(dev, format));
1771
1772 /* sanity check */
1773 if (caps->dst_alpha_forced_one) {
1774 enum pipe_format render_format;
1775
1776 switch (format) {
1777 case PIPE_FORMAT_B8G8R8X8_UNORM:
1778 render_format = PIPE_FORMAT_B8G8R8A8_UNORM;
1779 break;
1780 default:
1781 render_format = PIPE_FORMAT_NONE;
1782 break;
1783 }
1784
1785 assert(ilo_format_translate_render(dev, format) ==
1786 ilo_format_translate_color(dev, render_format));
1787 }
1788 }
1789
1790 void
1791 ilo_gpe_set_fb(const struct ilo_dev *dev,
1792 const struct pipe_framebuffer_state *state,
1793 struct ilo_fb_state *fb)
1794 {
1795 const struct pipe_surface *first_surf = NULL;
1796 int i;
1797
1798 ILO_DEV_ASSERT(dev, 6, 8);
1799
1800 util_copy_framebuffer_state(&fb->state, state);
1801
1802 for (i = 0; i < state->nr_cbufs; i++) {
1803 if (state->cbufs[i]) {
1804 fb_set_blend_caps(dev, state->cbufs[i]->format, &fb->blend_caps[i]);
1805
1806 if (!first_surf)
1807 first_surf = state->cbufs[i];
1808 } else {
1809 fb_set_blend_caps(dev, PIPE_FORMAT_NONE, &fb->blend_caps[i]);
1810 }
1811 }
1812
1813 if (!first_surf && state->zsbuf)
1814 first_surf = state->zsbuf;
1815
1816 fb->num_samples = (first_surf) ? first_surf->texture->nr_samples : 1;
1817 if (!fb->num_samples)
1818 fb->num_samples = 1;
1819
1820 /*
1821 * The PRMs list several restrictions when the framebuffer has more than
1822 * one surface. It seems they are actually lifted on GEN6+.
1823 */
1824 }