2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2015 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "ilo_debug.h"
29 #include "ilo_state_raster.h"
32 raster_validate_gen6_clip(const struct ilo_dev
*dev
,
33 const struct ilo_state_raster_info
*info
)
35 const struct ilo_state_raster_clip_info
*clip
= &info
->clip
;
37 ILO_DEV_ASSERT(dev
, 6, 8);
39 assert(clip
->viewport_count
);
42 * From the Sandy Bridge PRM, volume 2 part 1, page 188:
44 * ""Clip Distance Cull Test Enable Bitmask" and "Clip Distance Clip
45 * Test Enable Bitmask" should not have overlapping bits in the mask,
46 * else the results are undefined."
48 assert(!(clip
->user_cull_enables
& clip
->user_clip_enables
));
50 if (ilo_dev_gen(dev
) < ILO_GEN(9))
51 assert(clip
->z_near_enable
== clip
->z_far_enable
);
57 raster_set_gen6_3DSTATE_CLIP(struct ilo_state_raster
*rs
,
58 const struct ilo_dev
*dev
,
59 const struct ilo_state_raster_info
*info
)
61 const struct ilo_state_raster_clip_info
*clip
= &info
->clip
;
62 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
63 const struct ilo_state_raster_tri_info
*tri
= &info
->tri
;
64 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
65 uint32_t dw1
, dw2
, dw3
;
67 ILO_DEV_ASSERT(dev
, 6, 8);
69 if (!raster_validate_gen6_clip(dev
, info
))
72 dw1
= clip
->user_cull_enables
<< GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT
;
74 if (clip
->stats_enable
)
75 dw1
|= GEN6_CLIP_DW1_STATISTICS
;
77 if (ilo_dev_gen(dev
) >= ILO_GEN(7)) {
79 * From the Ivy Bridge PRM, volume 2 part 1, page 219:
81 * "Workaround : Due to Hardware issue "EarlyCull" needs to be
82 * enabled only for the cases where the incoming primitive topology
83 * into the clipper guaranteed to be Trilist."
85 * What does this mean?
87 dw1
|= GEN7_CLIP_DW1_SUBPIXEL_8BITS
|
88 GEN7_CLIP_DW1_EARLY_CULL_ENABLE
;
90 if (ilo_dev_gen(dev
) <= ILO_GEN(7.5)) {
91 dw1
|= tri
->front_winding
<< GEN7_CLIP_DW1_FRONT_WINDING__SHIFT
|
92 tri
->cull_mode
<< GEN7_CLIP_DW1_CULL_MODE__SHIFT
;
96 dw2
= clip
->user_clip_enables
<< GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT
|
97 GEN6_CLIPMODE_NORMAL
<< GEN6_CLIP_DW2_CLIP_MODE__SHIFT
;
99 if (clip
->clip_enable
)
100 dw2
|= GEN6_CLIP_DW2_CLIP_ENABLE
;
102 if (clip
->z_near_zero
)
103 dw2
|= GEN6_CLIP_DW2_APIMODE_D3D
;
105 dw2
|= GEN6_CLIP_DW2_APIMODE_OGL
;
107 if (clip
->xy_test_enable
)
108 dw2
|= GEN6_CLIP_DW2_XY_TEST_ENABLE
;
110 if (ilo_dev_gen(dev
) < ILO_GEN(8) && clip
->z_near_enable
)
111 dw2
|= GEN6_CLIP_DW2_Z_TEST_ENABLE
;
113 if (clip
->gb_test_enable
)
114 dw2
|= GEN6_CLIP_DW2_GB_TEST_ENABLE
;
116 if (scan
->barycentric_interps
& (GEN6_INTERP_NONPERSPECTIVE_PIXEL
|
117 GEN6_INTERP_NONPERSPECTIVE_CENTROID
|
118 GEN6_INTERP_NONPERSPECTIVE_SAMPLE
))
119 dw2
|= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE
;
121 if (setup
->first_vertex_provoking
) {
122 dw2
|= 0 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT
|
123 0 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT
|
124 1 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT
;
126 dw2
|= 2 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT
|
127 1 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT
|
128 2 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT
;
131 dw3
= 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT
|
132 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT
|
133 (clip
->viewport_count
- 1) << GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT
;
135 if (clip
->force_rtaindex_zero
)
136 dw3
|= GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO
;
138 STATIC_ASSERT(ARRAY_SIZE(rs
->clip
) >= 3);
147 raster_params_is_gen6_line_aa_allowed(const struct ilo_dev
*dev
,
148 const struct ilo_state_raster_params_info
*params
)
150 ILO_DEV_ASSERT(dev
, 6, 8);
153 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
155 * "This field (Anti-aliasing Enable) must be disabled if any of the
156 * render targets have integer (UINT or SINT) surface format."
158 if (params
->any_integer_rt
)
162 * From the Sandy Bridge PRM, volume 2 part 1, page 321:
164 * "[DevSNB+]: This field (Hierarchical Depth Buffer Enable) must be
165 * disabled if Anti-aliasing Enable in 3DSTATE_SF is enabled.
167 if (ilo_dev_gen(dev
) == ILO_GEN(6) && params
->hiz_enable
)
174 raster_get_gen6_effective_line(const struct ilo_dev
*dev
,
175 const struct ilo_state_raster_info
*info
,
176 struct ilo_state_raster_line_info
*line
)
178 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
179 const struct ilo_state_raster_params_info
*params
= &info
->params
;
184 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
186 * "This field (Anti-aliasing Enable) is ignored when Multisample
187 * Rasterization Mode is MSRASTMODE_ON_xx."
189 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
191 * "Setting a Line Width of 0.0 specifies the rasterization of the
192 * "thinnest" (one-pixel-wide), non-antialiased lines. Note that
193 * this effectively overrides the effect of AAEnable (though the
194 * AAEnable state variable is not modified). Lines rendered with
195 * zero Line Width are rasterized using GIQ (Grid Intersection
196 * Quantization) rules as specified by the GDI and Direct3D APIs."
198 * "Software must not program a value of 0.0 when running in
199 * MSRASTMODE_ON_xxx modes - zero-width lines are not available
200 * when multisampling rasterization is enabled."
202 * From the Sandy Bridge PRM, volume 2 part 1, page 294:
204 * "Line stipple, controlled via the Line Stipple Enable state variable
205 * in WM_STATE, discards certain pixels that are produced by non-AA
206 * line rasterization."
208 if (setup
->line_msaa_enable
||
209 !raster_params_is_gen6_line_aa_allowed(dev
, params
))
210 line
->aa_enable
= false;
211 if (setup
->line_msaa_enable
|| line
->aa_enable
) {
212 line
->stipple_enable
= false;
213 line
->giq_enable
= false;
214 line
->giq_last_pixel
= false;
219 raster_validate_gen8_raster(const struct ilo_dev
*dev
,
220 const struct ilo_state_raster_info
*info
)
222 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
223 const struct ilo_state_raster_tri_info
*tri
= &info
->tri
;
225 ILO_DEV_ASSERT(dev
, 6, 8);
228 * From the Sandy Bridge PRM, volume 2 part 1, page 249:
230 * "This setting (SOLID) is required when rendering rectangle
231 * (RECTLIST) objects.
233 if (tri
->fill_mode_front
!= GEN6_FILLMODE_SOLID
||
234 tri
->fill_mode_back
!= GEN6_FILLMODE_SOLID
)
235 assert(!setup
->cv_is_rectangle
);
240 static enum gen_msrast_mode
241 raster_setup_get_gen6_msrast_mode(const struct ilo_dev
*dev
,
242 const struct ilo_state_raster_setup_info
*setup
)
244 ILO_DEV_ASSERT(dev
, 6, 8);
246 if (setup
->line_msaa_enable
) {
247 return (setup
->msaa_enable
) ? GEN6_MSRASTMODE_ON_PATTERN
:
248 GEN6_MSRASTMODE_ON_PIXEL
;
250 return (setup
->msaa_enable
) ? GEN6_MSRASTMODE_OFF_PATTERN
:
251 GEN6_MSRASTMODE_OFF_PIXEL
;
256 get_gen6_line_width(const struct ilo_dev
*dev
, float fwidth
,
257 bool line_aa_enable
, bool line_giq_enable
)
261 ILO_DEV_ASSERT(dev
, 6, 8);
264 line_width
= (int) (fwidth
* 128.0f
+ 0.5f
);
267 * Smooth lines should intersect ceil(line_width) or (ceil(line_width) + 1)
268 * pixels in the minor direction. We have to make the lines slightly
269 * thicker, 0.5 pixel on both sides, so that they intersect that many
275 line_width
= CLAMP(line_width
, 1, 1023);
277 if (line_giq_enable
&& line_width
== 128)
284 get_gen6_point_width(const struct ilo_dev
*dev
, float fwidth
)
288 ILO_DEV_ASSERT(dev
, 6, 8);
291 point_width
= (int) (fwidth
* 8.0f
+ 0.5f
);
292 point_width
= CLAMP(point_width
, 1, 2047);
298 raster_set_gen7_3DSTATE_SF(struct ilo_state_raster
*rs
,
299 const struct ilo_dev
*dev
,
300 const struct ilo_state_raster_info
*info
,
301 const struct ilo_state_raster_line_info
*line
)
303 const struct ilo_state_raster_clip_info
*clip
= &info
->clip
;
304 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
305 const struct ilo_state_raster_point_info
*point
= &info
->point
;
306 const struct ilo_state_raster_tri_info
*tri
= &info
->tri
;
307 const struct ilo_state_raster_params_info
*params
= &info
->params
;
308 const enum gen_msrast_mode msrast
=
309 raster_setup_get_gen6_msrast_mode(dev
, setup
);
310 const int line_width
= get_gen6_line_width(dev
, params
->line_width
,
311 line
->aa_enable
, line
->giq_enable
);
312 const int point_width
= get_gen6_point_width(dev
, params
->point_width
);
313 uint32_t dw1
, dw2
, dw3
;
315 ILO_DEV_ASSERT(dev
, 6, 7.5);
317 if (!raster_validate_gen8_raster(dev
, info
))
320 dw1
= tri
->fill_mode_front
<< GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT
|
321 tri
->fill_mode_back
<< GEN7_SF_DW1_FILL_MODE_BACK__SHIFT
|
322 tri
->front_winding
<< GEN7_SF_DW1_FRONT_WINDING__SHIFT
;
324 if (ilo_dev_gen(dev
) >= ILO_GEN(7) && ilo_dev_gen(dev
) <= ILO_GEN(7.5)) {
325 enum gen_depth_format format
;
327 /* do it here as we want 0x0 to be valid */
328 switch (tri
->depth_offset_format
) {
329 case GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT
:
330 format
= GEN6_ZFORMAT_D32_FLOAT
;
332 case GEN6_ZFORMAT_D24_UNORM_S8_UINT
:
333 format
= GEN6_ZFORMAT_D24_UNORM_X8_UINT
;
336 format
= tri
->depth_offset_format
;
340 dw1
|= format
<< GEN7_SF_DW1_DEPTH_FORMAT__SHIFT
;
344 * From the Sandy Bridge PRM, volume 2 part 1, page 248:
346 * "This bit (Statistics Enable) should be set whenever clipping is
347 * enabled and the Statistics Enable bit is set in CLIP_STATE. It
348 * should be cleared if clipping is disabled or Statistics Enable in
349 * CLIP_STATE is clear."
351 if (clip
->stats_enable
&& clip
->clip_enable
)
352 dw1
|= GEN7_SF_DW1_STATISTICS
;
355 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
357 * "This bit (Legacy Global Depth Bias Enable, Global Depth Offset
358 * Enable Solid , Global Depth Offset Enable Wireframe, and Global
359 * Depth Offset Enable Point) should be set whenever non zero depth
360 * bias (Slope, Bias) values are used. Setting this bit may have some
361 * degradation of performance for some workloads."
363 * But it seems fine to ignore that.
365 if (tri
->depth_offset_solid
)
366 dw1
|= GEN7_SF_DW1_DEPTH_OFFSET_SOLID
;
367 if (tri
->depth_offset_wireframe
)
368 dw1
|= GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME
;
369 if (tri
->depth_offset_point
)
370 dw1
|= GEN7_SF_DW1_DEPTH_OFFSET_POINT
;
372 if (setup
->viewport_transform
)
373 dw1
|= GEN7_SF_DW1_VIEWPORT_TRANSFORM
;
375 dw2
= tri
->cull_mode
<< GEN7_SF_DW2_CULL_MODE__SHIFT
|
376 line_width
<< GEN7_SF_DW2_LINE_WIDTH__SHIFT
|
377 GEN7_SF_DW2_AA_LINE_CAP_1_0
|
378 msrast
<< GEN7_SF_DW2_MSRASTMODE__SHIFT
;
381 dw2
|= GEN7_SF_DW2_AA_LINE_ENABLE
;
383 if (ilo_dev_gen(dev
) == ILO_GEN(7.5) && line
->stipple_enable
)
384 dw2
|= GEN75_SF_DW2_LINE_STIPPLE_ENABLE
;
386 if (setup
->scissor_enable
)
387 dw2
|= GEN7_SF_DW2_SCISSOR_ENABLE
;
389 dw3
= GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE
|
390 GEN7_SF_DW3_SUBPIXEL_8BITS
;
392 /* this has no effect when line_width != 0 */
393 if (line
->giq_last_pixel
)
394 dw3
|= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE
;
396 if (setup
->first_vertex_provoking
) {
397 dw3
|= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT
|
398 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT
|
399 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT
;
401 dw3
|= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT
|
402 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT
|
403 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT
;
406 /* setup->point_aa_enable is ignored */
407 if (!point
->programmable_width
) {
408 dw3
|= GEN7_SF_DW3_USE_POINT_WIDTH
|
409 point_width
<< GEN7_SF_DW3_POINT_WIDTH__SHIFT
;
412 STATIC_ASSERT(ARRAY_SIZE(rs
->sf
) >= 3);
417 STATIC_ASSERT(ARRAY_SIZE(rs
->raster
) >= 4);
419 rs
->raster
[1] = fui(params
->depth_offset_const
);
420 rs
->raster
[2] = fui(params
->depth_offset_scale
);
421 rs
->raster
[3] = fui(params
->depth_offset_clamp
);
423 rs
->line_aa_enable
= line
->aa_enable
;
424 rs
->line_giq_enable
= line
->giq_enable
;
430 raster_set_gen8_3DSTATE_SF(struct ilo_state_raster
*rs
,
431 const struct ilo_dev
*dev
,
432 const struct ilo_state_raster_info
*info
,
433 const struct ilo_state_raster_line_info
*line
)
435 const struct ilo_state_raster_clip_info
*clip
= &info
->clip
;
436 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
437 const struct ilo_state_raster_point_info
*point
= &info
->point
;
438 const struct ilo_state_raster_params_info
*params
= &info
->params
;
439 const int line_width
= get_gen6_line_width(dev
, params
->line_width
,
440 line
->aa_enable
, line
->giq_enable
);
441 const int point_width
= get_gen6_point_width(dev
, params
->point_width
);
442 uint32_t dw1
, dw2
, dw3
;
444 ILO_DEV_ASSERT(dev
, 8, 8);
448 if (clip
->stats_enable
&& clip
->clip_enable
)
449 dw1
|= GEN7_SF_DW1_STATISTICS
;
451 if (setup
->viewport_transform
)
452 dw1
|= GEN7_SF_DW1_VIEWPORT_TRANSFORM
;
454 dw2
= line_width
<< GEN7_SF_DW2_LINE_WIDTH__SHIFT
|
455 GEN7_SF_DW2_AA_LINE_CAP_1_0
;
457 dw3
= GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE
|
458 GEN7_SF_DW3_SUBPIXEL_8BITS
;
460 /* this has no effect when line_width != 0 */
461 if (line
->giq_last_pixel
)
462 dw3
|= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE
;
464 if (setup
->first_vertex_provoking
) {
465 dw3
|= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT
|
466 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT
|
467 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT
;
469 dw3
|= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT
|
470 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT
|
471 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT
;
474 if (!point
->programmable_width
) {
475 dw3
|= GEN7_SF_DW3_USE_POINT_WIDTH
|
476 point_width
<< GEN7_SF_DW3_POINT_WIDTH__SHIFT
;
479 STATIC_ASSERT(ARRAY_SIZE(rs
->sf
) >= 3);
488 raster_set_gen8_3DSTATE_RASTER(struct ilo_state_raster
*rs
,
489 const struct ilo_dev
*dev
,
490 const struct ilo_state_raster_info
*info
,
491 const struct ilo_state_raster_line_info
*line
)
493 const struct ilo_state_raster_clip_info
*clip
= &info
->clip
;
494 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
495 const struct ilo_state_raster_point_info
*point
= &info
->point
;
496 const struct ilo_state_raster_tri_info
*tri
= &info
->tri
;
497 const struct ilo_state_raster_params_info
*params
= &info
->params
;
500 ILO_DEV_ASSERT(dev
, 8, 8);
502 if (!raster_validate_gen8_raster(dev
, info
))
505 dw1
= tri
->front_winding
<< GEN8_RASTER_DW1_FRONT_WINDING__SHIFT
|
506 tri
->cull_mode
<< GEN8_RASTER_DW1_CULL_MODE__SHIFT
|
507 tri
->fill_mode_front
<< GEN8_RASTER_DW1_FILL_MODE_FRONT__SHIFT
|
508 tri
->fill_mode_back
<< GEN8_RASTER_DW1_FILL_MODE_BACK__SHIFT
;
510 if (point
->aa_enable
)
511 dw1
|= GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE
;
513 /* where should line_msaa_enable be set? */
514 if (setup
->msaa_enable
)
515 dw1
|= GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE
;
517 if (tri
->depth_offset_solid
)
518 dw1
|= GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID
;
519 if (tri
->depth_offset_wireframe
)
520 dw1
|= GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME
;
521 if (tri
->depth_offset_point
)
522 dw1
|= GEN8_RASTER_DW1_DEPTH_OFFSET_POINT
;
525 dw1
|= GEN8_RASTER_DW1_AA_LINE_ENABLE
;
527 if (setup
->scissor_enable
)
528 dw1
|= GEN8_RASTER_DW1_SCISSOR_ENABLE
;
530 if (ilo_dev_gen(dev
) >= ILO_GEN(9)) {
531 if (clip
->z_far_enable
)
532 dw1
|= GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE
;
533 if (clip
->z_near_enable
)
534 dw1
|= GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE
;
536 if (clip
->z_near_enable
)
537 dw1
|= GEN8_RASTER_DW1_Z_TEST_ENABLE
;
540 STATIC_ASSERT(ARRAY_SIZE(rs
->raster
) >= 4);
542 rs
->raster
[1] = fui(params
->depth_offset_const
);
543 rs
->raster
[2] = fui(params
->depth_offset_scale
);
544 rs
->raster
[3] = fui(params
->depth_offset_clamp
);
546 rs
->line_aa_enable
= line
->aa_enable
;
547 rs
->line_giq_enable
= line
->giq_enable
;
552 static enum gen_sample_count
553 get_gen6_sample_count(const struct ilo_dev
*dev
, uint8_t sample_count
)
555 enum gen_sample_count c
;
558 ILO_DEV_ASSERT(dev
, 6, 8);
560 switch (sample_count
) {
562 c
= GEN6_NUMSAMPLES_1
;
563 min_gen
= ILO_GEN(6);
566 c
= GEN8_NUMSAMPLES_2
;
567 min_gen
= ILO_GEN(8);
570 c
= GEN6_NUMSAMPLES_4
;
571 min_gen
= ILO_GEN(6);
574 c
= GEN7_NUMSAMPLES_8
;
575 min_gen
= ILO_GEN(7);
578 c
= GEN8_NUMSAMPLES_16
;
579 min_gen
= ILO_GEN(8);
582 assert(!"unexpected sample count");
583 c
= GEN6_NUMSAMPLES_1
;
587 assert(ilo_dev_gen(dev
) >= min_gen
);
593 raster_set_gen8_3DSTATE_MULTISAMPLE(struct ilo_state_raster
*rs
,
594 const struct ilo_dev
*dev
,
595 const struct ilo_state_raster_info
*info
)
597 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
598 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
599 const enum gen_sample_count count
=
600 get_gen6_sample_count(dev
, scan
->sample_count
);
603 ILO_DEV_ASSERT(dev
, 6, 8);
606 * From the Sandy Bridge PRM, volume 2 part 1, page 307:
608 * "Setting Multisample Rasterization Mode to MSRASTMODE_xxx_PATTERN
609 * when Number of Multisamples == NUMSAMPLES_1 is UNDEFINED."
611 if (setup
->msaa_enable
)
612 assert(scan
->sample_count
> 1);
614 dw1
= scan
->pixloc
<< GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT
|
615 count
<< GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__SHIFT
;
617 STATIC_ASSERT(ARRAY_SIZE(rs
->sample
) >= 1);
624 raster_set_gen6_3DSTATE_SAMPLE_MASK(struct ilo_state_raster
*rs
,
625 const struct ilo_dev
*dev
,
626 const struct ilo_state_raster_info
*info
)
628 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
630 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
632 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
633 * (Sample Mask) must be zero.
635 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
638 const uint32_t mask
= (1 << scan
->sample_count
) - 1;
641 ILO_DEV_ASSERT(dev
, 6, 8);
643 dw1
= (scan
->sample_mask
& mask
) << GEN6_SAMPLE_MASK_DW1_VAL__SHIFT
;
645 STATIC_ASSERT(ARRAY_SIZE(rs
->sample
) >= 2);
652 raster_validate_gen6_wm(const struct ilo_dev
*dev
,
653 const struct ilo_state_raster_info
*info
)
655 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
657 ILO_DEV_ASSERT(dev
, 6, 8);
659 if (ilo_dev_gen(dev
) == ILO_GEN(6))
660 assert(scan
->earlyz_control
== GEN7_EDSC_NORMAL
);
663 * From the Sandy Bridge PRM, volume 2 part 1, page 272:
665 * "This bit (Statistics Enable) must be disabled if either of these
666 * bits is set: Depth Buffer Clear , Hierarchical Depth Buffer Resolve
667 * Enable or Depth Buffer Resolve Enable."
669 if (scan
->earlyz_op
!= ILO_STATE_RASTER_EARLYZ_NORMAL
)
670 assert(!scan
->stats_enable
);
673 * From the Sandy Bridge PRM, volume 2 part 1, page 273:
675 * "If this field (Depth Buffer Resolve Enable) is enabled, the Depth
676 * Buffer Clear and Hierarchical Depth Buffer Resolve Enable fields
677 * must both be disabled."
679 * "If this field (Hierarchical Depth Buffer Resolve Enable) is
680 * enabled, the Depth Buffer Clear and Depth Buffer Resolve Enable
681 * fields must both be disabled."
683 * This is guaranteed.
687 * From the Sandy Bridge PRM, volume 2 part 1, page 314-315:
689 * "Stencil buffer clear can be performed at the same time by enabling
690 * Stencil Buffer Write Enable."
692 * "Note also that stencil buffer clear can be performed without depth
695 if (scan
->earlyz_stencil_clear
) {
696 assert(scan
->earlyz_op
== ILO_STATE_RASTER_EARLYZ_NORMAL
||
697 scan
->earlyz_op
== ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR
);
704 raster_set_gen6_3dstate_wm(struct ilo_state_raster
*rs
,
705 const struct ilo_dev
*dev
,
706 const struct ilo_state_raster_info
*info
,
707 const struct ilo_state_raster_line_info
*line
)
709 const struct ilo_state_raster_tri_info
*tri
= &info
->tri
;
710 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
711 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
712 const enum gen_msrast_mode msrast
=
713 raster_setup_get_gen6_msrast_mode(dev
, setup
);
714 /* only scan conversion states are set, as in Gen8+ */
715 uint32_t dw4
, dw5
, dw6
;
717 ILO_DEV_ASSERT(dev
, 6, 6);
719 if (!raster_validate_gen6_wm(dev
, info
))
724 if (scan
->stats_enable
)
725 dw4
|= GEN6_WM_DW4_STATISTICS
;
727 switch (scan
->earlyz_op
) {
728 case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR
:
729 dw4
|= GEN6_WM_DW4_DEPTH_CLEAR
;
731 case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE
:
732 dw4
|= GEN6_WM_DW4_DEPTH_RESOLVE
;
734 case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE
:
735 dw4
|= GEN6_WM_DW4_HIZ_RESOLVE
;
738 if (scan
->earlyz_stencil_clear
)
739 dw4
|= GEN6_WM_DW4_DEPTH_CLEAR
;
743 dw5
= GEN6_WM_DW5_AA_LINE_CAP_1_0
| /* same as in 3DSTATE_SF */
744 GEN6_WM_DW5_AA_LINE_WIDTH_2_0
;
746 if (tri
->poly_stipple_enable
)
747 dw5
|= GEN6_WM_DW5_POLY_STIPPLE_ENABLE
;
748 if (line
->stipple_enable
)
749 dw5
|= GEN6_WM_DW5_LINE_STIPPLE_ENABLE
;
751 dw6
= scan
->zw_interp
<< GEN6_WM_DW6_ZW_INTERP__SHIFT
|
752 scan
->barycentric_interps
<< GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT
|
753 GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT
|
754 msrast
<< GEN6_WM_DW6_MSRASTMODE__SHIFT
;
756 STATIC_ASSERT(ARRAY_SIZE(rs
->wm
) >= 3);
765 raster_set_gen8_3DSTATE_WM(struct ilo_state_raster
*rs
,
766 const struct ilo_dev
*dev
,
767 const struct ilo_state_raster_info
*info
,
768 const struct ilo_state_raster_line_info
*line
)
770 const struct ilo_state_raster_tri_info
*tri
= &info
->tri
;
771 const struct ilo_state_raster_setup_info
*setup
= &info
->setup
;
772 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
773 const enum gen_msrast_mode msrast
=
774 raster_setup_get_gen6_msrast_mode(dev
, setup
);
777 ILO_DEV_ASSERT(dev
, 7, 8);
779 if (!raster_validate_gen6_wm(dev
, info
))
782 dw1
= scan
->earlyz_control
<< GEN7_WM_DW1_EDSC__SHIFT
|
783 scan
->zw_interp
<< GEN7_WM_DW1_ZW_INTERP__SHIFT
|
784 scan
->barycentric_interps
<< GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT
|
785 GEN7_WM_DW1_AA_LINE_CAP_1_0
| /* same as in 3DSTATE_SF */
786 GEN7_WM_DW1_AA_LINE_WIDTH_2_0
|
787 GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT
;
789 if (scan
->stats_enable
)
790 dw1
|= GEN7_WM_DW1_STATISTICS
;
792 if (ilo_dev_gen(dev
) < ILO_GEN(8)) {
793 switch (scan
->earlyz_op
) {
794 case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR
:
795 dw1
|= GEN7_WM_DW1_DEPTH_CLEAR
;
797 case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE
:
798 dw1
|= GEN7_WM_DW1_DEPTH_RESOLVE
;
800 case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE
:
801 dw1
|= GEN7_WM_DW1_HIZ_RESOLVE
;
804 if (scan
->earlyz_stencil_clear
)
805 dw1
|= GEN7_WM_DW1_DEPTH_CLEAR
;
810 if (tri
->poly_stipple_enable
)
811 dw1
|= GEN7_WM_DW1_POLY_STIPPLE_ENABLE
;
812 if (line
->stipple_enable
)
813 dw1
|= GEN7_WM_DW1_LINE_STIPPLE_ENABLE
;
815 if (ilo_dev_gen(dev
) < ILO_GEN(8))
816 dw1
|= msrast
<< GEN7_WM_DW1_MSRASTMODE__SHIFT
;
818 STATIC_ASSERT(ARRAY_SIZE(rs
->wm
) >= 1);
825 raster_set_gen8_3dstate_wm_hz_op(struct ilo_state_raster
*rs
,
826 const struct ilo_dev
*dev
,
827 const struct ilo_state_raster_info
*info
)
829 const struct ilo_state_raster_scan_info
*scan
= &info
->scan
;
830 const enum gen_sample_count count
=
831 get_gen6_sample_count(dev
, scan
->sample_count
);
832 const uint32_t mask
= (1 << scan
->sample_count
) - 1;
835 ILO_DEV_ASSERT(dev
, 8, 8);
837 dw1
= count
<< GEN8_WM_HZ_DW1_NUM_SAMPLES__SHIFT
;
839 if (scan
->earlyz_stencil_clear
)
840 dw1
|= GEN8_WM_HZ_DW1_STENCIL_CLEAR
;
842 switch (scan
->earlyz_op
) {
843 case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR
:
844 dw1
|= GEN8_WM_HZ_DW1_DEPTH_CLEAR
;
846 case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE
:
847 dw1
|= GEN8_WM_HZ_DW1_DEPTH_RESOLVE
;
849 case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE
:
850 dw1
|= GEN8_WM_HZ_DW1_HIZ_RESOLVE
;
856 dw4
= (scan
->sample_mask
& mask
) << GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT
;
858 STATIC_ASSERT(ARRAY_SIZE(rs
->wm
) >= 3);
866 ilo_state_raster_init(struct ilo_state_raster
*rs
,
867 const struct ilo_dev
*dev
,
868 const struct ilo_state_raster_info
*info
)
870 assert(ilo_is_zeroed(rs
, sizeof(*rs
)));
871 return ilo_state_raster_set_info(rs
, dev
, info
);
875 ilo_state_raster_init_for_rectlist(struct ilo_state_raster
*rs
,
876 const struct ilo_dev
*dev
,
877 uint8_t sample_count
,
878 enum ilo_state_raster_earlyz_op earlyz_op
,
879 bool earlyz_stencil_clear
)
881 struct ilo_state_raster_info info
;
883 memset(&info
, 0, sizeof(info
));
885 info
.clip
.viewport_count
= 1;
886 info
.setup
.cv_is_rectangle
= true;
887 info
.setup
.msaa_enable
= (sample_count
> 1);
888 info
.scan
.sample_count
= sample_count
;
889 info
.scan
.sample_mask
= ~0u;
890 info
.scan
.earlyz_op
= earlyz_op
;
891 info
.scan
.earlyz_stencil_clear
= earlyz_stencil_clear
;
893 return ilo_state_raster_init(rs
, dev
, &info
);
897 ilo_state_raster_set_info(struct ilo_state_raster
*rs
,
898 const struct ilo_dev
*dev
,
899 const struct ilo_state_raster_info
*info
)
901 struct ilo_state_raster_line_info line
;
904 ret
&= raster_set_gen6_3DSTATE_CLIP(rs
, dev
, info
);
906 raster_get_gen6_effective_line(dev
, info
, &line
);
908 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
909 ret
&= raster_set_gen8_3DSTATE_SF(rs
, dev
, info
, &line
);
910 ret
&= raster_set_gen8_3DSTATE_RASTER(rs
, dev
, info
, &line
);
912 ret
&= raster_set_gen7_3DSTATE_SF(rs
, dev
, info
, &line
);
915 ret
&= raster_set_gen8_3DSTATE_MULTISAMPLE(rs
, dev
, info
);
916 ret
&= raster_set_gen6_3DSTATE_SAMPLE_MASK(rs
, dev
, info
);
918 if (ilo_dev_gen(dev
) >= ILO_GEN(7)) {
919 ret
&= raster_set_gen8_3DSTATE_WM(rs
, dev
, info
, &line
);
921 if (ilo_dev_gen(dev
) >= ILO_GEN(8))
922 ret
&= raster_set_gen8_3dstate_wm_hz_op(rs
, dev
, info
);
924 ret
&= raster_set_gen6_3dstate_wm(rs
, dev
, info
, &line
);
933 ilo_state_raster_set_params(struct ilo_state_raster
*rs
,
934 const struct ilo_dev
*dev
,
935 const struct ilo_state_raster_params_info
*params
)
937 const bool line_aa_enable
= (rs
->line_aa_enable
&&
938 raster_params_is_gen6_line_aa_allowed(dev
, params
));
939 const int line_width
= get_gen6_line_width(dev
, params
->line_width
,
940 line_aa_enable
, rs
->line_giq_enable
);
942 ILO_DEV_ASSERT(dev
, 6, 8);
944 /* modify line AA enable */
945 if (rs
->line_aa_enable
) {
946 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
948 rs
->raster
[0] |= GEN8_RASTER_DW1_AA_LINE_ENABLE
;
950 rs
->raster
[0] &= ~GEN8_RASTER_DW1_AA_LINE_ENABLE
;
953 rs
->sf
[1] |= GEN7_SF_DW2_AA_LINE_ENABLE
;
955 rs
->sf
[1] &= ~GEN7_SF_DW2_AA_LINE_ENABLE
;
959 /* modify line width */
960 rs
->sf
[1] = (rs
->sf
[1] & ~GEN7_SF_DW2_LINE_WIDTH__MASK
) |
961 line_width
<< GEN7_SF_DW2_LINE_WIDTH__SHIFT
;
963 /* modify point width */
964 if (rs
->sf
[2] & GEN7_SF_DW3_USE_POINT_WIDTH
) {
965 const int point_width
= get_gen6_point_width(dev
, params
->point_width
);
967 rs
->sf
[2] = (rs
->sf
[2] & ~GEN7_SF_DW3_POINT_WIDTH__MASK
) |
968 point_width
<< GEN7_SF_DW3_POINT_WIDTH__SHIFT
;
971 /* modify depth offset */
972 rs
->raster
[1] = fui(params
->depth_offset_const
);
973 rs
->raster
[2] = fui(params
->depth_offset_scale
);
974 rs
->raster
[3] = fui(params
->depth_offset_clamp
);
980 ilo_state_raster_full_delta(const struct ilo_state_raster
*rs
,
981 const struct ilo_dev
*dev
,
982 struct ilo_state_raster_delta
*delta
)
984 delta
->dirty
= ILO_STATE_RASTER_3DSTATE_CLIP
|
985 ILO_STATE_RASTER_3DSTATE_SF
|
986 ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
|
987 ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
|
988 ILO_STATE_RASTER_3DSTATE_WM
|
989 ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS
;
991 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
992 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_RASTER
|
993 ILO_STATE_RASTER_3DSTATE_WM_HZ_OP
;
998 ilo_state_raster_get_delta(const struct ilo_state_raster
*rs
,
999 const struct ilo_dev
*dev
,
1000 const struct ilo_state_raster
*old
,
1001 struct ilo_state_raster_delta
*delta
)
1005 if (memcmp(rs
->clip
, old
->clip
, sizeof(rs
->clip
)))
1006 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_CLIP
;
1008 if (memcmp(rs
->sf
, old
->sf
, sizeof(rs
->sf
)))
1009 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_SF
;
1011 if (memcmp(rs
->raster
, old
->raster
, sizeof(rs
->raster
))) {
1012 if (ilo_dev_gen(dev
) >= ILO_GEN(8))
1013 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_RASTER
;
1015 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_SF
;
1018 if (memcmp(rs
->sample
, old
->sample
, sizeof(rs
->sample
))) {
1019 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
|
1020 ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
;
1023 if (memcmp(rs
->wm
, old
->wm
, sizeof(rs
->wm
))) {
1024 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_WM
;
1026 if (ilo_dev_gen(dev
) >= ILO_GEN(8))
1027 delta
->dirty
|= ILO_STATE_RASTER_3DSTATE_WM_HZ_OP
;