2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2015 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "ilo_debug.h"
29 #include "ilo_buffer.h"
30 #include "ilo_image.h"
31 #include "ilo_state_surface.h"
34 surface_set_gen6_null_SURFACE_STATE(struct ilo_state_surface
*surf
,
35 const struct ilo_dev
*dev
)
39 ILO_DEV_ASSERT(dev
, 6, 6);
42 * From the Sandy Bridge PRM, volume 4 part 1, page 71:
44 * "All of the remaining fields in surface state are ignored for null
45 * surfaces, with the following exceptions:
47 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
48 * depth buffer's corresponding state for all render target
49 * surfaces, including null.
50 * - Surface Format must be R8G8B8A8_UNORM."
52 * From the Sandy Bridge PRM, volume 4 part 1, page 82:
54 * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must
57 * Note that we ignore the first exception for all surface types.
59 dw0
= GEN6_SURFTYPE_NULL
<< GEN6_SURFACE_DW0_TYPE__SHIFT
|
60 GEN6_FORMAT_R8G8B8A8_UNORM
<< GEN6_SURFACE_DW0_FORMAT__SHIFT
;
61 dw3
= GEN6_TILING_X
<< GEN6_SURFACE_DW3_TILING__SHIFT
;
63 STATIC_ASSERT(ARRAY_SIZE(surf
->surface
) >= 6);
64 surf
->surface
[0] = dw0
;
67 surf
->surface
[3] = dw3
;
75 surface_set_gen7_null_SURFACE_STATE(struct ilo_state_surface
*surf
,
76 const struct ilo_dev
*dev
)
80 ILO_DEV_ASSERT(dev
, 7, 8);
82 dw0
= GEN6_SURFTYPE_NULL
<< GEN7_SURFACE_DW0_TYPE__SHIFT
|
83 GEN6_FORMAT_R8G8B8A8_UNORM
<< GEN7_SURFACE_DW0_FORMAT__SHIFT
;
84 if (ilo_dev_gen(dev
) >= ILO_GEN(8))
85 dw0
|= GEN6_TILING_X
<< GEN8_SURFACE_DW0_TILING__SHIFT
;
87 dw0
|= GEN6_TILING_X
<< GEN7_SURFACE_DW0_TILING__SHIFT
;
89 STATIC_ASSERT(ARRAY_SIZE(surf
->surface
) >= 13);
90 surf
->surface
[0] = dw0
;
91 memset(&surf
->surface
[1], 0, sizeof(uint32_t) *
92 (((ilo_dev_gen(dev
) >= ILO_GEN(8)) ? 13 : 8) - 1));
98 surface_validate_gen6_buffer(const struct ilo_dev
*dev
,
99 const struct ilo_state_surface_buffer_info
*info
)
101 ILO_DEV_ASSERT(dev
, 6, 8);
103 /* SVB writes are Gen6-only */
104 if (ilo_dev_gen(dev
) >= ILO_GEN(7))
105 assert(info
->access
!= ILO_STATE_SURFACE_ACCESS_DP_SVB
);
107 if (info
->offset
+ info
->size
> info
->buf
->bo_size
) {
108 ilo_warn("invalid buffer range\n");
113 * From the Sandy Bridge PRM, volume 4 part 1, page 81:
115 * "For surfaces of type SURFTYPE_BUFFER: [0,2047] -> [1B, 2048B]
116 * For surfaces of type SURFTYPE_STRBUF: [0,2047] -> [1B, 2048B]"
118 if (!info
->struct_size
|| info
->struct_size
> 2048) {
119 ilo_warn("invalid buffer struct size\n");
124 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
126 * "The Base Address for linear render target surfaces and surfaces
127 * accessed with the typed surface read/write data port messages must
128 * be element-size aligned, for non-YUV surface formats, or a multiple
129 * of 2 element-sizes for YUV surface formats. Other linear surfaces
130 * have no alignment requirements (byte alignment is sufficient)."
132 * "Certain message types used to access surfaces have more stringent
133 * alignment requirements. Please refer to the specific message
134 * documentation for additional restrictions."
136 * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, and 237:
138 * "the surface base address must be OWord aligned"
140 * for OWord Block Read/Write, Unaligned OWord Block Read, and OWord Dual
143 * From the Ivy Bridge PRM, volume 4 part 1, page 246 and 249:
145 * "The surface base address must be DWord aligned"
147 * for DWord Scattered Read/Write and Byte Scattered Read/Write.
149 * We have to rely on users to correctly set info->struct_size here. DWord
150 * Scattered Read/Write has conflicting pitch and alignment, but we do not
151 * use them yet so we are fine.
153 * It is unclear if sampling engine surfaces require aligned offsets.
155 if (info
->access
!= ILO_STATE_SURFACE_ACCESS_DP_SVB
) {
156 assert(info
->struct_size
% info
->format_size
== 0);
158 if (info
->offset
% info
->struct_size
) {
159 ilo_warn("bad buffer offset\n");
164 if (info
->format
== GEN6_FORMAT_RAW
) {
166 * From the Sandy Bridge PRM, volume 4 part 1, page 97:
168 * ""RAW" is supported only with buffers and structured buffers
169 * accessed via the untyped surface read/write and untyped atomic
170 * operation messages, which do not have a column in the table."
172 * We do not have a specific access mode for untyped messages.
174 assert(info
->access
== ILO_STATE_SURFACE_ACCESS_DP_UNTYPED
);
177 * Nothing is said about Untyped* messages, but I guess they require the
178 * base address to be DWord aligned.
180 if (info
->offset
% 4) {
181 ilo_warn("bad RAW buffer offset\n");
185 if (info
->struct_size
> 1) {
186 /* no STRBUF on Gen6 */
187 if (ilo_dev_gen(dev
) == ILO_GEN(6)) {
188 ilo_warn("no STRBUF support\n");
193 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
195 * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the
196 * pitch must be a multiple of 4 bytes."
198 if (info
->struct_size
% 4) {
199 ilo_warn("bad STRBUF pitch\n");
209 surface_get_gen6_buffer_struct_count(const struct ilo_dev
*dev
,
210 const struct ilo_state_surface_buffer_info
*info
,
213 uint32_t max_struct
, c
;
215 ILO_DEV_ASSERT(dev
, 6, 8);
217 c
= info
->size
/ info
->struct_size
;
218 if (info
->access
== ILO_STATE_SURFACE_ACCESS_DP_SVB
&&
219 info
->format_size
< info
->size
- info
->struct_size
* c
)
223 * From the Sandy Bridge PRM, volume 4 part 1, page 77:
225 * "For buffer surfaces, the number of entries in the buffer ranges
228 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
230 * "For typed buffer and structured buffer surfaces, the number of
231 * entries in the buffer ranges from 1 to 2^27. For raw buffer
232 * surfaces, the number of entries in the buffer is the number of
233 * bytes which can range from 1 to 2^30."
235 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
237 * For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
238 * 11 if the Surface Format is RAW (the size of the buffer must be a
239 * multiple of 4 bytes)."
241 max_struct
= 1 << 27;
242 if (info
->format
== GEN6_FORMAT_RAW
&& info
->struct_size
== 1) {
243 if (ilo_dev_gen(dev
) >= ILO_GEN(7))
244 max_struct
= 1 << 30;
249 if (!c
|| c
> max_struct
) {
250 ilo_warn("too many or zero buffer structs\n");
260 surface_set_gen6_buffer_SURFACE_STATE(struct ilo_state_surface
*surf
,
261 const struct ilo_dev
*dev
,
262 const struct ilo_state_surface_buffer_info
*info
)
264 uint32_t dw0
, dw1
, dw2
, dw3
;
265 uint32_t struct_count
;
266 int width
, height
, depth
;
268 ILO_DEV_ASSERT(dev
, 6, 6);
270 if (!surface_validate_gen6_buffer(dev
, info
) ||
271 !surface_get_gen6_buffer_struct_count(dev
, info
, &struct_count
))
275 width
= (struct_count
& 0x0000007f);
277 height
= (struct_count
& 0x000fff80) >> 7;
279 depth
= (struct_count
& 0x07f00000) >> 20;
281 dw0
= GEN6_SURFTYPE_BUFFER
<< GEN6_SURFACE_DW0_TYPE__SHIFT
|
282 info
->format
<< GEN6_SURFACE_DW0_FORMAT__SHIFT
;
284 dw2
= height
<< GEN6_SURFACE_DW2_HEIGHT__SHIFT
|
285 width
<< GEN6_SURFACE_DW2_WIDTH__SHIFT
;
286 dw3
= depth
<< GEN6_SURFACE_DW3_DEPTH__SHIFT
|
287 (info
->struct_size
- 1) << GEN6_SURFACE_DW3_PITCH__SHIFT
;
289 STATIC_ASSERT(ARRAY_SIZE(surf
->surface
) >= 6);
290 surf
->surface
[0] = dw0
;
291 surf
->surface
[1] = dw1
;
292 surf
->surface
[2] = dw2
;
293 surf
->surface
[3] = dw3
;
294 surf
->surface
[4] = 0;
295 surf
->surface
[5] = 0;
297 surf
->type
= GEN6_SURFTYPE_BUFFER
;
305 surface_set_gen7_buffer_SURFACE_STATE(struct ilo_state_surface
*surf
,
306 const struct ilo_dev
*dev
,
307 const struct ilo_state_surface_buffer_info
*info
)
309 uint32_t dw0
, dw1
, dw2
, dw3
, dw7
;
310 enum gen_surface_type type
;
311 uint32_t struct_count
;
312 int width
, height
, depth
;
314 ILO_DEV_ASSERT(dev
, 7, 8);
316 if (!surface_validate_gen6_buffer(dev
, info
) ||
317 !surface_get_gen6_buffer_struct_count(dev
, info
, &struct_count
))
320 type
= (info
->format
== GEN6_FORMAT_RAW
&& info
->struct_size
> 1) ?
321 GEN7_SURFTYPE_STRBUF
: GEN6_SURFTYPE_BUFFER
;
324 width
= (struct_count
& 0x0000007f);
326 height
= (struct_count
& 0x001fff80) >> 7;
328 depth
= (struct_count
& 0x7fe00000) >> 21;
330 dw0
= type
<< GEN7_SURFACE_DW0_TYPE__SHIFT
|
331 info
->format
<< GEN7_SURFACE_DW0_FORMAT__SHIFT
;
332 dw1
= (ilo_dev_gen(dev
) >= ILO_GEN(8)) ? 0 : info
->offset
;
333 dw2
= GEN_SHIFT32(height
, GEN7_SURFACE_DW2_HEIGHT
) |
334 GEN_SHIFT32(width
, GEN7_SURFACE_DW2_WIDTH
);
335 dw3
= GEN_SHIFT32(depth
, GEN7_SURFACE_DW3_DEPTH
) |
336 GEN_SHIFT32(info
->struct_size
- 1, GEN7_SURFACE_DW3_PITCH
);
339 if (ilo_dev_gen(dev
) >= ILO_GEN(7.5)) {
340 dw7
|= GEN_SHIFT32(GEN75_SCS_RED
, GEN75_SURFACE_DW7_SCS_R
) |
341 GEN_SHIFT32(GEN75_SCS_GREEN
, GEN75_SURFACE_DW7_SCS_G
) |
342 GEN_SHIFT32(GEN75_SCS_BLUE
, GEN75_SURFACE_DW7_SCS_B
) |
343 GEN_SHIFT32(GEN75_SCS_ALPHA
, GEN75_SURFACE_DW7_SCS_A
);
346 STATIC_ASSERT(ARRAY_SIZE(surf
->surface
) >= 13);
347 surf
->surface
[0] = dw0
;
348 surf
->surface
[1] = dw1
;
349 surf
->surface
[2] = dw2
;
350 surf
->surface
[3] = dw3
;
351 surf
->surface
[4] = 0;
352 surf
->surface
[5] = 0;
353 surf
->surface
[6] = 0;
354 surf
->surface
[7] = dw7
;
355 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
356 surf
->surface
[8] = info
->offset
;
357 surf
->surface
[9] = 0;
358 surf
->surface
[10] = 0;
359 surf
->surface
[11] = 0;
360 surf
->surface
[12] = 0;
370 static enum gen_surface_type
371 get_gen6_surface_type(const struct ilo_dev
*dev
, const struct ilo_image
*img
)
373 ILO_DEV_ASSERT(dev
, 6, 8);
375 switch (img
->target
) {
376 case PIPE_TEXTURE_1D
:
377 case PIPE_TEXTURE_1D_ARRAY
:
378 return GEN6_SURFTYPE_1D
;
379 case PIPE_TEXTURE_2D
:
380 case PIPE_TEXTURE_CUBE
:
381 case PIPE_TEXTURE_RECT
:
382 case PIPE_TEXTURE_2D_ARRAY
:
383 case PIPE_TEXTURE_CUBE_ARRAY
:
384 return GEN6_SURFTYPE_2D
;
385 case PIPE_TEXTURE_3D
:
386 return GEN6_SURFTYPE_3D
;
388 assert(!"unknown texture target");
389 return GEN6_SURFTYPE_NULL
;
394 surface_validate_gen6_image(const struct ilo_dev
*dev
,
395 const struct ilo_state_surface_image_info
*info
)
397 ILO_DEV_ASSERT(dev
, 6, 8);
399 switch (info
->access
) {
400 case ILO_STATE_SURFACE_ACCESS_SAMPLER
:
401 case ILO_STATE_SURFACE_ACCESS_DP_RENDER
:
403 case ILO_STATE_SURFACE_ACCESS_DP_TYPED
:
404 assert(ilo_dev_gen(dev
) >= ILO_GEN(7));
407 assert(!"unsupported surface access");
412 * From the Sandy Bridge PRM, volume 4 part 1, page 78:
414 * "For surface types other than SURFTYPE_BUFFER, the Width specified
415 * by this field must be less than or equal to the surface pitch
416 * (specified in bytes via the Surface Pitch field)."
418 assert(info
->img
->bo_stride
&& info
->img
->bo_stride
<= 512 * 1024 &&
419 info
->img
->width0
<= info
->img
->bo_stride
);
421 if (info
->is_cube_map
) {
422 assert(get_gen6_surface_type(dev
, info
->img
) == GEN6_SURFTYPE_2D
);
425 * From the Sandy Bridge PRM, volume 4 part 1, page 78:
427 * "For cube maps, Width must be set equal to the Height."
429 assert(info
->img
->width0
== info
->img
->height0
);
433 * From the Sandy Bridge PRM, volume 4 part 1, page 72:
435 * "Tile Walk TILEWALK_YMAJOR is UNDEFINED for render target formats
436 * that have 128 bits-per-element (BPE)."
438 * "If Number of Multisamples is set to a value other than
439 * MULTISAMPLECOUNT_1, this field cannot be set to the following
442 * - any format with greater than 64 bits per element
443 * - any compressed texture format (BC*)
444 * - any YCRCB* format"
446 * From the Ivy Bridge PRM, volume 4 part 1, page 63:
448 * If Number of Multisamples is set to a value other than
449 * MULTISAMPLECOUNT_1, this field cannot be set to the following
450 * formats: any format with greater than 64 bits per element, if
451 * Number of Multisamples is MULTISAMPLECOUNT_8, any compressed
452 * texture format (BC*), and any YCRCB* format.
457 if (ilo_dev_gen(dev
) < ILO_GEN(8) && info
->img
->tiling
== GEN8_TILING_W
) {
458 ilo_warn("tiling W is not supported\n");
466 get_gen6_max_extent(const struct ilo_dev
*dev
,
467 const struct ilo_image
*img
,
468 uint16_t *max_w
, uint16_t *max_h
)
470 const uint16_t max_size
= (ilo_dev_gen(dev
) >= ILO_GEN(7)) ? 16384 : 8192;
472 ILO_DEV_ASSERT(dev
, 6, 8);
474 switch (get_gen6_surface_type(dev
, img
)) {
475 case GEN6_SURFTYPE_1D
:
479 case GEN6_SURFTYPE_2D
:
483 case GEN6_SURFTYPE_3D
:
488 assert(!"invalid surface type");
496 surface_get_gen6_image_extent(const struct ilo_dev
*dev
,
497 const struct ilo_state_surface_image_info
*info
,
498 uint16_t *width
, uint16_t *height
)
500 uint16_t w
, h
, max_w
, max_h
;
502 ILO_DEV_ASSERT(dev
, 6, 8);
504 w
= info
->img
->width0
;
505 h
= info
->img
->height0
;
507 get_gen6_max_extent(dev
, info
->img
, &max_w
, &max_h
);
508 assert(w
&& h
&& w
<= max_w
&& h
<= max_h
);
517 surface_get_gen6_image_slices(const struct ilo_dev
*dev
,
518 const struct ilo_state_surface_image_info
*info
,
519 uint16_t *depth
, uint16_t *min_array_elem
,
520 uint16_t *rt_view_extent
)
522 uint16_t max_slice
, d
;
524 ILO_DEV_ASSERT(dev
, 6, 8);
527 * From the Ivy Bridge PRM, volume 4 part 1, page 63:
529 * "If this field (Surface Array) is enabled, the Surface Type must be
530 * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
531 * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
532 * SURFTYPE_CUBE, the Depth field must be set to zero."
534 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
536 * "This field (Depth) specifies the total number of levels for a
537 * volume texture or the number of array elements allowed to be
538 * accessed starting at the Minimum Array Element for arrayed
539 * surfaces. If the volume texture is MIP-mapped, this field
540 * specifies the depth of the base MIP level."
542 * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of this
543 * field is [0,340], indicating the number of cube array elements
544 * (equal to the number of underlying 2D array elements divided by 6).
545 * For other surfaces, this field must be zero."
547 * "Errata: For SURFTYPE_CUBE sampling engine surfaces, the range of
548 * this field is limited to [0,85].
550 * Errata: If Surface Array is enabled, and Depth is between 1024 and
551 * 2047, an incorrect array slice may be accessed if the requested
552 * array index in the message is greater than or equal to 4096."
554 * The errata are for Gen7-specific, and they limit the number of useable
555 * layers to (86 * 6), about 512.
558 switch (get_gen6_surface_type(dev
, info
->img
)) {
559 case GEN6_SURFTYPE_1D
:
560 case GEN6_SURFTYPE_2D
:
561 max_slice
= (ilo_dev_gen(dev
) >= ILO_GEN(7.5)) ? 2048 : 512;
563 assert(info
->img
->array_size
<= max_slice
);
564 max_slice
= info
->img
->array_size
;
566 d
= info
->slice_count
;
567 if (info
->is_cube_map
) {
568 if (info
->access
== ILO_STATE_SURFACE_ACCESS_SAMPLER
) {
570 ilo_warn("invalid cube slice count\n");
574 if (ilo_dev_gen(dev
) == ILO_GEN(7) && d
> 86 * 6) {
575 ilo_warn("cube slice count exceeds Gen7 limit\n");
580 * Minumum Array Element and Depth must be 0; Render Target View
583 if (info
->slice_base
|| d
!= 6) {
584 ilo_warn("no cube RT array support in data port\n");
592 if (!info
->is_array
&& d
> 1) {
593 ilo_warn("non-array surface with non-zero depth\n");
597 case GEN6_SURFTYPE_3D
:
600 assert(info
->img
->depth0
<= max_slice
);
601 max_slice
= u_minify(info
->img
->depth0
, info
->level_base
);
603 d
= info
->img
->depth0
;
605 if (info
->is_array
) {
606 ilo_warn("3D surfaces cannot be arrays\n");
611 assert(!"invalid surface type");
616 if (!info
->slice_count
||
617 info
->slice_base
+ info
->slice_count
> max_slice
) {
618 ilo_warn("invalid slice range\n");
626 * From the Sandy Bridge PRM, volume 4 part 1, page 84:
628 * "For Sampling Engine and Render Target 1D and 2D Surfaces:
629 * This field (Minimum Array Element) indicates the minimum array
630 * element that can be accessed as part of this surface. This field
631 * is added to the delivered array index before it is used to address
634 * For Render Target 3D Surfaces:
635 * This field indicates the minimum `R' coordinate on the LOD
636 * currently being rendered to. This field is added to the delivered
637 * array index before it is used to address the surface.
639 * For Sampling Engine Cube Surfaces on [DevSNB+] only:
640 * This field indicates the minimum array element in the underlying 2D
641 * surface array that can be accessed as part of this surface (the
642 * cube array index is multipled by 6 to compute this value, although
643 * this field is not restricted to only multiples of 6). This field is
644 * added to the delivered array index before it is used to address the
647 * For Other Surfaces:
648 * This field must be set to zero."
650 * On Gen7+, typed sufaces are treated like sampling engine 1D and 2D
653 *min_array_elem
= info
->slice_base
;
656 * From the Sandy Bridge PRM, volume 4 part 1, page 84:
658 * "For Render Target 3D Surfaces:
659 * This field (Render Target View Extent) indicates the extent of the
660 * accessible `R' coordinates minus 1 on the LOD currently being
663 * For Render Target 1D and 2D Surfaces:
664 * This field must be set to the same value as the Depth field.
666 * For Other Surfaces:
667 * This field is ignored."
669 *rt_view_extent
= info
->slice_count
- 1;
675 surface_get_gen6_image_levels(const struct ilo_dev
*dev
,
676 const struct ilo_state_surface_image_info
*info
,
677 uint8_t *min_lod
, uint8_t *mip_count
)
679 uint8_t max_level
= (ilo_dev_gen(dev
) >= ILO_GEN(7)) ? 15 : 14;
681 ILO_DEV_ASSERT(dev
, 6, 8);
683 assert(info
->img
->level_count
<= max_level
);
684 max_level
= info
->img
->level_count
;
686 if (!info
->level_count
||
687 info
->level_base
+ info
->level_count
> max_level
) {
688 ilo_warn("invalid level range\n");
693 * From the Sandy Bridge PRM, volume 4 part 1, page 79:
695 * "For Sampling Engine Surfaces:
696 * This field (MIP Count / LOD) indicates the number of MIP levels
697 * allowed to be accessed starting at Surface Min LOD, which must be
698 * less than or equal to the number of MIP levels actually stored in
699 * memory for this surface.
701 * Force the mip map access to be between the mipmap specified by the
702 * integer bits of the Min LOD and the ceiling of the value specified
705 * For Render Target Surfaces:
706 * This field defines the MIP level that is currently being rendered
707 * into. This is the absolute MIP level on the surface and is not
708 * relative to the Surface Min LOD field, which is ignored for render
711 * For Other Surfaces:
712 * This field is reserved : MBZ"
714 * From the Sandy Bridge PRM, volume 4 part 1, page 83:
716 * "For Sampling Engine Surfaces:
718 * This field (Surface Min LOD) indicates the most detailed LOD that
719 * can be accessed as part of this surface. This field is added to
720 * the delivered LOD (sample_l, ld, or resinfo message types) before
721 * it is used to address the surface.
723 * For Other Surfaces:
724 * This field is ignored."
726 * On Gen7+, typed sufaces are treated like sampling engine surfaces.
728 if (info
->access
== ILO_STATE_SURFACE_ACCESS_DP_RENDER
) {
729 assert(info
->level_count
== 1);
732 *mip_count
= info
->level_base
;
734 *min_lod
= info
->level_base
;
735 *mip_count
= info
->level_count
- 1;
742 surface_get_gen6_image_sample_count(const struct ilo_dev
*dev
,
743 const struct ilo_state_surface_image_info
*info
,
744 enum gen_sample_count
*sample_count
)
748 ILO_DEV_ASSERT(dev
, 6, 8);
750 switch (info
->img
->sample_count
) {
752 *sample_count
= GEN6_NUMSAMPLES_1
;
753 min_gen
= ILO_GEN(6);
756 *sample_count
= GEN8_NUMSAMPLES_2
;
757 min_gen
= ILO_GEN(8);
760 *sample_count
= GEN6_NUMSAMPLES_4
;
761 min_gen
= ILO_GEN(6);
764 *sample_count
= GEN7_NUMSAMPLES_8
;
765 min_gen
= ILO_GEN(7);
768 *sample_count
= GEN8_NUMSAMPLES_16
;
769 min_gen
= ILO_GEN(8);
772 assert(!"invalid sample count");
773 *sample_count
= GEN6_NUMSAMPLES_1
;
777 assert(ilo_dev_gen(dev
) >= min_gen
);
783 surface_get_gen6_image_alignments(const struct ilo_dev
*dev
,
784 const struct ilo_state_surface_image_info
*info
,
785 uint32_t *alignments
)
790 ILO_DEV_ASSERT(dev
, 6, 8);
792 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
793 switch (info
->img
->align_i
) {
795 a
|= GEN8_SURFACE_DW0_HALIGN_4
;
798 a
|= GEN8_SURFACE_DW0_HALIGN_8
;
801 a
|= GEN8_SURFACE_DW0_HALIGN_16
;
808 switch (info
->img
->align_j
) {
810 a
|= GEN7_SURFACE_DW0_VALIGN_4
;
813 a
|= GEN8_SURFACE_DW0_VALIGN_8
;
816 a
|= GEN8_SURFACE_DW0_VALIGN_16
;
822 } else if (ilo_dev_gen(dev
) >= ILO_GEN(7)) {
823 switch (info
->img
->align_i
) {
825 a
|= GEN7_SURFACE_DW0_HALIGN_4
;
828 a
|= GEN7_SURFACE_DW0_HALIGN_8
;
835 switch (info
->img
->align_j
) {
837 a
|= GEN7_SURFACE_DW0_VALIGN_2
;
840 a
|= GEN7_SURFACE_DW0_VALIGN_4
;
847 if (info
->img
->align_i
!= 4)
850 switch (info
->img
->align_j
) {
852 a
|= GEN6_SURFACE_DW5_VALIGN_2
;
855 a
|= GEN6_SURFACE_DW5_VALIGN_4
;
864 assert(!"invalid HALIGN or VALIGN");
872 surface_set_gen6_image_SURFACE_STATE(struct ilo_state_surface
*surf
,
873 const struct ilo_dev
*dev
,
874 const struct ilo_state_surface_image_info
*info
)
876 uint16_t width
, height
, depth
, array_base
, view_extent
;
877 uint8_t min_lod
, mip_count
;
878 enum gen_sample_count sample_count
;
880 enum gen_surface_type type
;
881 uint32_t dw0
, dw2
, dw3
, dw4
, dw5
;
883 ILO_DEV_ASSERT(dev
, 6, 6);
885 if (!surface_validate_gen6_image(dev
, info
) ||
886 !surface_get_gen6_image_extent(dev
, info
, &width
, &height
) ||
887 !surface_get_gen6_image_slices(dev
, info
, &depth
, &array_base
,
889 !surface_get_gen6_image_levels(dev
, info
, &min_lod
, &mip_count
) ||
890 !surface_get_gen6_image_sample_count(dev
, info
, &sample_count
) ||
891 !surface_get_gen6_image_alignments(dev
, info
, &alignments
))
895 assert(info
->img
->walk
!= ILO_IMAGE_WALK_LOD
);
897 if (info
->img
->sample_count
> 1)
898 assert(info
->img
->interleaved_samples
);
900 type
= (info
->is_cube_map
) ? GEN6_SURFTYPE_CUBE
:
901 get_gen6_surface_type(dev
, info
->img
);
903 dw0
= type
<< GEN6_SURFACE_DW0_TYPE__SHIFT
|
904 info
->format
<< GEN6_SURFACE_DW0_FORMAT__SHIFT
|
905 GEN6_SURFACE_DW0_MIPLAYOUT_BELOW
;
908 * From the Sandy Bridge PRM, volume 4 part 1, page 74:
910 * "CUBE_AVERAGE may only be selected if all of the Cube Face Enable
911 * fields are equal to one."
913 * From the Sandy Bridge PRM, volume 4 part 1, page 75-76:
915 * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine:
916 * Bits 5:0 of this field (Cube Face Enables) enable the individual
917 * faces of a cube map. Enabling a face indicates that the face is
918 * present in the cube map, while disabling it indicates that that
919 * face is represented by the texture map's border color. Refer to
920 * Memory Data Formats for the correlation between faces and the cube
921 * map memory layout. Note that storage for disabled faces must be
924 * For other surfaces:
925 * This field is reserved : MBZ"
927 * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
928 * field must be programmed to 111111b (all faces enabled)."
930 if (info
->is_cube_map
&&
931 info
->access
== ILO_STATE_SURFACE_ACCESS_SAMPLER
) {
932 dw0
|= GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE
|
933 GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK
;
936 dw2
= height
<< GEN6_SURFACE_DW2_HEIGHT__SHIFT
|
937 width
<< GEN6_SURFACE_DW2_WIDTH__SHIFT
|
938 mip_count
<< GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT
;
940 dw3
= depth
<< GEN6_SURFACE_DW3_DEPTH__SHIFT
|
941 (info
->img
->bo_stride
- 1) << GEN6_SURFACE_DW3_PITCH__SHIFT
|
942 info
->img
->tiling
<< GEN6_SURFACE_DW3_TILING__SHIFT
;
944 dw4
= min_lod
<< GEN6_SURFACE_DW4_MIN_LOD__SHIFT
|
945 array_base
<< GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT
|
946 view_extent
<< GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT
|
947 sample_count
<< GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT
;
951 STATIC_ASSERT(ARRAY_SIZE(surf
->surface
) >= 6);
952 surf
->surface
[0] = dw0
;
953 surf
->surface
[1] = 0;
954 surf
->surface
[2] = dw2
;
955 surf
->surface
[3] = dw3
;
956 surf
->surface
[4] = dw4
;
957 surf
->surface
[5] = dw5
;
960 surf
->min_lod
= min_lod
;
961 surf
->mip_count
= mip_count
;
967 surface_set_gen7_image_SURFACE_STATE(struct ilo_state_surface
*surf
,
968 const struct ilo_dev
*dev
,
969 const struct ilo_state_surface_image_info
*info
)
971 uint16_t width
, height
, depth
, array_base
, view_extent
;
972 uint8_t min_lod
, mip_count
;
974 enum gen_sample_count sample_count
;
975 enum gen_surface_type type
;
976 uint32_t dw0
, dw1
, dw2
, dw3
, dw4
, dw5
, dw7
;
978 ILO_DEV_ASSERT(dev
, 7, 8);
980 if (!surface_validate_gen6_image(dev
, info
) ||
981 !surface_get_gen6_image_extent(dev
, info
, &width
, &height
) ||
982 !surface_get_gen6_image_slices(dev
, info
, &depth
, &array_base
,
984 !surface_get_gen6_image_levels(dev
, info
, &min_lod
, &mip_count
) ||
985 !surface_get_gen6_image_sample_count(dev
, info
, &sample_count
) ||
986 !surface_get_gen6_image_alignments(dev
, info
, &alignments
))
989 type
= (info
->is_cube_map
) ? GEN6_SURFTYPE_CUBE
:
990 get_gen6_surface_type(dev
, info
->img
);
992 dw0
= type
<< GEN7_SURFACE_DW0_TYPE__SHIFT
|
993 info
->format
<< GEN7_SURFACE_DW0_FORMAT__SHIFT
|
997 dw0
|= GEN7_SURFACE_DW0_IS_ARRAY
;
999 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
1000 dw0
|= info
->img
->tiling
<< GEN8_SURFACE_DW0_TILING__SHIFT
;
1002 dw0
|= info
->img
->tiling
<< GEN7_SURFACE_DW0_TILING__SHIFT
;
1004 if (info
->img
->walk
== ILO_IMAGE_WALK_LOD
)
1005 dw0
|= GEN7_SURFACE_DW0_ARYSPC_LOD0
;
1007 dw0
|= GEN7_SURFACE_DW0_ARYSPC_FULL
;
1011 * From the Ivy Bridge PRM, volume 4 part 1, page 67:
1013 * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine: Bits
1014 * 5:0 of this field (Cube Face Enables) enable the individual faces
1015 * of a cube map. Enabling a face indicates that the face is present
1016 * in the cube map, while disabling it indicates that that face is
1017 * represented by the texture map's border color. Refer to Memory Data
1018 * Formats for the correlation between faces and the cube map memory
1019 * layout. Note that storage for disabled faces must be provided. For
1020 * other surfaces this field is reserved and MBZ."
1022 * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
1023 * field must be programmed to 111111b (all faces enabled). This field
1024 * is ignored unless the Surface Type is SURFTYPE_CUBE."
1026 if (info
->is_cube_map
&&
1027 info
->access
== ILO_STATE_SURFACE_ACCESS_SAMPLER
)
1028 dw0
|= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK
;
1031 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
1032 assert(info
->img
->walk_layer_height
% 4 == 0);
1033 dw1
|= info
->img
->walk_layer_height
/ 4 <<
1034 GEN8_SURFACE_DW1_QPITCH__SHIFT
;
1037 dw2
= height
<< GEN7_SURFACE_DW2_HEIGHT__SHIFT
|
1038 width
<< GEN7_SURFACE_DW2_WIDTH__SHIFT
;
1040 dw3
= depth
<< GEN7_SURFACE_DW3_DEPTH__SHIFT
|
1041 (info
->img
->bo_stride
- 1) << GEN7_SURFACE_DW3_PITCH__SHIFT
;
1043 if (ilo_dev_gen(dev
) == ILO_GEN(7.5))
1044 dw3
|= 0 << GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT
;
1046 dw4
= array_base
<< GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT
|
1047 view_extent
<< GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT
|
1048 sample_count
<< GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT
;
1051 * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
1052 * means the samples are interleaved. The layouts are the same when the
1053 * number of samples is 1.
1055 if (info
->img
->interleaved_samples
&& info
->img
->sample_count
> 1) {
1056 assert(info
->access
!= ILO_STATE_SURFACE_ACCESS_DP_RENDER
);
1057 dw4
|= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL
;
1059 dw4
|= GEN7_SURFACE_DW4_MSFMT_MSS
;
1062 dw5
= min_lod
<< GEN7_SURFACE_DW5_MIN_LOD__SHIFT
|
1063 mip_count
<< GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT
;
1066 if (ilo_dev_gen(dev
) >= ILO_GEN(7.5)) {
1067 dw7
|= GEN_SHIFT32(GEN75_SCS_RED
, GEN75_SURFACE_DW7_SCS_R
) |
1068 GEN_SHIFT32(GEN75_SCS_GREEN
, GEN75_SURFACE_DW7_SCS_G
) |
1069 GEN_SHIFT32(GEN75_SCS_BLUE
, GEN75_SURFACE_DW7_SCS_B
) |
1070 GEN_SHIFT32(GEN75_SCS_ALPHA
, GEN75_SURFACE_DW7_SCS_A
);
1073 STATIC_ASSERT(ARRAY_SIZE(surf
->surface
) >= 13);
1074 surf
->surface
[0] = dw0
;
1075 surf
->surface
[1] = dw1
;
1076 surf
->surface
[2] = dw2
;
1077 surf
->surface
[3] = dw3
;
1078 surf
->surface
[4] = dw4
;
1079 surf
->surface
[5] = dw5
;
1080 surf
->surface
[6] = 0;
1081 surf
->surface
[7] = dw7
;
1082 if (ilo_dev_gen(dev
) >= ILO_GEN(8)) {
1083 surf
->surface
[8] = 0;
1084 surf
->surface
[9] = 0;
1085 surf
->surface
[10] = 0;
1086 surf
->surface
[11] = 0;
1087 surf
->surface
[12] = 0;
1091 surf
->min_lod
= min_lod
;
1092 surf
->mip_count
= mip_count
;
1098 ilo_state_surface_init_for_null(struct ilo_state_surface
*surf
,
1099 const struct ilo_dev
*dev
)
1103 assert(ilo_is_zeroed(surf
, sizeof(*surf
)));
1105 if (ilo_dev_gen(dev
) >= ILO_GEN(7))
1106 ret
&= surface_set_gen7_null_SURFACE_STATE(surf
, dev
);
1108 ret
&= surface_set_gen6_null_SURFACE_STATE(surf
, dev
);
1110 surf
->type
= GEN6_SURFTYPE_NULL
;
1111 surf
->readonly
= true;
1119 ilo_state_surface_init_for_buffer(struct ilo_state_surface
*surf
,
1120 const struct ilo_dev
*dev
,
1121 const struct ilo_state_surface_buffer_info
*info
)
1125 assert(ilo_is_zeroed(surf
, sizeof(*surf
)));
1127 if (ilo_dev_gen(dev
) >= ILO_GEN(7))
1128 ret
&= surface_set_gen7_buffer_SURFACE_STATE(surf
, dev
, info
);
1130 ret
&= surface_set_gen6_buffer_SURFACE_STATE(surf
, dev
, info
);
1132 surf
->readonly
= info
->readonly
;
1140 ilo_state_surface_init_for_image(struct ilo_state_surface
*surf
,
1141 const struct ilo_dev
*dev
,
1142 const struct ilo_state_surface_image_info
*info
)
1146 assert(ilo_is_zeroed(surf
, sizeof(*surf
)));
1148 if (ilo_dev_gen(dev
) >= ILO_GEN(7))
1149 ret
&= surface_set_gen7_image_SURFACE_STATE(surf
, dev
, info
);
1151 ret
&= surface_set_gen6_image_SURFACE_STATE(surf
, dev
, info
);
1153 surf
->is_integer
= info
->is_integer
;
1154 surf
->readonly
= info
->readonly
;
1155 surf
->scanout
= info
->img
->scanout
;
1163 ilo_state_surface_set_scs(struct ilo_state_surface
*surf
,
1164 const struct ilo_dev
*dev
,
1165 enum gen_surface_scs rgba
[4])
1167 const uint32_t scs
= GEN_SHIFT32(rgba
[0], GEN75_SURFACE_DW7_SCS_R
) |
1168 GEN_SHIFT32(rgba
[1], GEN75_SURFACE_DW7_SCS_G
) |
1169 GEN_SHIFT32(rgba
[2], GEN75_SURFACE_DW7_SCS_B
) |
1170 GEN_SHIFT32(rgba
[3], GEN75_SURFACE_DW7_SCS_A
);
1172 ILO_DEV_ASSERT(dev
, 6, 8);
1174 assert(ilo_dev_gen(dev
) >= ILO_GEN(7.5));
1176 surf
->surface
[7] = (surf
->surface
[7] & ~GEN75_SURFACE_DW7_SCS__MASK
) | scs
;