src/gallium/drivers/ilo/genhw/gen_mi.xml.h

   1 #ifndef GEN_MI_XML
   2 #define GEN_MI_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 https://github.com/olvaffe/envytools/
   8 git clone https://github.com/olvaffe/envytools.git
   9
  10 Copyright (C) 2014 by the following authors:
  11 - Chia-I Wu <olvaffe@gmail.com> (olv)
  12
  13 Permission is hereby granted, free of charge, to any person obtaining
  14 a copy of this software and associated documentation files (the
  15 "Software"), to deal in the Software without restriction, including
  16 without limitation the rights to use, copy, modify, merge, publish,
  17 distribute, sublicense, and/or sell copies of the Software, and to
  18 permit persons to whom the Software is furnished to do so, subject to
  19 the following conditions:
  20
  21 The above copyright notice and this permission notice (including the
  22 next paragraph) shall be included in all copies or substantial
  23 portions of the Software.
  24
  25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  32 */
  33
  34
  35 #define GEN6_MI_TYPE__MASK                                      0xe0000000
  36 #define GEN6_MI_TYPE__SHIFT                                     29
  37 #define GEN6_MI_TYPE_MI                                         (0x0 << 29)
  38 #define GEN6_MI_OPCODE__MASK                                    0x1f800000
  39 #define GEN6_MI_OPCODE__SHIFT                                   23
  40 #define GEN6_MI_OPCODE_MI_NOOP                                  (0x0 << 23)
  41 #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END                      (0xa << 23)
  42 #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM                        (0x20 << 23)
  43 #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM                     (0x22 << 23)
  44 #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM                    (0x24 << 23)
  45 #define GEN6_MI_OPCODE_MI_FLUSH_DW                              (0x26 << 23)
  46 #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT                     (0x28 << 23)
  47 #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM                     (0x29 << 23)
  48 #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START                    (0x31 << 23)
  49 #define GEN6_MI_LENGTH__MASK                                    0x0000003f
  50 #define GEN6_MI_LENGTH__SHIFT                                   0
  51 #define GEN6_MI_NOOP__SIZE                                      1
  52
  53 #define GEN6_MI_BATCH_BUFFER_END__SIZE                          1
  54
  55 #define GEN6_MI_STORE_DATA_IMM__SIZE                            5
  56 #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT                     (0x1 << 22)
  57
  58 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK                   0xfffffffc
  59 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT                  2
  60 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR                    2
  61
  62
  63 #define GEN6_MI_LOAD_REGISTER_IMM__SIZE                         3
  64 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK      0x00000f00
  65 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT     8
  66
  67 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK                 0x007ffffc
  68 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT                2
  69 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR                  2
  70
  71
  72 #define GEN6_MI_STORE_REGISTER_MEM__SIZE                        3
  73 #define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT                 (0x1 << 22)
  74 #define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE        (0x1 << 21)
  75
  76 #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK                0x007ffffc
  77 #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT               2
  78 #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR                 2
  79
  80 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK               0xfffffffc
  81 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT              2
  82 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR                2
  83
  84 #define GEN6_MI_FLUSH_DW__SIZE                                  4
  85
  86 #define GEN6_MI_REPORT_PERF_COUNT__SIZE                         3
  87
  88 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK                0xffffffc0
  89 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT               6
  90 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR                 6
  91 #define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE          (0x1 << 4)
  92 #define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT                  (0x1 << 0)
  93
  94
  95 #define GEN7_MI_LOAD_REGISTER_MEM__SIZE                         3
  96 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT                  (0x1 << 22)
  97 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE         (0x1 << 21)
  98
  99 #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK                 0x007ffffc
 100 #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT                2
 101 #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR                  2
 102
 103 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK                0xfffffffc
 104 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT               2
 105 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR                 2
 106
 107 #define GEN6_MI_BATCH_BUFFER_START__SIZE                        2
 108 #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL            (0x1 << 22)
 109 #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE       (0x1 << 16)
 110 #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE      (0x1 << 15)
 111 #define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED          (0x1 << 13)
 112 #define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER     (0x1 << 11)
 113 #define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT                (0x1 << 8)
 114
 115 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK               0xfffffffc
 116 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT              2
 117 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR                2
 118
 119
 120 #endif /* GEN_MI_XML */