2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "util/u_prim.h"
29 #include "intel_winsys.h"
31 #include "ilo_3d_pipeline.h"
33 #include "ilo_context.h"
35 #include "ilo_query.h"
36 #include "ilo_shader.h"
37 #include "ilo_state.h"
41 process_query_for_occlusion_counter(struct ilo_3d
*hw3d
,
44 uint64_t *vals
, depth_count
= 0;
48 assert(q
->reg_read
% 2 == 0);
50 vals
= intel_bo_map(q
->bo
, false);
51 for (i
= 1; i
< q
->reg_read
; i
+= 2)
52 depth_count
+= vals
[i
] - vals
[i
- 1];
53 intel_bo_unmap(q
->bo
);
55 /* accumulate so that the query can be resumed if wanted */
56 q
->data
.u64
+= depth_count
;
61 timestamp_to_ns(uint64_t timestamp
)
63 /* see ilo_get_timestamp() */
64 return (timestamp
& 0xffffffff) * 80;
68 process_query_for_timestamp(struct ilo_3d
*hw3d
, struct ilo_query
*q
)
70 uint64_t *vals
, timestamp
;
72 assert(q
->reg_read
== 1);
74 vals
= intel_bo_map(q
->bo
, false);
76 intel_bo_unmap(q
->bo
);
78 q
->data
.u64
= timestamp_to_ns(timestamp
);
83 process_query_for_time_elapsed(struct ilo_3d
*hw3d
, struct ilo_query
*q
)
85 uint64_t *vals
, elapsed
= 0;
89 assert(q
->reg_read
% 2 == 0);
91 vals
= intel_bo_map(q
->bo
, false);
93 for (i
= 1; i
< q
->reg_read
; i
+= 2)
94 elapsed
+= vals
[i
] - vals
[i
- 1];
96 intel_bo_unmap(q
->bo
);
98 /* accumulate so that the query can be resumed if wanted */
99 q
->data
.u64
+= timestamp_to_ns(elapsed
);
104 ilo_3d_resume_queries(struct ilo_3d
*hw3d
)
108 /* resume occlusion queries */
109 LIST_FOR_EACH_ENTRY(q
, &hw3d
->occlusion_queries
, list
) {
110 /* accumulate the result if the bo is alreay full */
111 if (q
->reg_read
>= q
->reg_total
)
112 process_query_for_occlusion_counter(hw3d
, q
);
114 ilo_3d_pipeline_emit_write_depth_count(hw3d
->pipeline
,
115 q
->bo
, q
->reg_read
++);
118 /* resume timer queries */
119 LIST_FOR_EACH_ENTRY(q
, &hw3d
->time_elapsed_queries
, list
) {
120 /* accumulate the result if the bo is alreay full */
121 if (q
->reg_read
>= q
->reg_total
)
122 process_query_for_time_elapsed(hw3d
, q
);
124 ilo_3d_pipeline_emit_write_timestamp(hw3d
->pipeline
,
125 q
->bo
, q
->reg_read
++);
130 ilo_3d_pause_queries(struct ilo_3d
*hw3d
)
134 /* pause occlusion queries */
135 LIST_FOR_EACH_ENTRY(q
, &hw3d
->occlusion_queries
, list
) {
136 assert(q
->reg_read
< q
->reg_total
);
137 ilo_3d_pipeline_emit_write_depth_count(hw3d
->pipeline
,
138 q
->bo
, q
->reg_read
++);
141 /* pause timer queries */
142 LIST_FOR_EACH_ENTRY(q
, &hw3d
->time_elapsed_queries
, list
) {
143 assert(q
->reg_read
< q
->reg_total
);
144 ilo_3d_pipeline_emit_write_timestamp(hw3d
->pipeline
,
145 q
->bo
, q
->reg_read
++);
150 ilo_3d_release_render_ring(struct ilo_cp
*cp
, void *data
)
152 struct ilo_3d
*hw3d
= data
;
154 ilo_3d_pause_queries(hw3d
);
158 ilo_3d_own_render_ring(struct ilo_3d
*hw3d
)
160 ilo_cp_set_ring(hw3d
->cp
, INTEL_RING_RENDER
);
162 if (ilo_cp_set_owner(hw3d
->cp
, &hw3d
->owner
, hw3d
->owner_reserve
))
163 ilo_3d_resume_queries(hw3d
);
170 ilo_3d_begin_query(struct ilo_context
*ilo
, struct ilo_query
*q
)
172 struct ilo_3d
*hw3d
= ilo
->hw3d
;
174 ilo_3d_own_render_ring(hw3d
);
177 case PIPE_QUERY_OCCLUSION_COUNTER
:
178 /* reserve some space for pausing the query */
179 q
->reg_cmd_size
= ilo_3d_pipeline_estimate_size(hw3d
->pipeline
,
180 ILO_3D_PIPELINE_WRITE_DEPTH_COUNT
, NULL
);
181 hw3d
->owner_reserve
+= q
->reg_cmd_size
;
182 ilo_cp_set_owner(hw3d
->cp
, &hw3d
->owner
, hw3d
->owner_reserve
);
186 if (ilo_query_alloc_bo(q
, 2, -1, hw3d
->cp
->winsys
)) {
187 /* XXX we should check the aperture size */
188 ilo_3d_pipeline_emit_write_depth_count(hw3d
->pipeline
,
189 q
->bo
, q
->reg_read
++);
191 list_add(&q
->list
, &hw3d
->occlusion_queries
);
194 case PIPE_QUERY_TIMESTAMP
:
197 case PIPE_QUERY_TIME_ELAPSED
:
198 /* reserve some space for pausing the query */
199 q
->reg_cmd_size
= ilo_3d_pipeline_estimate_size(hw3d
->pipeline
,
200 ILO_3D_PIPELINE_WRITE_TIMESTAMP
, NULL
);
201 hw3d
->owner_reserve
+= q
->reg_cmd_size
;
202 ilo_cp_set_owner(hw3d
->cp
, &hw3d
->owner
, hw3d
->owner_reserve
);
206 if (ilo_query_alloc_bo(q
, 2, -1, hw3d
->cp
->winsys
)) {
207 /* XXX we should check the aperture size */
208 ilo_3d_pipeline_emit_write_timestamp(hw3d
->pipeline
,
209 q
->bo
, q
->reg_read
++);
211 list_add(&q
->list
, &hw3d
->time_elapsed_queries
);
214 case PIPE_QUERY_PRIMITIVES_GENERATED
:
216 list_add(&q
->list
, &hw3d
->prim_generated_queries
);
218 case PIPE_QUERY_PRIMITIVES_EMITTED
:
220 list_add(&q
->list
, &hw3d
->prim_emitted_queries
);
223 assert(!"unknown query type");
232 ilo_3d_end_query(struct ilo_context
*ilo
, struct ilo_query
*q
)
234 struct ilo_3d
*hw3d
= ilo
->hw3d
;
236 ilo_3d_own_render_ring(hw3d
);
239 case PIPE_QUERY_OCCLUSION_COUNTER
:
242 assert(q
->reg_read
< q
->reg_total
);
243 hw3d
->owner_reserve
-= q
->reg_cmd_size
;
244 ilo_cp_set_owner(hw3d
->cp
, &hw3d
->owner
, hw3d
->owner_reserve
);
245 ilo_3d_pipeline_emit_write_depth_count(hw3d
->pipeline
,
246 q
->bo
, q
->reg_read
++);
248 case PIPE_QUERY_TIMESTAMP
:
251 if (ilo_query_alloc_bo(q
, 1, 1, hw3d
->cp
->winsys
)) {
252 ilo_3d_pipeline_emit_write_timestamp(hw3d
->pipeline
,
253 q
->bo
, q
->reg_read
++);
256 case PIPE_QUERY_TIME_ELAPSED
:
259 assert(q
->reg_read
< q
->reg_total
);
260 hw3d
->owner_reserve
-= q
->reg_cmd_size
;
261 ilo_cp_set_owner(hw3d
->cp
, &hw3d
->owner
, hw3d
->owner_reserve
);
262 ilo_3d_pipeline_emit_write_timestamp(hw3d
->pipeline
,
263 q
->bo
, q
->reg_read
++);
265 case PIPE_QUERY_PRIMITIVES_GENERATED
:
266 case PIPE_QUERY_PRIMITIVES_EMITTED
:
270 assert(!"unknown query type");
276 * Process the raw query data.
279 ilo_3d_process_query(struct ilo_context
*ilo
, struct ilo_query
*q
)
281 struct ilo_3d
*hw3d
= ilo
->hw3d
;
284 case PIPE_QUERY_OCCLUSION_COUNTER
:
286 process_query_for_occlusion_counter(hw3d
, q
);
288 case PIPE_QUERY_TIMESTAMP
:
290 process_query_for_timestamp(hw3d
, q
);
292 case PIPE_QUERY_TIME_ELAPSED
:
294 process_query_for_time_elapsed(hw3d
, q
);
296 case PIPE_QUERY_PRIMITIVES_GENERATED
:
297 case PIPE_QUERY_PRIMITIVES_EMITTED
:
300 assert(!"unknown query type");
306 * Hook for CP new-batch.
309 ilo_3d_cp_flushed(struct ilo_3d
*hw3d
)
311 if (ilo_debug
& ILO_DEBUG_3D
)
312 ilo_3d_pipeline_dump(hw3d
->pipeline
);
314 /* invalidate the pipeline */
315 ilo_3d_pipeline_invalidate(hw3d
->pipeline
,
316 ILO_3D_PIPELINE_INVALIDATE_BATCH_BO
|
317 ILO_3D_PIPELINE_INVALIDATE_STATE_BO
);
319 hw3d
->new_batch
= true;
323 * Create a 3D context.
326 ilo_3d_create(struct ilo_cp
*cp
, const struct ilo_dev_info
*dev
)
330 hw3d
= CALLOC_STRUCT(ilo_3d
);
335 hw3d
->owner
.release_callback
= ilo_3d_release_render_ring
;
336 hw3d
->owner
.release_data
= hw3d
;
338 hw3d
->new_batch
= true;
340 list_inithead(&hw3d
->occlusion_queries
);
341 list_inithead(&hw3d
->time_elapsed_queries
);
342 list_inithead(&hw3d
->prim_generated_queries
);
343 list_inithead(&hw3d
->prim_emitted_queries
);
345 hw3d
->pipeline
= ilo_3d_pipeline_create(cp
, dev
);
346 if (!hw3d
->pipeline
) {
355 * Destroy a 3D context.
358 ilo_3d_destroy(struct ilo_3d
*hw3d
)
360 ilo_3d_pipeline_destroy(hw3d
->pipeline
);
363 intel_bo_unreference(hw3d
->kernel
.bo
);
369 draw_vbo(struct ilo_3d
*hw3d
, const struct ilo_context
*ilo
,
370 int *prim_generated
, int *prim_emitted
)
372 bool need_flush
= false;
375 ilo_3d_own_render_ring(hw3d
);
377 if (!hw3d
->new_batch
) {
379 * Without a better tracking mechanism, when the framebuffer changes, we
380 * have to assume that the old framebuffer may be sampled from. If that
381 * happens in the middle of a batch buffer, we need to insert manual
384 need_flush
= (ilo
->dirty
& ILO_DIRTY_FB
);
386 /* same to SO target changes */
387 need_flush
|= (ilo
->dirty
& ILO_DIRTY_SO
);
390 /* make sure there is enough room first */
391 max_len
= ilo_3d_pipeline_estimate_size(hw3d
->pipeline
,
392 ILO_3D_PIPELINE_DRAW
, ilo
);
394 max_len
+= ilo_3d_pipeline_estimate_size(hw3d
->pipeline
,
395 ILO_3D_PIPELINE_FLUSH
, NULL
);
398 if (max_len
> ilo_cp_space(hw3d
->cp
)) {
399 ilo_cp_flush(hw3d
->cp
, "out of space");
401 assert(max_len
<= ilo_cp_space(hw3d
->cp
));
405 ilo_3d_pipeline_emit_flush(hw3d
->pipeline
);
407 return ilo_3d_pipeline_emit_draw(hw3d
->pipeline
, ilo
,
408 prim_generated
, prim_emitted
);
412 update_prim_count(struct ilo_3d
*hw3d
, int generated
, int emitted
)
416 LIST_FOR_EACH_ENTRY(q
, &hw3d
->prim_generated_queries
, list
)
417 q
->data
.u64
+= generated
;
419 LIST_FOR_EACH_ENTRY(q
, &hw3d
->prim_emitted_queries
, list
)
420 q
->data
.u64
+= emitted
;
424 ilo_3d_pass_render_condition(struct ilo_context
*ilo
)
426 struct ilo_3d
*hw3d
= ilo
->hw3d
;
430 if (!hw3d
->render_condition
.query
)
433 switch (hw3d
->render_condition
.mode
) {
434 case PIPE_RENDER_COND_WAIT
:
435 case PIPE_RENDER_COND_BY_REGION_WAIT
:
438 case PIPE_RENDER_COND_NO_WAIT
:
439 case PIPE_RENDER_COND_BY_REGION_NO_WAIT
:
445 if (ilo
->base
.get_query_result(&ilo
->base
, hw3d
->render_condition
.query
,
446 wait
, (union pipe_query_result
*) &result
))
447 return (!result
== hw3d
->render_condition
.cond
);
452 #define UPDATE_MIN2(a, b) (a) = MIN2((a), (b))
453 #define UPDATE_MAX2(a, b) (a) = MAX2((a), (b))
456 * \see find_sub_primitives() from core mesa
459 ilo_find_sub_primitives(const void *elements
, unsigned element_size
,
460 const struct pipe_draw_info
*orig_info
,
461 struct pipe_draw_info
*info
)
463 const unsigned max_prims
= orig_info
->count
- orig_info
->start
;
464 unsigned i
, cur_start
, cur_count
;
468 cur_start
= orig_info
->start
;
472 #define IB_INDEX_READ(TYPE, INDEX) (((const TYPE *) elements)[INDEX])
474 #define SCAN_ELEMENTS(TYPE) \
475 info[scan_num] = *orig_info; \
476 info[scan_num].primitive_restart = false; \
477 for (i = orig_info->start; i < orig_info->count; i++) { \
478 scan_index = IB_INDEX_READ(TYPE, i); \
479 if (scan_index == orig_info->restart_index) { \
480 if (cur_count > 0) { \
481 assert(scan_num < max_prims); \
482 info[scan_num].start = cur_start; \
483 info[scan_num].count = cur_count; \
485 info[scan_num] = *orig_info; \
486 info[scan_num].primitive_restart = false; \
492 UPDATE_MIN2(info[scan_num].min_index, scan_index); \
493 UPDATE_MAX2(info[scan_num].max_index, scan_index); \
497 if (cur_count > 0) { \
498 assert(scan_num < max_prims); \
499 info[scan_num].start = cur_start; \
500 info[scan_num].count = cur_count; \
504 switch (element_size
) {
506 SCAN_ELEMENTS(uint8_t);
509 SCAN_ELEMENTS(uint16_t);
512 SCAN_ELEMENTS(uint32_t);
515 assert(0 && "bad index_size in find_sub_primitives()");
524 ilo_check_restart_index(const struct ilo_context
*ilo
, unsigned restart_index
)
527 * Haswell (GEN(7.5)) supports an arbitrary cut index, check everything
530 if (ilo
->dev
->gen
>= ILO_GEN(7.5))
533 /* Note: indices must be unsigned byte, unsigned short or unsigned int */
534 switch (ilo
->ib
.index_size
) {
536 return ((restart_index
& 0xff) == 0xff);
539 return ((restart_index
& 0xffff) == 0xffff);
542 return (restart_index
== 0xffffffff);
549 ilo_check_restart_prim_type(const struct ilo_context
*ilo
, unsigned prim
)
552 case PIPE_PRIM_POINTS
:
553 case PIPE_PRIM_LINES
:
554 case PIPE_PRIM_LINE_STRIP
:
555 case PIPE_PRIM_TRIANGLES
:
556 case PIPE_PRIM_TRIANGLE_STRIP
:
557 /* All 965 GEN graphics support a cut index for these primitive types */
561 case PIPE_PRIM_LINE_LOOP
:
562 case PIPE_PRIM_POLYGON
:
563 case PIPE_PRIM_QUAD_STRIP
:
564 case PIPE_PRIM_QUADS
:
565 case PIPE_PRIM_TRIANGLE_FAN
:
566 if (ilo
->dev
->gen
>= ILO_GEN(7.5)) {
567 /* Haswell and newer parts can handle these prim types. */
577 * Handle VBOs using primitive restart.
578 * Verify that restart index and primitive type can be handled by the HW.
579 * Return true if this routine did the rendering
580 * Return false if this routine did NOT render because restart can be handled
584 ilo_draw_vbo_with_sw_restart(struct pipe_context
*pipe
,
585 const struct pipe_draw_info
*info
)
587 struct ilo_context
*ilo
= ilo_context(pipe
);
588 struct pipe_draw_info
*restart_info
= NULL
;
589 int sub_prim_count
= 1;
592 * We have to break up the primitive into chunks manually
593 * Worst case, every other index could be a restart index so
594 * need to have space for that many primitives
596 restart_info
= MALLOC(((info
->count
+ 1) / 2) * sizeof(*info
));
597 if (NULL
== restart_info
) {
598 /* If we can't get memory for this, bail out */
599 ilo_err("%s:%d - Out of memory", __FILE__
, __LINE__
);
603 if (ilo
->ib
.buffer
) {
604 struct pipe_transfer
*transfer
;
607 map
= pipe_buffer_map(pipe
, ilo
->ib
.buffer
,
608 PIPE_TRANSFER_READ
, &transfer
);
610 sub_prim_count
= ilo_find_sub_primitives(map
+ ilo
->ib
.offset
,
611 ilo
->ib
.index_size
, info
, restart_info
);
613 pipe_buffer_unmap(pipe
, transfer
);
616 sub_prim_count
= ilo_find_sub_primitives(ilo
->ib
.user_buffer
,
617 ilo
->ib
.index_size
, info
, restart_info
);
622 while (sub_prim_count
> 0) {
623 pipe
->draw_vbo(pipe
, info
);
633 upload_shaders(struct ilo_3d
*hw3d
, struct ilo_shader_cache
*shc
)
635 bool incremental
= true;
638 upload
= ilo_shader_cache_upload(shc
,
639 NULL
, hw3d
->kernel
.used
, incremental
);
644 * Allocate a new bo. When this is a new batch, assume the bo is still in
645 * use by the previous batch and force allocation.
647 * Does it help to make shader cache upload with unsynchronized mapping,
648 * and remove the check for new batch here?
650 if (hw3d
->kernel
.used
+ upload
> hw3d
->kernel
.size
|| hw3d
->new_batch
) {
651 unsigned new_size
= (hw3d
->kernel
.size
) ?
652 hw3d
->kernel
.size
: (8 * 1024);
654 while (hw3d
->kernel
.used
+ upload
> new_size
)
658 intel_bo_unreference(hw3d
->kernel
.bo
);
660 hw3d
->kernel
.bo
= intel_winsys_alloc_buffer(hw3d
->cp
->winsys
,
661 "kernel bo", new_size
, INTEL_DOMAIN_CPU
);
662 if (!hw3d
->kernel
.bo
) {
663 ilo_err("failed to allocate kernel bo\n");
667 hw3d
->kernel
.used
= 0;
668 hw3d
->kernel
.size
= new_size
;
671 assert(new_size
>= ilo_shader_cache_upload(shc
,
672 NULL
, hw3d
->kernel
.used
, incremental
));
674 ilo_3d_pipeline_invalidate(hw3d
->pipeline
,
675 ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO
);
678 upload
= ilo_shader_cache_upload(shc
,
679 hw3d
->kernel
.bo
, hw3d
->kernel
.used
, incremental
);
681 ilo_err("failed to upload shaders\n");
685 hw3d
->kernel
.used
+= upload
;
687 assert(hw3d
->kernel
.used
<= hw3d
->kernel
.size
);
693 ilo_draw_vbo(struct pipe_context
*pipe
, const struct pipe_draw_info
*info
)
695 struct ilo_context
*ilo
= ilo_context(pipe
);
696 struct ilo_3d
*hw3d
= ilo
->hw3d
;
697 int prim_generated
, prim_emitted
;
699 if (ilo_debug
& ILO_DEBUG_DRAW
) {
701 ilo_printf("indexed draw %s: "
702 "index start %d, count %d, vertex range [%d, %d]\n",
703 u_prim_name(info
->mode
), info
->start
, info
->count
,
704 info
->min_index
, info
->max_index
);
707 ilo_printf("draw %s: vertex start %d, count %d\n",
708 u_prim_name(info
->mode
), info
->start
, info
->count
);
711 ilo_dump_dirty_flags(ilo
->dirty
);
714 if (!ilo_3d_pass_render_condition(ilo
))
717 if (info
->primitive_restart
&& info
->indexed
) {
719 * Want to draw an indexed primitive using primitive restart
720 * Check that HW can handle the request and fall to SW if not.
722 if (!ilo_check_restart_index(ilo
, info
->restart_index
) ||
723 !ilo_check_restart_prim_type(ilo
, info
->mode
)) {
724 ilo_draw_vbo_with_sw_restart(pipe
, info
);
729 ilo_finalize_3d_states(ilo
, info
);
731 if (!upload_shaders(hw3d
, ilo
->shader_cache
))
734 ilo_blit_resolve_framebuffer(ilo
);
736 /* If draw_vbo ever fails, return immediately. */
737 if (!draw_vbo(hw3d
, ilo
, &prim_generated
, &prim_emitted
))
740 /* clear dirty status */
742 hw3d
->new_batch
= false;
744 /* avoid dangling pointer reference */
747 update_prim_count(hw3d
, prim_generated
, prim_emitted
);
749 if (ilo_debug
& ILO_DEBUG_NOCACHE
)
750 ilo_3d_pipeline_emit_flush(hw3d
->pipeline
);
754 ilo_render_condition(struct pipe_context
*pipe
,
755 struct pipe_query
*query
,
759 struct ilo_context
*ilo
= ilo_context(pipe
);
760 struct ilo_3d
*hw3d
= ilo
->hw3d
;
762 /* reference count? */
763 hw3d
->render_condition
.query
= query
;
764 hw3d
->render_condition
.mode
= mode
;
765 hw3d
->render_condition
.cond
= condition
;
769 ilo_texture_barrier(struct pipe_context
*pipe
)
771 struct ilo_context
*ilo
= ilo_context(pipe
);
772 struct ilo_3d
*hw3d
= ilo
->hw3d
;
774 if (ilo
->cp
->ring
!= INTEL_RING_RENDER
)
777 ilo_3d_pipeline_emit_flush(hw3d
->pipeline
);
780 if (ilo
->dev
->gen
>= ILO_GEN(7))
781 ilo_cp_flush(hw3d
->cp
, "texture barrier");
785 ilo_get_sample_position(struct pipe_context
*pipe
,
786 unsigned sample_count
,
787 unsigned sample_index
,
790 struct ilo_context
*ilo
= ilo_context(pipe
);
791 struct ilo_3d
*hw3d
= ilo
->hw3d
;
793 ilo_3d_pipeline_get_sample_position(hw3d
->pipeline
,
794 sample_count
, sample_index
,
795 &out_value
[0], &out_value
[1]);
799 * Initialize 3D-related functions.
802 ilo_init_3d_functions(struct ilo_context
*ilo
)
804 ilo
->base
.draw_vbo
= ilo_draw_vbo
;
805 ilo
->base
.render_condition
= ilo_render_condition
;
806 ilo
->base
.texture_barrier
= ilo_texture_barrier
;
807 ilo
->base
.get_sample_position
= ilo_get_sample_position
;