2 * Copyright © 2007 Intel Corporation
3 * Copyright (C) 2012-2013 LunarG, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * Eric Anholt <eric@anholt.net>
26 * Chia-I Wu <olv@lunarg.com>
29 #include "intel_winsys.h"
32 #include "ilo_3d_pipeline.h"
34 #define PRINTFLIKE(f, a) _util_printf_format(f, a)
35 typedef short GLshort
;
37 typedef unsigned char GLubyte
;
38 typedef unsigned int GLuint
;
39 typedef float GLfloat
;
43 #include "brw_structs.h"
44 #include "brw_defines.h"
46 struct intel_context
{
57 struct intel_context intel
;
61 batch_out(struct brw_context
*brw
, const char *name
, uint32_t offset
,
62 int index
, char *fmt
, ...) PRINTFLIKE(5, 6);
65 batch_out(struct brw_context
*brw
, const char *name
, uint32_t offset
,
66 int index
, char *fmt
, ...)
68 struct intel_context
*intel
= &brw
->intel
;
69 uint32_t *data
= intel
->batch
.bo
->virtual + offset
;
72 fprintf(stderr
, "0x%08x: 0x%08x: %8s: ",
73 offset
+ index
* 4, data
[index
], name
);
75 vfprintf(stderr
, fmt
, va
);
80 get_965_surfacetype(unsigned int surfacetype
)
82 switch (surfacetype
) {
86 case 3: return "CUBE";
87 case 4: return "BUFFER";
88 case 7: return "NULL";
89 default: return "unknown";
94 get_965_surface_format(unsigned int surface_format
)
96 switch (surface_format
) {
97 case 0x000: return "r32g32b32a32_float";
98 case 0x0c1: return "b8g8r8a8_unorm";
99 case 0x100: return "b5g6r5_unorm";
100 case 0x102: return "b5g5r5a1_unorm";
101 case 0x104: return "b4g4r4a4_unorm";
102 default: return "unknown";
106 static void dump_vs_state(struct brw_context
*brw
, uint32_t offset
)
108 struct intel_context
*intel
= &brw
->intel
;
109 const char *name
= "VS_STATE";
110 struct brw_vs_unit_state
*vs
= intel
->batch
.bo
->virtual + offset
;
112 batch_out(brw
, name
, offset
, 0, "thread0\n");
113 batch_out(brw
, name
, offset
, 1, "thread1\n");
114 batch_out(brw
, name
, offset
, 2, "thread2\n");
115 batch_out(brw
, name
, offset
, 3, "thread3\n");
116 batch_out(brw
, name
, offset
, 4, "thread4: %d threads\n",
117 vs
->thread4
.max_threads
+ 1);
118 batch_out(brw
, name
, offset
, 5, "vs5\n");
119 batch_out(brw
, name
, offset
, 6, "vs6\n");
122 static void dump_gs_state(struct brw_context
*brw
, uint32_t offset
)
124 struct intel_context
*intel
= &brw
->intel
;
125 const char *name
= "GS_STATE";
126 struct brw_gs_unit_state
*gs
= intel
->batch
.bo
->virtual + offset
;
128 batch_out(brw
, name
, offset
, 0, "thread0\n");
129 batch_out(brw
, name
, offset
, 1, "thread1\n");
130 batch_out(brw
, name
, offset
, 2, "thread2\n");
131 batch_out(brw
, name
, offset
, 3, "thread3\n");
132 batch_out(brw
, name
, offset
, 4, "thread4: %d threads\n",
133 gs
->thread4
.max_threads
+ 1);
134 batch_out(brw
, name
, offset
, 5, "vs5\n");
135 batch_out(brw
, name
, offset
, 6, "vs6\n");
138 static void dump_clip_state(struct brw_context
*brw
, uint32_t offset
)
140 struct intel_context
*intel
= &brw
->intel
;
141 const char *name
= "CLIP_STATE";
142 struct brw_clip_unit_state
*clip
= intel
->batch
.bo
->virtual + offset
;
144 batch_out(brw
, name
, offset
, 0, "thread0\n");
145 batch_out(brw
, name
, offset
, 1, "thread1\n");
146 batch_out(brw
, name
, offset
, 2, "thread2\n");
147 batch_out(brw
, name
, offset
, 3, "thread3\n");
148 batch_out(brw
, name
, offset
, 4, "thread4: %d threads\n",
149 clip
->thread4
.max_threads
+ 1);
150 batch_out(brw
, name
, offset
, 5, "clip5\n");
151 batch_out(brw
, name
, offset
, 6, "clip6\n");
152 batch_out(brw
, name
, offset
, 7, "vp xmin %f\n", clip
->viewport_xmin
);
153 batch_out(brw
, name
, offset
, 8, "vp xmax %f\n", clip
->viewport_xmax
);
154 batch_out(brw
, name
, offset
, 9, "vp ymin %f\n", clip
->viewport_ymin
);
155 batch_out(brw
, name
, offset
, 10, "vp ymax %f\n", clip
->viewport_ymax
);
158 static void dump_sf_state(struct brw_context
*brw
, uint32_t offset
)
160 struct intel_context
*intel
= &brw
->intel
;
161 const char *name
= "SF_STATE";
162 struct brw_sf_unit_state
*sf
= intel
->batch
.bo
->virtual + offset
;
164 batch_out(brw
, name
, offset
, 0, "thread0\n");
165 batch_out(brw
, name
, offset
, 1, "thread1\n");
166 batch_out(brw
, name
, offset
, 2, "thread2\n");
167 batch_out(brw
, name
, offset
, 3, "thread3\n");
168 batch_out(brw
, name
, offset
, 4, "thread4: %d threads\n",
169 sf
->thread4
.max_threads
+ 1);
170 batch_out(brw
, name
, offset
, 5, "sf5: viewport offset\n");
171 batch_out(brw
, name
, offset
, 6, "sf6\n");
172 batch_out(brw
, name
, offset
, 7, "sf7\n");
175 static void dump_wm_state(struct brw_context
*brw
, uint32_t offset
)
177 struct intel_context
*intel
= &brw
->intel
;
178 const char *name
= "WM_STATE";
179 struct brw_wm_unit_state
*wm
= intel
->batch
.bo
->virtual + offset
;
181 batch_out(brw
, name
, offset
, 0, "thread0\n");
182 batch_out(brw
, name
, offset
, 1, "thread1\n");
183 batch_out(brw
, name
, offset
, 2, "thread2\n");
184 batch_out(brw
, name
, offset
, 3, "thread3\n");
185 batch_out(brw
, name
, offset
, 4, "wm4\n");
186 batch_out(brw
, name
, offset
, 5, "wm5: %s%s%s%s%s%s, %d threads\n",
187 wm
->wm5
.enable_8_pix
? "8pix" : "",
188 wm
->wm5
.enable_16_pix
? "16pix" : "",
189 wm
->wm5
.program_uses_depth
? ", uses depth" : "",
190 wm
->wm5
.program_computes_depth
? ", computes depth" : "",
191 wm
->wm5
.program_uses_killpixel
? ", kills" : "",
192 wm
->wm5
.thread_dispatch_enable
? "" : ", no dispatch",
193 wm
->wm5
.max_threads
+ 1);
194 batch_out(brw
, name
, offset
, 6, "depth offset constant %f\n",
195 wm
->global_depth_offset_constant
);
196 batch_out(brw
, name
, offset
, 7, "depth offset scale %f\n",
197 wm
->global_depth_offset_scale
);
198 batch_out(brw
, name
, offset
, 8, "wm8: kernel 1 (gen5+)\n");
199 batch_out(brw
, name
, offset
, 9, "wm9: kernel 2 (gen5+)\n");
200 batch_out(brw
, name
, offset
, 10, "wm10: kernel 3 (gen5+)\n");
203 static void dump_surface_state(struct brw_context
*brw
, uint32_t offset
)
205 const char *name
= "SURF";
206 uint32_t *surf
= brw
->intel
.batch
.bo
->virtual + offset
;
208 batch_out(brw
, name
, offset
, 0, "%s %s\n",
209 get_965_surfacetype(GET_FIELD(surf
[0], BRW_SURFACE_TYPE
)),
210 get_965_surface_format(GET_FIELD(surf
[0], BRW_SURFACE_FORMAT
)));
211 batch_out(brw
, name
, offset
, 1, "offset\n");
212 batch_out(brw
, name
, offset
, 2, "%dx%d size, %d mips\n",
213 GET_FIELD(surf
[2], BRW_SURFACE_WIDTH
) + 1,
214 GET_FIELD(surf
[2], BRW_SURFACE_HEIGHT
) + 1,
215 GET_FIELD(surf
[2], BRW_SURFACE_LOD
));
216 batch_out(brw
, name
, offset
, 3, "pitch %d, %s tiled\n",
217 GET_FIELD(surf
[3], BRW_SURFACE_PITCH
) + 1,
218 (surf
[3] & BRW_SURFACE_TILED
) ?
219 ((surf
[3] & BRW_SURFACE_TILED_Y
) ? "Y" : "X") : "not");
220 batch_out(brw
, name
, offset
, 4, "mip base %d\n",
221 GET_FIELD(surf
[4], BRW_SURFACE_MIN_LOD
));
222 batch_out(brw
, name
, offset
, 5, "x,y offset: %d,%d\n",
223 GET_FIELD(surf
[5], BRW_SURFACE_X_OFFSET
),
224 GET_FIELD(surf
[5], BRW_SURFACE_Y_OFFSET
));
227 static void dump_gen7_surface_state(struct brw_context
*brw
, uint32_t offset
)
229 const char *name
= "SURF";
230 uint32_t *surf
= brw
->intel
.batch
.bo
->virtual + offset
;
232 batch_out(brw
, name
, offset
, 0, "%s %s\n",
233 get_965_surfacetype(GET_FIELD(surf
[0], BRW_SURFACE_TYPE
)),
234 get_965_surface_format(GET_FIELD(surf
[0], BRW_SURFACE_FORMAT
)));
235 batch_out(brw
, name
, offset
, 1, "offset\n");
236 batch_out(brw
, name
, offset
, 2, "%dx%d size, %d mips\n",
237 GET_FIELD(surf
[2], GEN7_SURFACE_WIDTH
) + 1,
238 GET_FIELD(surf
[2], GEN7_SURFACE_HEIGHT
) + 1,
239 surf
[5] & INTEL_MASK(3, 0));
240 batch_out(brw
, name
, offset
, 3, "pitch %d, %stiled\n",
241 (surf
[3] & INTEL_MASK(17, 0)) + 1,
242 (surf
[0] & (1 << 14)) ? "" : "not ");
243 batch_out(brw
, name
, offset
, 4, "mip base %d\n",
244 GET_FIELD(surf
[5], GEN7_SURFACE_MIN_LOD
));
245 batch_out(brw
, name
, offset
, 5, "x,y offset: %d,%d\n",
246 GET_FIELD(surf
[5], BRW_SURFACE_X_OFFSET
),
247 GET_FIELD(surf
[5], BRW_SURFACE_Y_OFFSET
));
251 dump_sdc(struct brw_context
*brw
, uint32_t offset
)
253 const char *name
= "SDC";
254 struct intel_context
*intel
= &brw
->intel
;
256 if (intel
->gen
>= 5 && intel
->gen
<= 6) {
257 struct gen5_sampler_default_color
*sdc
= (intel
->batch
.bo
->virtual +
259 batch_out(brw
, name
, offset
, 0, "unorm rgba\n");
260 batch_out(brw
, name
, offset
, 1, "r %f\n", sdc
->f
[0]);
261 batch_out(brw
, name
, offset
, 2, "b %f\n", sdc
->f
[1]);
262 batch_out(brw
, name
, offset
, 3, "g %f\n", sdc
->f
[2]);
263 batch_out(brw
, name
, offset
, 4, "a %f\n", sdc
->f
[3]);
264 batch_out(brw
, name
, offset
, 5, "half float rg\n");
265 batch_out(brw
, name
, offset
, 6, "half float ba\n");
266 batch_out(brw
, name
, offset
, 7, "u16 rg\n");
267 batch_out(brw
, name
, offset
, 8, "u16 ba\n");
268 batch_out(brw
, name
, offset
, 9, "s16 rg\n");
269 batch_out(brw
, name
, offset
, 10, "s16 ba\n");
270 batch_out(brw
, name
, offset
, 11, "s8 rgba\n");
272 struct brw_sampler_default_color
*sdc
= (intel
->batch
.bo
->virtual +
274 batch_out(brw
, name
, offset
, 0, "r %f\n", sdc
->color
[0]);
275 batch_out(brw
, name
, offset
, 1, "g %f\n", sdc
->color
[1]);
276 batch_out(brw
, name
, offset
, 2, "b %f\n", sdc
->color
[2]);
277 batch_out(brw
, name
, offset
, 3, "a %f\n", sdc
->color
[3]);
281 static void dump_sampler_state(struct brw_context
*brw
,
282 uint32_t offset
, uint32_t size
)
284 struct intel_context
*intel
= &brw
->intel
;
286 struct brw_sampler_state
*samp
= intel
->batch
.bo
->virtual + offset
;
288 assert(intel
->gen
< 7);
290 for (i
= 0; i
< size
/ sizeof(*samp
); i
++) {
293 sprintf(name
, "WM SAMP%d", i
);
294 batch_out(brw
, name
, offset
, 0, "filtering\n");
295 batch_out(brw
, name
, offset
, 1, "wrapping, lod\n");
296 batch_out(brw
, name
, offset
, 2, "default color pointer\n");
297 batch_out(brw
, name
, offset
, 3, "chroma key, aniso\n");
300 offset
+= sizeof(*samp
);
304 static void dump_gen7_sampler_state(struct brw_context
*brw
,
305 uint32_t offset
, uint32_t size
)
307 struct intel_context
*intel
= &brw
->intel
;
308 struct gen7_sampler_state
*samp
= intel
->batch
.bo
->virtual + offset
;
311 assert(intel
->gen
>= 7);
313 for (i
= 0; i
< size
/ sizeof(*samp
); i
++) {
316 sprintf(name
, "WM SAMP%d", i
);
317 batch_out(brw
, name
, offset
, 0, "filtering\n");
318 batch_out(brw
, name
, offset
, 1, "wrapping, lod\n");
319 batch_out(brw
, name
, offset
, 2, "default color pointer\n");
320 batch_out(brw
, name
, offset
, 3, "chroma key, aniso\n");
323 offset
+= sizeof(*samp
);
328 static void dump_sf_viewport_state(struct brw_context
*brw
,
331 struct intel_context
*intel
= &brw
->intel
;
332 const char *name
= "SF VP";
333 struct brw_sf_viewport
*vp
= intel
->batch
.bo
->virtual + offset
;
335 assert(intel
->gen
< 7);
337 batch_out(brw
, name
, offset
, 0, "m00 = %f\n", vp
->viewport
.m00
);
338 batch_out(brw
, name
, offset
, 1, "m11 = %f\n", vp
->viewport
.m11
);
339 batch_out(brw
, name
, offset
, 2, "m22 = %f\n", vp
->viewport
.m22
);
340 batch_out(brw
, name
, offset
, 3, "m30 = %f\n", vp
->viewport
.m30
);
341 batch_out(brw
, name
, offset
, 4, "m31 = %f\n", vp
->viewport
.m31
);
342 batch_out(brw
, name
, offset
, 5, "m32 = %f\n", vp
->viewport
.m32
);
344 batch_out(brw
, name
, offset
, 6, "top left = %d,%d\n",
345 vp
->scissor
.xmin
, vp
->scissor
.ymin
);
346 batch_out(brw
, name
, offset
, 7, "bottom right = %d,%d\n",
347 vp
->scissor
.xmax
, vp
->scissor
.ymax
);
350 static void dump_clip_viewport_state(struct brw_context
*brw
,
353 struct intel_context
*intel
= &brw
->intel
;
354 const char *name
= "CLIP VP";
355 struct brw_clipper_viewport
*vp
= intel
->batch
.bo
->virtual + offset
;
357 assert(intel
->gen
< 7);
359 batch_out(brw
, name
, offset
, 0, "xmin = %f\n", vp
->xmin
);
360 batch_out(brw
, name
, offset
, 1, "xmax = %f\n", vp
->xmax
);
361 batch_out(brw
, name
, offset
, 2, "ymin = %f\n", vp
->ymin
);
362 batch_out(brw
, name
, offset
, 3, "ymax = %f\n", vp
->ymax
);
365 static void dump_sf_clip_viewport_state(struct brw_context
*brw
,
368 struct intel_context
*intel
= &brw
->intel
;
369 const char *name
= "SF_CLIP VP";
370 struct gen7_sf_clip_viewport
*vp
= intel
->batch
.bo
->virtual + offset
;
372 assert(intel
->gen
>= 7);
374 batch_out(brw
, name
, offset
, 0, "m00 = %f\n", vp
->viewport
.m00
);
375 batch_out(brw
, name
, offset
, 1, "m11 = %f\n", vp
->viewport
.m11
);
376 batch_out(brw
, name
, offset
, 2, "m22 = %f\n", vp
->viewport
.m22
);
377 batch_out(brw
, name
, offset
, 3, "m30 = %f\n", vp
->viewport
.m30
);
378 batch_out(brw
, name
, offset
, 4, "m31 = %f\n", vp
->viewport
.m31
);
379 batch_out(brw
, name
, offset
, 5, "m32 = %f\n", vp
->viewport
.m32
);
380 batch_out(brw
, name
, offset
, 6, "guardband xmin = %f\n", vp
->guardband
.xmin
);
381 batch_out(brw
, name
, offset
, 7, "guardband xmax = %f\n", vp
->guardband
.xmax
);
382 batch_out(brw
, name
, offset
, 8, "guardband ymin = %f\n", vp
->guardband
.ymin
);
383 batch_out(brw
, name
, offset
, 9, "guardband ymax = %f\n", vp
->guardband
.ymax
);
387 static void dump_cc_viewport_state(struct brw_context
*brw
, uint32_t offset
)
389 const char *name
= "CC VP";
390 struct brw_cc_viewport
*vp
= brw
->intel
.batch
.bo
->virtual + offset
;
392 batch_out(brw
, name
, offset
, 0, "min_depth = %f\n", vp
->min_depth
);
393 batch_out(brw
, name
, offset
, 1, "max_depth = %f\n", vp
->max_depth
);
396 static void dump_depth_stencil_state(struct brw_context
*brw
, uint32_t offset
)
398 const char *name
= "D_S";
399 struct gen6_depth_stencil_state
*ds
= brw
->intel
.batch
.bo
->virtual + offset
;
401 batch_out(brw
, name
, offset
, 0,
402 "stencil %sable, func %d, write %sable\n",
403 ds
->ds0
.stencil_enable
? "en" : "dis",
404 ds
->ds0
.stencil_func
,
405 ds
->ds0
.stencil_write_enable
? "en" : "dis");
406 batch_out(brw
, name
, offset
, 1,
407 "stencil test mask 0x%x, write mask 0x%x\n",
408 ds
->ds1
.stencil_test_mask
, ds
->ds1
.stencil_write_mask
);
409 batch_out(brw
, name
, offset
, 2,
410 "depth test %sable, func %d, write %sable\n",
411 ds
->ds2
.depth_test_enable
? "en" : "dis",
412 ds
->ds2
.depth_test_func
,
413 ds
->ds2
.depth_write_enable
? "en" : "dis");
416 static void dump_cc_state_gen4(struct brw_context
*brw
, uint32_t offset
)
418 const char *name
= "CC";
420 batch_out(brw
, name
, offset
, 0, "cc0\n");
421 batch_out(brw
, name
, offset
, 1, "cc1\n");
422 batch_out(brw
, name
, offset
, 2, "cc2\n");
423 batch_out(brw
, name
, offset
, 3, "cc3\n");
424 batch_out(brw
, name
, offset
, 4, "cc4: viewport offset\n");
425 batch_out(brw
, name
, offset
, 5, "cc5\n");
426 batch_out(brw
, name
, offset
, 6, "cc6\n");
427 batch_out(brw
, name
, offset
, 7, "cc7\n");
430 static void dump_cc_state_gen6(struct brw_context
*brw
, uint32_t offset
)
432 const char *name
= "CC";
433 struct gen6_color_calc_state
*cc
= brw
->intel
.batch
.bo
->virtual + offset
;
435 batch_out(brw
, name
, offset
, 0,
436 "alpha test format %s, round disable %d, stencil ref %d, "
437 "bf stencil ref %d\n",
438 cc
->cc0
.alpha_test_format
? "FLOAT32" : "UNORM8",
439 cc
->cc0
.round_disable
,
441 cc
->cc0
.bf_stencil_ref
);
442 batch_out(brw
, name
, offset
, 1, "\n");
443 batch_out(brw
, name
, offset
, 2, "constant red %f\n", cc
->constant_r
);
444 batch_out(brw
, name
, offset
, 3, "constant green %f\n", cc
->constant_g
);
445 batch_out(brw
, name
, offset
, 4, "constant blue %f\n", cc
->constant_b
);
446 batch_out(brw
, name
, offset
, 5, "constant alpha %f\n", cc
->constant_a
);
449 static void dump_blend_state(struct brw_context
*brw
, uint32_t offset
)
451 const char *name
= "BLEND";
453 batch_out(brw
, name
, offset
, 0, "\n");
454 batch_out(brw
, name
, offset
, 1, "\n");
458 dump_scissor(struct brw_context
*brw
, uint32_t offset
)
460 const char *name
= "SCISSOR";
461 struct intel_context
*intel
= &brw
->intel
;
462 struct gen6_scissor_rect
*scissor
= intel
->batch
.bo
->virtual + offset
;
464 batch_out(brw
, name
, offset
, 0, "xmin %d, ymin %d\n",
465 scissor
->xmin
, scissor
->ymin
);
466 batch_out(brw
, name
, offset
, 1, "xmax %d, ymax %d\n",
467 scissor
->xmax
, scissor
->ymax
);
471 dump_vs_constants(struct brw_context
*brw
, uint32_t offset
, uint32_t size
)
473 const char *name
= "VS_CONST";
474 struct intel_context
*intel
= &brw
->intel
;
475 uint32_t *as_uint
= intel
->batch
.bo
->virtual + offset
;
476 float *as_float
= intel
->batch
.bo
->virtual + offset
;
479 for (i
= 0; i
< size
/ 4; i
+= 4) {
480 batch_out(brw
, name
, offset
, i
, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
482 as_float
[i
], as_float
[i
+ 1], as_float
[i
+ 2], as_float
[i
+ 3],
483 as_uint
[i
], as_uint
[i
+ 1], as_uint
[i
+ 2], as_uint
[i
+ 3]);
488 dump_wm_constants(struct brw_context
*brw
, uint32_t offset
, uint32_t size
)
490 const char *name
= "WM_CONST";
491 struct intel_context
*intel
= &brw
->intel
;
492 uint32_t *as_uint
= intel
->batch
.bo
->virtual + offset
;
493 float *as_float
= intel
->batch
.bo
->virtual + offset
;
496 for (i
= 0; i
< size
/ 4; i
+= 4) {
497 batch_out(brw
, name
, offset
, i
, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
499 as_float
[i
], as_float
[i
+ 1], as_float
[i
+ 2], as_float
[i
+ 3],
500 as_uint
[i
], as_uint
[i
+ 1], as_uint
[i
+ 2], as_uint
[i
+ 3]);
504 static void dump_binding_table(struct brw_context
*brw
, uint32_t offset
,
509 uint32_t *data
= brw
->intel
.batch
.bo
->virtual + offset
;
511 for (i
= 0; i
< size
/ 4; i
++) {
515 sprintf(name
, "BIND%d", i
);
516 batch_out(brw
, name
, offset
, i
, "surface state address\n");
521 init_brw(struct brw_context
*brw
, struct ilo_3d_pipeline
*p
)
523 brw
->intel
.gen
= ILO_GEN_GET_MAJOR(p
->dev
->gen
);
524 brw
->intel
.batch
.bo
= &brw
->intel
.batch
.bo_dst
;
526 brw
->intel
.batch
.bo_dst
.virtual = intel_bo_map(p
->cp
->bo
, false);
527 if (!brw
->intel
.batch
.bo_dst
.virtual)
534 dump_3d_state(struct ilo_3d_pipeline
*p
)
536 struct brw_context brw
;
539 if (!init_brw(&brw
, p
))
542 if (brw
.intel
.gen
>= 7) {
543 dump_cc_viewport_state(&brw
, p
->state
.CC_VIEWPORT
);
544 dump_sf_clip_viewport_state(&brw
, p
->state
.SF_CLIP_VIEWPORT
);
547 dump_clip_viewport_state(&brw
, p
->state
.CLIP_VIEWPORT
);
548 dump_sf_viewport_state(&brw
, p
->state
.SF_VIEWPORT
);
549 dump_cc_viewport_state(&brw
, p
->state
.CC_VIEWPORT
);
552 dump_blend_state(&brw
, p
->state
.BLEND_STATE
);
553 dump_cc_state_gen6(&brw
, p
->state
.COLOR_CALC_STATE
);
554 dump_depth_stencil_state(&brw
, p
->state
.DEPTH_STENCIL_STATE
);
557 num_states
= p
->state
.vs
.BINDING_TABLE_STATE_size
;
558 for (i
= 0; i
< num_states
; i
++) {
559 if (brw
.intel
.gen
< 7)
560 dump_surface_state(&brw
, p
->state
.vs
.SURFACE_STATE
[i
]);
562 dump_gen7_surface_state(&brw
, p
->state
.vs
.SURFACE_STATE
[i
]);
564 dump_binding_table(&brw
, p
->state
.vs
.BINDING_TABLE_STATE
, num_states
* 4);
567 for (i
= 0; i
< Elements(p
->state
.vs
.SAMPLER_BORDER_COLOR_STATE
); i
++) {
568 if (!p
->state
.vs
.SAMPLER_BORDER_COLOR_STATE
[i
])
571 dump_sdc(&brw
, p
->state
.vs
.SAMPLER_BORDER_COLOR_STATE
[i
]);
574 if (brw
.intel
.gen
< 7)
575 dump_sampler_state(&brw
, p
->state
.vs
.SAMPLER_STATE
, num_states
* 16);
577 dump_gen7_sampler_state(&brw
, p
->state
.vs
.SAMPLER_STATE
, num_states
* 16);
579 if (p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
) {
580 dump_vs_constants(&brw
, p
->state
.vs
.PUSH_CONSTANT_BUFFER
,
581 p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
);
585 num_states
= p
->state
.gs
.BINDING_TABLE_STATE_size
;
586 for (i
= 0; i
< num_states
; i
++) {
587 if (!p
->state
.gs
.SURFACE_STATE
[i
])
590 if (brw
.intel
.gen
< 7)
591 dump_surface_state(&brw
, p
->state
.gs
.SURFACE_STATE
[i
]);
593 dump_gen7_surface_state(&brw
, p
->state
.gs
.SURFACE_STATE
[i
]);
595 dump_binding_table(&brw
, p
->state
.gs
.BINDING_TABLE_STATE
, num_states
* 4);
598 num_states
= p
->state
.wm
.BINDING_TABLE_STATE_size
;
599 for (i
= 0; i
< num_states
; i
++) {
600 if (!p
->state
.wm
.SURFACE_STATE
[i
])
603 if (brw
.intel
.gen
< 7)
604 dump_surface_state(&brw
, p
->state
.wm
.SURFACE_STATE
[i
]);
606 dump_gen7_surface_state(&brw
, p
->state
.wm
.SURFACE_STATE
[i
]);
608 dump_binding_table(&brw
, p
->state
.wm
.BINDING_TABLE_STATE
, num_states
* 4);
611 for (i
= 0; i
< Elements(p
->state
.wm
.SAMPLER_BORDER_COLOR_STATE
); i
++) {
612 if (!p
->state
.wm
.SAMPLER_BORDER_COLOR_STATE
[i
])
615 dump_sdc(&brw
, p
->state
.wm
.SAMPLER_BORDER_COLOR_STATE
[i
]);
618 if (brw
.intel
.gen
< 7)
619 dump_sampler_state(&brw
, p
->state
.wm
.SAMPLER_STATE
, num_states
* 16);
621 dump_gen7_sampler_state(&brw
, p
->state
.wm
.SAMPLER_STATE
, num_states
* 16);
623 if (p
->state
.wm
.PUSH_CONSTANT_BUFFER_size
) {
624 dump_wm_constants(&brw
, p
->state
.wm
.PUSH_CONSTANT_BUFFER
,
625 p
->state
.wm
.PUSH_CONSTANT_BUFFER_size
);
628 dump_scissor(&brw
, p
->state
.SCISSOR_RECT
);
630 (void) dump_vs_state
;
631 (void) dump_gs_state
;
632 (void) dump_clip_state
;
633 (void) dump_sf_state
;
634 (void) dump_wm_state
;
635 (void) dump_cc_state_gen4
;
637 intel_bo_unmap(p
->cp
->bo
);
644 ilo_3d_pipeline_dump(struct ilo_3d_pipeline
*p
)