2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_prim.h"
32 #include "ilo_blitter.h"
34 #include "ilo_context.h"
36 #include "ilo_gpe_gen6.h"
37 #include "ilo_gpe_gen7.h"
38 #include "ilo_shader.h"
39 #include "ilo_state.h"
40 #include "ilo_3d_pipeline.h"
41 #include "ilo_3d_pipeline_gen6.h"
44 * This should be called before any depth stall flush (including those
45 * produced by non-pipelined state commands) or cache flush on GEN6.
47 * \see intel_emit_post_sync_nonzero_flush()
50 gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline
*p
,
51 bool caller_post_sync
)
53 assert(p
->dev
->gen
== ILO_GEN(6));
56 if (p
->state
.has_gen6_wa_pipe_control
)
59 p
->state
.has_gen6_wa_pipe_control
= true;
62 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
64 * "Pipe-control with CS-stall bit set must be sent BEFORE the
65 * pipe-control with a post-sync op and no write-cache flushes."
67 * The workaround below necessitates this workaround.
69 gen6_emit_PIPE_CONTROL(p
->dev
,
70 GEN6_PIPE_CONTROL_CS_STALL
|
71 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
,
72 NULL
, 0, false, p
->cp
);
74 /* the caller will emit the post-sync op */
79 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
81 * "Before any depth stall flush (including those produced by
82 * non-pipelined state commands), software needs to first send a
83 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
85 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
86 * PIPE_CONTROL with any non-zero post-sync-op is required."
88 gen6_emit_PIPE_CONTROL(p
->dev
,
89 GEN6_PIPE_CONTROL_WRITE_IMM
,
90 p
->workaround_bo
, 0, false, p
->cp
);
94 gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline
*p
)
96 assert(p
->dev
->gen
== ILO_GEN(6));
98 gen6_wa_pipe_control_post_sync(p
, false);
101 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
103 * "Driver must guarentee that all the caches in the depth pipe are
104 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
105 * requires driver to send a PIPE_CONTROL with a CS stall along with a
106 * Depth Flush prior to this command."
108 gen6_emit_PIPE_CONTROL(p
->dev
,
109 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
110 GEN6_PIPE_CONTROL_CS_STALL
,
115 gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline
*p
)
117 assert(p
->dev
->gen
== ILO_GEN(6));
119 gen6_wa_pipe_control_post_sync(p
, false);
122 * According to intel_emit_depth_stall_flushes() of classic i965, we need
123 * to emit a sequence of PIPE_CONTROLs prior to emitting depth related
126 gen6_emit_PIPE_CONTROL(p
->dev
,
127 GEN6_PIPE_CONTROL_DEPTH_STALL
,
128 NULL
, 0, false, p
->cp
);
130 gen6_emit_PIPE_CONTROL(p
->dev
,
131 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
,
132 NULL
, 0, false, p
->cp
);
134 gen6_emit_PIPE_CONTROL(p
->dev
,
135 GEN6_PIPE_CONTROL_DEPTH_STALL
,
136 NULL
, 0, false, p
->cp
);
140 gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline
*p
)
142 assert(p
->dev
->gen
== ILO_GEN(6));
144 /* the post-sync workaround should cover this already */
145 if (p
->state
.has_gen6_wa_pipe_control
)
149 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
151 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
152 * field set (DW1 Bit 1), must be issued prior to any change to the
153 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
155 gen6_emit_PIPE_CONTROL(p
->dev
,
156 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
,
157 NULL
, 0, false, p
->cp
);
162 gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline
*p
)
164 assert(p
->dev
->gen
== ILO_GEN(6));
166 gen6_wa_pipe_control_post_sync(p
, false);
169 * According to upload_vs_state() of classic i965, we need to emit
170 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
171 * buffered by VS FF, to the point that the FF dies.
173 gen6_emit_PIPE_CONTROL(p
->dev
,
174 GEN6_PIPE_CONTROL_DEPTH_STALL
|
175 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
176 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
,
177 NULL
, 0, false, p
->cp
);
180 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
183 gen6_pipeline_common_select(struct ilo_3d_pipeline
*p
,
184 const struct ilo_context
*ilo
,
185 struct gen6_pipeline_session
*session
)
187 /* PIPELINE_SELECT */
188 if (session
->hw_ctx_changed
) {
189 if (p
->dev
->gen
== ILO_GEN(6))
190 gen6_wa_pipe_control_post_sync(p
, false);
192 gen6_emit_PIPELINE_SELECT(p
->dev
, 0x0, p
->cp
);
197 gen6_pipeline_common_sip(struct ilo_3d_pipeline
*p
,
198 const struct ilo_context
*ilo
,
199 struct gen6_pipeline_session
*session
)
202 if (session
->hw_ctx_changed
) {
203 if (p
->dev
->gen
== ILO_GEN(6))
204 gen6_wa_pipe_control_post_sync(p
, false);
206 gen6_emit_STATE_SIP(p
->dev
, 0, p
->cp
);
211 gen6_pipeline_common_base_address(struct ilo_3d_pipeline
*p
,
212 const struct ilo_context
*ilo
,
213 struct gen6_pipeline_session
*session
)
215 /* STATE_BASE_ADDRESS */
216 if (session
->state_bo_changed
|| session
->kernel_bo_changed
||
217 session
->batch_bo_changed
) {
218 if (p
->dev
->gen
== ILO_GEN(6))
219 gen6_wa_pipe_control_post_sync(p
, false);
221 gen6_emit_STATE_BASE_ADDRESS(p
->dev
,
222 NULL
, p
->cp
->bo
, p
->cp
->bo
, NULL
, ilo
->hw3d
->kernel
.bo
,
226 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
228 * "The following commands must be reissued following any change to
229 * the base addresses:
231 * * 3DSTATE_BINDING_TABLE_POINTERS
232 * * 3DSTATE_SAMPLER_STATE_POINTERS
233 * * 3DSTATE_VIEWPORT_STATE_POINTERS
234 * * 3DSTATE_CC_POINTERS
235 * * MEDIA_STATE_POINTERS"
237 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
238 * reasonable to also reissue the command. Same to PCB.
240 session
->viewport_state_changed
= true;
242 session
->cc_state_blend_changed
= true;
243 session
->cc_state_dsa_changed
= true;
244 session
->cc_state_cc_changed
= true;
246 session
->scissor_state_changed
= true;
248 session
->binding_table_vs_changed
= true;
249 session
->binding_table_gs_changed
= true;
250 session
->binding_table_fs_changed
= true;
252 session
->sampler_state_vs_changed
= true;
253 session
->sampler_state_gs_changed
= true;
254 session
->sampler_state_fs_changed
= true;
256 session
->pcb_state_vs_changed
= true;
257 session
->pcb_state_gs_changed
= true;
258 session
->pcb_state_fs_changed
= true;
263 gen6_pipeline_common_urb(struct ilo_3d_pipeline
*p
,
264 const struct ilo_context
*ilo
,
265 struct gen6_pipeline_session
*session
)
268 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
269 const bool gs_active
= (ilo
->gs
|| (ilo
->vs
&&
270 ilo_shader_get_kernel_param(ilo
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
271 int vs_entry_size
, gs_entry_size
;
272 int vs_total_size
, gs_total_size
;
274 vs_entry_size
= (ilo
->vs
) ?
275 ilo_shader_get_kernel_param(ilo
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
278 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
279 * share VUE handles. The VUE allocation size must be large enough to
280 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
282 * I am not sure if the PRM explicitly states that VF and VS share VUE
283 * handles. But here is a citation that implies so:
285 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
287 * "Once a FF stage that spawn threads has sufficient input to
288 * initiate a thread, it must guarantee that it is safe to request
289 * the thread initiation. For all these FF stages, this check is
292 * - The availability of output URB entries:
293 * - VS: As the input URB entries are overwritten with the
294 * VS-generated output data, output URB availability isn't a
297 if (vs_entry_size
< ilo
->ve
->count
)
298 vs_entry_size
= ilo
->ve
->count
;
300 gs_entry_size
= (ilo
->gs
) ?
301 ilo_shader_get_kernel_param(ilo
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
302 (gs_active
) ? vs_entry_size
: 0;
305 vs_entry_size
*= sizeof(float) * 4;
306 gs_entry_size
*= sizeof(float) * 4;
307 vs_total_size
= ilo
->dev
->urb_size
;
311 gs_total_size
= vs_total_size
;
317 gen6_emit_3DSTATE_URB(p
->dev
, vs_total_size
, gs_total_size
,
318 vs_entry_size
, gs_entry_size
, p
->cp
);
321 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
323 * "Because of a urb corruption caused by allocating a previous
324 * gsunit's urb entry to vsunit software is required to send a
325 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
326 * size == 0) plus a dummy DRAW call before any case where VS will
327 * be taking over GS URB space."
329 if (p
->state
.gs
.active
&& !gs_active
)
330 ilo_3d_pipeline_emit_flush_gen6(p
);
332 p
->state
.gs
.active
= gs_active
;
337 gen6_pipeline_common_pointers_1(struct ilo_3d_pipeline
*p
,
338 const struct ilo_context
*ilo
,
339 struct gen6_pipeline_session
*session
)
341 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
342 if (session
->viewport_state_changed
) {
343 gen6_emit_3DSTATE_VIEWPORT_STATE_POINTERS(p
->dev
,
344 p
->state
.CLIP_VIEWPORT
,
345 p
->state
.SF_VIEWPORT
,
346 p
->state
.CC_VIEWPORT
, p
->cp
);
351 gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline
*p
,
352 const struct ilo_context
*ilo
,
353 struct gen6_pipeline_session
*session
)
355 /* 3DSTATE_CC_STATE_POINTERS */
356 if (session
->cc_state_blend_changed
||
357 session
->cc_state_dsa_changed
||
358 session
->cc_state_cc_changed
) {
359 gen6_emit_3DSTATE_CC_STATE_POINTERS(p
->dev
,
360 p
->state
.BLEND_STATE
,
361 p
->state
.DEPTH_STENCIL_STATE
,
362 p
->state
.COLOR_CALC_STATE
, p
->cp
);
365 /* 3DSTATE_SAMPLER_STATE_POINTERS */
366 if (session
->sampler_state_vs_changed
||
367 session
->sampler_state_gs_changed
||
368 session
->sampler_state_fs_changed
) {
369 gen6_emit_3DSTATE_SAMPLER_STATE_POINTERS(p
->dev
,
370 p
->state
.vs
.SAMPLER_STATE
,
372 p
->state
.wm
.SAMPLER_STATE
, p
->cp
);
377 gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline
*p
,
378 const struct ilo_context
*ilo
,
379 struct gen6_pipeline_session
*session
)
381 /* 3DSTATE_SCISSOR_STATE_POINTERS */
382 if (session
->scissor_state_changed
) {
383 gen6_emit_3DSTATE_SCISSOR_STATE_POINTERS(p
->dev
,
384 p
->state
.SCISSOR_RECT
, p
->cp
);
387 /* 3DSTATE_BINDING_TABLE_POINTERS */
388 if (session
->binding_table_vs_changed
||
389 session
->binding_table_gs_changed
||
390 session
->binding_table_fs_changed
) {
391 gen6_emit_3DSTATE_BINDING_TABLE_POINTERS(p
->dev
,
392 p
->state
.vs
.BINDING_TABLE_STATE
,
393 p
->state
.gs
.BINDING_TABLE_STATE
,
394 p
->state
.wm
.BINDING_TABLE_STATE
, p
->cp
);
399 gen6_pipeline_vf(struct ilo_3d_pipeline
*p
,
400 const struct ilo_context
*ilo
,
401 struct gen6_pipeline_session
*session
)
403 if (p
->dev
->gen
>= ILO_GEN(7.5)) {
404 /* 3DSTATE_INDEX_BUFFER */
405 if (DIRTY(IB
) || session
->batch_bo_changed
) {
406 gen6_emit_3DSTATE_INDEX_BUFFER(p
->dev
,
407 &ilo
->ib
, false, p
->cp
);
411 if (session
->primitive_restart_changed
) {
412 gen7_emit_3DSTATE_VF(p
->dev
, ilo
->draw
->primitive_restart
,
413 ilo
->draw
->restart_index
, p
->cp
);
417 /* 3DSTATE_INDEX_BUFFER */
418 if (DIRTY(IB
) || session
->primitive_restart_changed
||
419 session
->batch_bo_changed
) {
420 gen6_emit_3DSTATE_INDEX_BUFFER(p
->dev
,
421 &ilo
->ib
, ilo
->draw
->primitive_restart
, p
->cp
);
425 /* 3DSTATE_VERTEX_BUFFERS */
426 if (DIRTY(VB
) || DIRTY(VE
) || session
->batch_bo_changed
)
427 gen6_emit_3DSTATE_VERTEX_BUFFERS(p
->dev
, ilo
->ve
, &ilo
->vb
, p
->cp
);
429 /* 3DSTATE_VERTEX_ELEMENTS */
430 if (DIRTY(VE
) || DIRTY(VS
)) {
431 const struct ilo_ve_state
*ve
= ilo
->ve
;
432 bool last_velement_edgeflag
= false;
433 bool prepend_generate_ids
= false;
436 if (ilo_shader_get_kernel_param(ilo
->vs
,
437 ILO_KERNEL_VS_INPUT_EDGEFLAG
)) {
438 /* we rely on the state tracker here */
439 assert(ilo_shader_get_kernel_param(ilo
->vs
,
440 ILO_KERNEL_INPUT_COUNT
) == ve
->count
);
442 last_velement_edgeflag
= true;
445 if (ilo_shader_get_kernel_param(ilo
->vs
,
446 ILO_KERNEL_VS_INPUT_INSTANCEID
) ||
447 ilo_shader_get_kernel_param(ilo
->vs
,
448 ILO_KERNEL_VS_INPUT_VERTEXID
))
449 prepend_generate_ids
= true;
452 gen6_emit_3DSTATE_VERTEX_ELEMENTS(p
->dev
, ve
,
453 last_velement_edgeflag
, prepend_generate_ids
, p
->cp
);
458 gen6_pipeline_vf_statistics(struct ilo_3d_pipeline
*p
,
459 const struct ilo_context
*ilo
,
460 struct gen6_pipeline_session
*session
)
462 /* 3DSTATE_VF_STATISTICS */
463 if (session
->hw_ctx_changed
)
464 gen6_emit_3DSTATE_VF_STATISTICS(p
->dev
, false, p
->cp
);
468 gen6_pipeline_vf_draw(struct ilo_3d_pipeline
*p
,
469 const struct ilo_context
*ilo
,
470 struct gen6_pipeline_session
*session
)
473 gen6_emit_3DPRIMITIVE(p
->dev
, ilo
->draw
, &ilo
->ib
, false, p
->cp
);
474 p
->state
.has_gen6_wa_pipe_control
= false;
478 gen6_pipeline_vs(struct ilo_3d_pipeline
*p
,
479 const struct ilo_context
*ilo
,
480 struct gen6_pipeline_session
*session
)
482 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(SAMPLER_VS
) ||
483 session
->kernel_bo_changed
);
484 const bool emit_3dstate_constant_vs
= session
->pcb_state_vs_changed
;
487 * the classic i965 does this in upload_vs_state(), citing a spec that I
490 if (emit_3dstate_vs
&& p
->dev
->gen
== ILO_GEN(6))
491 gen6_wa_pipe_control_post_sync(p
, false);
493 /* 3DSTATE_CONSTANT_VS */
494 if (emit_3dstate_constant_vs
) {
495 gen6_emit_3DSTATE_CONSTANT_VS(p
->dev
,
496 &p
->state
.vs
.PUSH_CONSTANT_BUFFER
,
497 &p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
502 if (emit_3dstate_vs
) {
503 const int num_samplers
= ilo
->sampler
[PIPE_SHADER_VERTEX
].count
;
505 gen6_emit_3DSTATE_VS(p
->dev
, ilo
->vs
, num_samplers
, p
->cp
);
508 if (emit_3dstate_constant_vs
&& p
->dev
->gen
== ILO_GEN(6))
509 gen6_wa_pipe_control_vs_const_flush(p
);
513 gen6_pipeline_gs(struct ilo_3d_pipeline
*p
,
514 const struct ilo_context
*ilo
,
515 struct gen6_pipeline_session
*session
)
517 /* 3DSTATE_CONSTANT_GS */
518 if (session
->pcb_state_gs_changed
)
519 gen6_emit_3DSTATE_CONSTANT_GS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
522 if (DIRTY(GS
) || DIRTY(VS
) ||
523 session
->prim_changed
|| session
->kernel_bo_changed
) {
524 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
526 gen6_emit_3DSTATE_GS(p
->dev
, ilo
->gs
, ilo
->vs
, verts_per_prim
, p
->cp
);
531 gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline
*p
,
532 const struct ilo_context
*ilo
,
533 struct gen6_pipeline_session
*session
)
535 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
536 const struct pipe_stream_output_info
*so_info
=
537 (ilo
->gs
) ? ilo_shader_get_kernel_so_info(ilo
->gs
) :
538 (ilo
->vs
) ? ilo_shader_get_kernel_so_info(ilo
->vs
) : NULL
;
539 unsigned max_svbi
= 0xffffffff;
542 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
543 const int output_buffer
= so_info
->output
[i
].output_buffer
;
544 const struct pipe_stream_output_target
*so
=
545 ilo
->so
.states
[output_buffer
];
546 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
547 const int elem_size
= so_info
->output
[i
].num_components
* 4;
555 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
557 count
= buf_size
/ struct_size
;
558 if (buf_size
% struct_size
>= elem_size
)
561 if (count
< max_svbi
)
565 if (p
->state
.so_max_vertices
!= max_svbi
) {
566 p
->state
.so_max_vertices
= max_svbi
;
575 gen6_pipeline_gs_svbi(struct ilo_3d_pipeline
*p
,
576 const struct ilo_context
*ilo
,
577 struct gen6_pipeline_session
*session
)
579 const bool emit
= gen6_pipeline_update_max_svbi(p
, ilo
, session
);
581 /* 3DSTATE_GS_SVB_INDEX */
583 if (p
->dev
->gen
== ILO_GEN(6))
584 gen6_wa_pipe_control_post_sync(p
, false);
586 gen6_emit_3DSTATE_GS_SVB_INDEX(p
->dev
,
587 0, p
->state
.so_num_vertices
, p
->state
.so_max_vertices
,
590 if (session
->hw_ctx_changed
) {
594 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
596 * "If a buffer is not enabled then the SVBI must be set to 0x0
597 * in order to not cause overflow in that SVBI."
599 * "If a buffer is not enabled then the MaxSVBI must be set to
600 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
602 for (i
= 1; i
< 4; i
++) {
603 gen6_emit_3DSTATE_GS_SVB_INDEX(p
->dev
,
604 i
, 0, 0xffffffff, false, p
->cp
);
611 gen6_pipeline_clip(struct ilo_3d_pipeline
*p
,
612 const struct ilo_context
*ilo
,
613 struct gen6_pipeline_session
*session
)
616 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(VIEWPORT
) || DIRTY(FB
)) {
617 bool enable_guardband
= true;
621 * We do not do 2D clipping yet. Guard band test should only be enabled
622 * when the viewport is larger than the framebuffer.
624 for (i
= 0; i
< ilo
->viewport
.count
; i
++) {
625 const struct ilo_viewport_cso
*vp
= &ilo
->viewport
.cso
[i
];
627 if (vp
->min_x
> 0.0f
|| vp
->max_x
< ilo
->fb
.state
.width
||
628 vp
->min_y
> 0.0f
|| vp
->max_y
< ilo
->fb
.state
.height
) {
629 enable_guardband
= false;
634 gen6_emit_3DSTATE_CLIP(p
->dev
, ilo
->rasterizer
,
635 ilo
->fs
, enable_guardband
, 1, p
->cp
);
640 gen6_pipeline_sf(struct ilo_3d_pipeline
*p
,
641 const struct ilo_context
*ilo
,
642 struct gen6_pipeline_session
*session
)
645 if (DIRTY(RASTERIZER
) || DIRTY(FS
))
646 gen6_emit_3DSTATE_SF(p
->dev
, ilo
->rasterizer
, ilo
->fs
, p
->cp
);
650 gen6_pipeline_sf_rect(struct ilo_3d_pipeline
*p
,
651 const struct ilo_context
*ilo
,
652 struct gen6_pipeline_session
*session
)
654 /* 3DSTATE_DRAWING_RECTANGLE */
656 if (p
->dev
->gen
== ILO_GEN(6))
657 gen6_wa_pipe_control_post_sync(p
, false);
659 gen6_emit_3DSTATE_DRAWING_RECTANGLE(p
->dev
, 0, 0,
660 ilo
->fb
.state
.width
, ilo
->fb
.state
.height
, p
->cp
);
665 gen6_pipeline_wm(struct ilo_3d_pipeline
*p
,
666 const struct ilo_context
*ilo
,
667 struct gen6_pipeline_session
*session
)
669 /* 3DSTATE_CONSTANT_PS */
670 if (session
->pcb_state_fs_changed
) {
671 gen6_emit_3DSTATE_CONSTANT_PS(p
->dev
,
672 &p
->state
.wm
.PUSH_CONSTANT_BUFFER
,
673 &p
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
678 if (DIRTY(FS
) || DIRTY(SAMPLER_FS
) || DIRTY(BLEND
) || DIRTY(DSA
) ||
679 DIRTY(RASTERIZER
) || session
->kernel_bo_changed
) {
680 const int num_samplers
= ilo
->sampler
[PIPE_SHADER_FRAGMENT
].count
;
681 const bool dual_blend
= ilo
->blend
->dual_blend
;
682 const bool cc_may_kill
= (ilo
->dsa
->dw_alpha
||
683 ilo
->blend
->alpha_to_coverage
);
685 if (p
->dev
->gen
== ILO_GEN(6) && session
->hw_ctx_changed
)
686 gen6_wa_pipe_control_wm_max_threads_stall(p
);
688 gen6_emit_3DSTATE_WM(p
->dev
, ilo
->fs
, num_samplers
,
689 ilo
->rasterizer
, dual_blend
, cc_may_kill
, 0, p
->cp
);
694 gen6_pipeline_wm_multisample(struct ilo_3d_pipeline
*p
,
695 const struct ilo_context
*ilo
,
696 struct gen6_pipeline_session
*session
)
698 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
699 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
700 const uint32_t *packed_sample_pos
;
702 packed_sample_pos
= (ilo
->fb
.num_samples
> 1) ?
703 &p
->packed_sample_position_4x
: &p
->packed_sample_position_1x
;
705 if (p
->dev
->gen
== ILO_GEN(6)) {
706 gen6_wa_pipe_control_post_sync(p
, false);
707 gen6_wa_pipe_control_wm_multisample_flush(p
);
710 gen6_emit_3DSTATE_MULTISAMPLE(p
->dev
,
711 ilo
->fb
.num_samples
, packed_sample_pos
,
712 ilo
->rasterizer
->state
.half_pixel_center
, p
->cp
);
714 gen6_emit_3DSTATE_SAMPLE_MASK(p
->dev
,
715 (ilo
->fb
.num_samples
> 1) ? ilo
->sample_mask
: 0x1, p
->cp
);
720 gen6_pipeline_wm_depth(struct ilo_3d_pipeline
*p
,
721 const struct ilo_context
*ilo
,
722 struct gen6_pipeline_session
*session
)
724 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
725 if (DIRTY(FB
) || session
->batch_bo_changed
) {
726 const struct ilo_zs_surface
*zs
;
727 uint32_t clear_params
;
729 if (ilo
->fb
.state
.zsbuf
) {
730 const struct ilo_surface_cso
*surface
=
731 (const struct ilo_surface_cso
*) ilo
->fb
.state
.zsbuf
;
732 const struct ilo_texture_slice
*slice
=
733 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
734 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
736 assert(!surface
->is_rt
);
739 clear_params
= slice
->clear_value
;
742 zs
= &ilo
->fb
.null_zs
;
746 if (p
->dev
->gen
== ILO_GEN(6)) {
747 gen6_wa_pipe_control_post_sync(p
, false);
748 gen6_wa_pipe_control_wm_depth_flush(p
);
751 gen6_emit_3DSTATE_DEPTH_BUFFER(p
->dev
, zs
, p
->cp
);
752 gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p
->dev
, zs
, p
->cp
);
753 gen6_emit_3DSTATE_STENCIL_BUFFER(p
->dev
, zs
, p
->cp
);
754 gen6_emit_3DSTATE_CLEAR_PARAMS(p
->dev
, clear_params
, p
->cp
);
759 gen6_pipeline_wm_raster(struct ilo_3d_pipeline
*p
,
760 const struct ilo_context
*ilo
,
761 struct gen6_pipeline_session
*session
)
763 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
764 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
765 ilo
->rasterizer
->state
.poly_stipple_enable
) {
766 if (p
->dev
->gen
== ILO_GEN(6))
767 gen6_wa_pipe_control_post_sync(p
, false);
769 gen6_emit_3DSTATE_POLY_STIPPLE_PATTERN(p
->dev
,
770 &ilo
->poly_stipple
, p
->cp
);
772 gen6_emit_3DSTATE_POLY_STIPPLE_OFFSET(p
->dev
, 0, 0, p
->cp
);
775 /* 3DSTATE_LINE_STIPPLE */
776 if (DIRTY(RASTERIZER
) && ilo
->rasterizer
->state
.line_stipple_enable
) {
777 if (p
->dev
->gen
== ILO_GEN(6))
778 gen6_wa_pipe_control_post_sync(p
, false);
780 gen6_emit_3DSTATE_LINE_STIPPLE(p
->dev
,
781 ilo
->rasterizer
->state
.line_stipple_pattern
,
782 ilo
->rasterizer
->state
.line_stipple_factor
+ 1, p
->cp
);
785 /* 3DSTATE_AA_LINE_PARAMETERS */
786 if (DIRTY(RASTERIZER
) && ilo
->rasterizer
->state
.line_smooth
) {
787 if (p
->dev
->gen
== ILO_GEN(6))
788 gen6_wa_pipe_control_post_sync(p
, false);
790 gen6_emit_3DSTATE_AA_LINE_PARAMETERS(p
->dev
, p
->cp
);
795 gen6_pipeline_state_viewports(struct ilo_3d_pipeline
*p
,
796 const struct ilo_context
*ilo
,
797 struct gen6_pipeline_session
*session
)
799 /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
800 if (p
->dev
->gen
>= ILO_GEN(7) && DIRTY(VIEWPORT
)) {
801 p
->state
.SF_CLIP_VIEWPORT
= gen7_emit_SF_CLIP_VIEWPORT(p
->dev
,
802 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
804 p
->state
.CC_VIEWPORT
= gen6_emit_CC_VIEWPORT(p
->dev
,
805 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
807 session
->viewport_state_changed
= true;
809 /* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
810 else if (DIRTY(VIEWPORT
)) {
811 p
->state
.CLIP_VIEWPORT
= gen6_emit_CLIP_VIEWPORT(p
->dev
,
812 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
814 p
->state
.SF_VIEWPORT
= gen6_emit_SF_VIEWPORT(p
->dev
,
815 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
817 p
->state
.CC_VIEWPORT
= gen6_emit_CC_VIEWPORT(p
->dev
,
818 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
820 session
->viewport_state_changed
= true;
825 gen6_pipeline_state_cc(struct ilo_3d_pipeline
*p
,
826 const struct ilo_context
*ilo
,
827 struct gen6_pipeline_session
*session
)
830 if (DIRTY(BLEND
) || DIRTY(FB
) || DIRTY(DSA
)) {
831 p
->state
.BLEND_STATE
= gen6_emit_BLEND_STATE(p
->dev
,
832 ilo
->blend
, &ilo
->fb
, ilo
->dsa
, p
->cp
);
834 session
->cc_state_blend_changed
= true;
837 /* COLOR_CALC_STATE */
838 if (DIRTY(DSA
) || DIRTY(STENCIL_REF
) || DIRTY(BLEND_COLOR
)) {
839 p
->state
.COLOR_CALC_STATE
=
840 gen6_emit_COLOR_CALC_STATE(p
->dev
, &ilo
->stencil_ref
,
841 ilo
->dsa
->alpha_ref
, &ilo
->blend_color
, p
->cp
);
843 session
->cc_state_cc_changed
= true;
846 /* DEPTH_STENCIL_STATE */
848 p
->state
.DEPTH_STENCIL_STATE
=
849 gen6_emit_DEPTH_STENCIL_STATE(p
->dev
, ilo
->dsa
, p
->cp
);
851 session
->cc_state_dsa_changed
= true;
856 gen6_pipeline_state_scissors(struct ilo_3d_pipeline
*p
,
857 const struct ilo_context
*ilo
,
858 struct gen6_pipeline_session
*session
)
861 if (DIRTY(SCISSOR
) || DIRTY(VIEWPORT
)) {
862 /* there should be as many scissors as there are viewports */
863 p
->state
.SCISSOR_RECT
= gen6_emit_SCISSOR_RECT(p
->dev
,
864 &ilo
->scissor
, ilo
->viewport
.count
, p
->cp
);
866 session
->scissor_state_changed
= true;
871 gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline
*p
,
872 const struct ilo_context
*ilo
,
873 struct gen6_pipeline_session
*session
)
875 /* SURFACE_STATEs for render targets */
877 const struct ilo_fb_state
*fb
= &ilo
->fb
;
878 const int offset
= ILO_WM_DRAW_SURFACE(0);
879 uint32_t *surface_state
= &p
->state
.wm
.SURFACE_STATE
[offset
];
882 for (i
= 0; i
< fb
->state
.nr_cbufs
; i
++) {
883 const struct ilo_surface_cso
*surface
=
884 (const struct ilo_surface_cso
*) fb
->state
.cbufs
[i
];
888 gen6_emit_SURFACE_STATE(p
->dev
, &fb
->null_rt
, true, p
->cp
);
891 assert(surface
&& surface
->is_rt
);
893 gen6_emit_SURFACE_STATE(p
->dev
, &surface
->u
.rt
, true, p
->cp
);
898 * Upload at least one render target, as
899 * brw_update_renderbuffer_surfaces() does. I don't know why.
903 gen6_emit_SURFACE_STATE(p
->dev
, &fb
->null_rt
, true, p
->cp
);
908 memset(&surface_state
[i
], 0, (ILO_MAX_DRAW_BUFFERS
- i
) * 4);
910 if (i
&& session
->num_surfaces
[PIPE_SHADER_FRAGMENT
] < offset
+ i
)
911 session
->num_surfaces
[PIPE_SHADER_FRAGMENT
] = offset
+ i
;
913 session
->binding_table_fs_changed
= true;
918 gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline
*p
,
919 const struct ilo_context
*ilo
,
920 struct gen6_pipeline_session
*session
)
922 const struct ilo_so_state
*so
= &ilo
->so
;
924 if (p
->dev
->gen
!= ILO_GEN(6))
927 /* SURFACE_STATEs for stream output targets */
928 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
929 const struct pipe_stream_output_info
*so_info
=
930 (ilo
->gs
) ? ilo_shader_get_kernel_so_info(ilo
->gs
) :
931 (ilo
->vs
) ? ilo_shader_get_kernel_so_info(ilo
->vs
) : NULL
;
932 const int offset
= ILO_GS_SO_SURFACE(0);
933 uint32_t *surface_state
= &p
->state
.gs
.SURFACE_STATE
[offset
];
936 for (i
= 0; so_info
&& i
< so_info
->num_outputs
; i
++) {
937 const int target
= so_info
->output
[i
].output_buffer
;
938 const struct pipe_stream_output_target
*so_target
=
939 (target
< so
->count
) ? so
->states
[target
] : NULL
;
942 surface_state
[i
] = gen6_emit_so_SURFACE_STATE(p
->dev
,
943 so_target
, so_info
, i
, p
->cp
);
946 surface_state
[i
] = 0;
950 memset(&surface_state
[i
], 0, (ILO_MAX_SO_BINDINGS
- i
) * 4);
952 if (i
&& session
->num_surfaces
[PIPE_SHADER_GEOMETRY
] < offset
+ i
)
953 session
->num_surfaces
[PIPE_SHADER_GEOMETRY
] = offset
+ i
;
955 session
->binding_table_gs_changed
= true;
960 gen6_pipeline_state_surfaces_view(struct ilo_3d_pipeline
*p
,
961 const struct ilo_context
*ilo
,
963 struct gen6_pipeline_session
*session
)
965 const struct ilo_view_state
*view
= &ilo
->view
[shader_type
];
966 uint32_t *surface_state
;
970 /* SURFACE_STATEs for sampler views */
971 switch (shader_type
) {
972 case PIPE_SHADER_VERTEX
:
973 if (DIRTY(VIEW_VS
)) {
974 offset
= ILO_VS_TEXTURE_SURFACE(0);
975 surface_state
= &p
->state
.vs
.SURFACE_STATE
[offset
];
977 session
->binding_table_vs_changed
= true;
983 case PIPE_SHADER_FRAGMENT
:
984 if (DIRTY(VIEW_FS
)) {
985 offset
= ILO_WM_TEXTURE_SURFACE(0);
986 surface_state
= &p
->state
.wm
.SURFACE_STATE
[offset
];
988 session
->binding_table_fs_changed
= true;
1002 for (i
= 0; i
< view
->count
; i
++) {
1003 if (view
->states
[i
]) {
1004 const struct ilo_view_cso
*cso
=
1005 (const struct ilo_view_cso
*) view
->states
[i
];
1008 gen6_emit_SURFACE_STATE(p
->dev
, &cso
->surface
, false, p
->cp
);
1011 surface_state
[i
] = 0;
1015 memset(&surface_state
[i
], 0, (ILO_MAX_SAMPLER_VIEWS
- i
) * 4);
1017 if (i
&& session
->num_surfaces
[shader_type
] < offset
+ i
)
1018 session
->num_surfaces
[shader_type
] = offset
+ i
;
1022 gen6_pipeline_state_surfaces_const(struct ilo_3d_pipeline
*p
,
1023 const struct ilo_context
*ilo
,
1025 struct gen6_pipeline_session
*session
)
1027 const struct ilo_cbuf_state
*cbuf
= &ilo
->cbuf
[shader_type
];
1028 uint32_t *surface_state
;
1029 bool *binding_table_changed
;
1030 int offset
, count
, i
;
1035 /* SURFACE_STATEs for constant buffers */
1036 switch (shader_type
) {
1037 case PIPE_SHADER_VERTEX
:
1038 offset
= ILO_VS_CONST_SURFACE(0);
1039 surface_state
= &p
->state
.vs
.SURFACE_STATE
[offset
];
1040 binding_table_changed
= &session
->binding_table_vs_changed
;
1042 case PIPE_SHADER_FRAGMENT
:
1043 offset
= ILO_WM_CONST_SURFACE(0);
1044 surface_state
= &p
->state
.wm
.SURFACE_STATE
[offset
];
1045 binding_table_changed
= &session
->binding_table_fs_changed
;
1052 /* constants are pushed via PCB */
1053 if (cbuf
->enabled_mask
== 0x1 && !cbuf
->cso
[0].resource
) {
1054 memset(surface_state
, 0, ILO_MAX_CONST_BUFFERS
* 4);
1058 count
= util_last_bit(cbuf
->enabled_mask
);
1059 for (i
= 0; i
< count
; i
++) {
1060 if (cbuf
->cso
[i
].resource
) {
1061 surface_state
[i
] = gen6_emit_SURFACE_STATE(p
->dev
,
1062 &cbuf
->cso
[i
].surface
, false, p
->cp
);
1065 surface_state
[i
] = 0;
1069 memset(&surface_state
[count
], 0, (ILO_MAX_CONST_BUFFERS
- count
) * 4);
1071 if (count
&& session
->num_surfaces
[shader_type
] < offset
+ count
)
1072 session
->num_surfaces
[shader_type
] = offset
+ count
;
1074 *binding_table_changed
= true;
1078 gen6_pipeline_state_binding_tables(struct ilo_3d_pipeline
*p
,
1079 const struct ilo_context
*ilo
,
1081 struct gen6_pipeline_session
*session
)
1083 uint32_t *binding_table_state
, *surface_state
;
1084 int *binding_table_state_size
, size
;
1087 /* BINDING_TABLE_STATE */
1088 switch (shader_type
) {
1089 case PIPE_SHADER_VERTEX
:
1090 surface_state
= p
->state
.vs
.SURFACE_STATE
;
1091 binding_table_state
= &p
->state
.vs
.BINDING_TABLE_STATE
;
1092 binding_table_state_size
= &p
->state
.vs
.BINDING_TABLE_STATE_size
;
1094 skip
= !session
->binding_table_vs_changed
;
1096 case PIPE_SHADER_GEOMETRY
:
1097 surface_state
= p
->state
.gs
.SURFACE_STATE
;
1098 binding_table_state
= &p
->state
.gs
.BINDING_TABLE_STATE
;
1099 binding_table_state_size
= &p
->state
.gs
.BINDING_TABLE_STATE_size
;
1101 skip
= !session
->binding_table_gs_changed
;
1103 case PIPE_SHADER_FRAGMENT
:
1104 surface_state
= p
->state
.wm
.SURFACE_STATE
;
1105 binding_table_state
= &p
->state
.wm
.BINDING_TABLE_STATE
;
1106 binding_table_state_size
= &p
->state
.wm
.BINDING_TABLE_STATE_size
;
1108 skip
= !session
->binding_table_fs_changed
;
1119 * If we have seemingly less SURFACE_STATEs than before, it could be that
1120 * we did not touch those reside at the tail in this upload. Loop over
1121 * them to figure out the real number of SURFACE_STATEs.
1123 for (size
= *binding_table_state_size
;
1124 size
> session
->num_surfaces
[shader_type
]; size
--) {
1125 if (surface_state
[size
- 1])
1128 if (size
< session
->num_surfaces
[shader_type
])
1129 size
= session
->num_surfaces
[shader_type
];
1131 *binding_table_state
= gen6_emit_BINDING_TABLE_STATE(p
->dev
,
1132 surface_state
, size
, p
->cp
);
1133 *binding_table_state_size
= size
;
1137 gen6_pipeline_state_samplers(struct ilo_3d_pipeline
*p
,
1138 const struct ilo_context
*ilo
,
1140 struct gen6_pipeline_session
*session
)
1142 const struct ilo_sampler_cso
* const *samplers
=
1143 ilo
->sampler
[shader_type
].cso
;
1144 const struct pipe_sampler_view
* const *views
=
1145 (const struct pipe_sampler_view
**) ilo
->view
[shader_type
].states
;
1146 const int num_samplers
= ilo
->sampler
[shader_type
].count
;
1147 const int num_views
= ilo
->view
[shader_type
].count
;
1148 uint32_t *sampler_state
, *border_color_state
;
1149 bool emit_border_color
= false;
1152 /* SAMPLER_BORDER_COLOR_STATE and SAMPLER_STATE */
1153 switch (shader_type
) {
1154 case PIPE_SHADER_VERTEX
:
1155 if (DIRTY(SAMPLER_VS
) || DIRTY(VIEW_VS
)) {
1156 sampler_state
= &p
->state
.vs
.SAMPLER_STATE
;
1157 border_color_state
= p
->state
.vs
.SAMPLER_BORDER_COLOR_STATE
;
1159 if (DIRTY(SAMPLER_VS
))
1160 emit_border_color
= true;
1162 session
->sampler_state_vs_changed
= true;
1168 case PIPE_SHADER_FRAGMENT
:
1169 if (DIRTY(SAMPLER_FS
) || DIRTY(VIEW_FS
)) {
1170 sampler_state
= &p
->state
.wm
.SAMPLER_STATE
;
1171 border_color_state
= p
->state
.wm
.SAMPLER_BORDER_COLOR_STATE
;
1173 if (DIRTY(SAMPLER_FS
))
1174 emit_border_color
= true;
1176 session
->sampler_state_fs_changed
= true;
1190 if (emit_border_color
) {
1193 for (i
= 0; i
< num_samplers
; i
++) {
1194 border_color_state
[i
] = (samplers
[i
]) ?
1195 gen6_emit_SAMPLER_BORDER_COLOR_STATE(p
->dev
,
1196 samplers
[i
], p
->cp
) : 0;
1200 /* should we take the minimum of num_samplers and num_views? */
1201 *sampler_state
= gen6_emit_SAMPLER_STATE(p
->dev
,
1204 MIN2(num_samplers
, num_views
), p
->cp
);
1208 gen6_pipeline_state_pcb(struct ilo_3d_pipeline
*p
,
1209 const struct ilo_context
*ilo
,
1210 struct gen6_pipeline_session
*session
)
1212 /* push constant buffer for VS */
1213 if (DIRTY(VS
) || DIRTY(CBUF
) || DIRTY(CLIP
)) {
1214 const int cbuf0_size
= (ilo
->vs
) ?
1215 ilo_shader_get_kernel_param(ilo
->vs
,
1216 ILO_KERNEL_PCB_CBUF0_SIZE
) : 0;
1217 const int clip_state_size
= (ilo
->vs
) ?
1218 ilo_shader_get_kernel_param(ilo
->vs
,
1219 ILO_KERNEL_VS_PCB_UCP_SIZE
) : 0;
1220 const int total_size
= cbuf0_size
+ clip_state_size
;
1225 p
->state
.vs
.PUSH_CONSTANT_BUFFER
=
1226 gen6_emit_push_constant_buffer(p
->dev
, total_size
, &pcb
, p
->cp
);
1227 p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
= total_size
;
1230 const struct ilo_cbuf_state
*cbuf
=
1231 &ilo
->cbuf
[PIPE_SHADER_VERTEX
];
1233 if (cbuf0_size
<= cbuf
->cso
[0].user_buffer_size
) {
1234 memcpy(pcb
, cbuf
->cso
[0].user_buffer
, cbuf0_size
);
1237 memcpy(pcb
, cbuf
->cso
[0].user_buffer
,
1238 cbuf
->cso
[0].user_buffer_size
);
1239 memset(pcb
+ cbuf
->cso
[0].user_buffer_size
, 0,
1240 cbuf0_size
- cbuf
->cso
[0].user_buffer_size
);
1246 if (clip_state_size
)
1247 memcpy(pcb
, &ilo
->clip
, clip_state_size
);
1249 session
->pcb_state_vs_changed
= true;
1251 else if (p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
) {
1252 p
->state
.vs
.PUSH_CONSTANT_BUFFER
= 0;
1253 p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
= 0;
1255 session
->pcb_state_vs_changed
= true;
1259 /* push constant buffer for FS */
1260 if (DIRTY(FS
) || DIRTY(CBUF
)) {
1261 const int cbuf0_size
= (ilo
->fs
) ?
1262 ilo_shader_get_kernel_param(ilo
->fs
, ILO_KERNEL_PCB_CBUF0_SIZE
) : 0;
1265 const struct ilo_cbuf_state
*cbuf
= &ilo
->cbuf
[PIPE_SHADER_FRAGMENT
];
1268 p
->state
.wm
.PUSH_CONSTANT_BUFFER
=
1269 gen6_emit_push_constant_buffer(p
->dev
, cbuf0_size
, &pcb
, p
->cp
);
1270 p
->state
.wm
.PUSH_CONSTANT_BUFFER_size
= cbuf0_size
;
1272 if (cbuf0_size
<= cbuf
->cso
[0].user_buffer_size
) {
1273 memcpy(pcb
, cbuf
->cso
[0].user_buffer
, cbuf0_size
);
1276 memcpy(pcb
, cbuf
->cso
[0].user_buffer
,
1277 cbuf
->cso
[0].user_buffer_size
);
1278 memset(pcb
+ cbuf
->cso
[0].user_buffer_size
, 0,
1279 cbuf0_size
- cbuf
->cso
[0].user_buffer_size
);
1282 session
->pcb_state_fs_changed
= true;
1284 else if (p
->state
.wm
.PUSH_CONSTANT_BUFFER_size
) {
1285 p
->state
.wm
.PUSH_CONSTANT_BUFFER
= 0;
1286 p
->state
.wm
.PUSH_CONSTANT_BUFFER_size
= 0;
1288 session
->pcb_state_fs_changed
= true;
1296 gen6_pipeline_commands(struct ilo_3d_pipeline
*p
,
1297 const struct ilo_context
*ilo
,
1298 struct gen6_pipeline_session
*session
)
1301 * We try to keep the order of the commands match, as closely as possible,
1302 * that of the classic i965 driver. It allows us to compare the command
1305 gen6_pipeline_common_select(p
, ilo
, session
);
1306 gen6_pipeline_gs_svbi(p
, ilo
, session
);
1307 gen6_pipeline_common_sip(p
, ilo
, session
);
1308 gen6_pipeline_vf_statistics(p
, ilo
, session
);
1309 gen6_pipeline_common_base_address(p
, ilo
, session
);
1310 gen6_pipeline_common_pointers_1(p
, ilo
, session
);
1311 gen6_pipeline_common_urb(p
, ilo
, session
);
1312 gen6_pipeline_common_pointers_2(p
, ilo
, session
);
1313 gen6_pipeline_wm_multisample(p
, ilo
, session
);
1314 gen6_pipeline_vs(p
, ilo
, session
);
1315 gen6_pipeline_gs(p
, ilo
, session
);
1316 gen6_pipeline_clip(p
, ilo
, session
);
1317 gen6_pipeline_sf(p
, ilo
, session
);
1318 gen6_pipeline_wm(p
, ilo
, session
);
1319 gen6_pipeline_common_pointers_3(p
, ilo
, session
);
1320 gen6_pipeline_wm_depth(p
, ilo
, session
);
1321 gen6_pipeline_wm_raster(p
, ilo
, session
);
1322 gen6_pipeline_sf_rect(p
, ilo
, session
);
1323 gen6_pipeline_vf(p
, ilo
, session
);
1324 gen6_pipeline_vf_draw(p
, ilo
, session
);
1328 gen6_pipeline_states(struct ilo_3d_pipeline
*p
,
1329 const struct ilo_context
*ilo
,
1330 struct gen6_pipeline_session
*session
)
1334 gen6_pipeline_state_viewports(p
, ilo
, session
);
1335 gen6_pipeline_state_cc(p
, ilo
, session
);
1336 gen6_pipeline_state_scissors(p
, ilo
, session
);
1337 gen6_pipeline_state_pcb(p
, ilo
, session
);
1340 * upload all SURAFCE_STATEs together so that we know there are minimal
1343 gen6_pipeline_state_surfaces_rt(p
, ilo
, session
);
1344 gen6_pipeline_state_surfaces_so(p
, ilo
, session
);
1345 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
1346 gen6_pipeline_state_surfaces_view(p
, ilo
, shader_type
, session
);
1347 gen6_pipeline_state_surfaces_const(p
, ilo
, shader_type
, session
);
1350 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
1351 gen6_pipeline_state_samplers(p
, ilo
, shader_type
, session
);
1352 /* this must be called after all SURFACE_STATEs are uploaded */
1353 gen6_pipeline_state_binding_tables(p
, ilo
, shader_type
, session
);
1358 gen6_pipeline_prepare(const struct ilo_3d_pipeline
*p
,
1359 const struct ilo_context
*ilo
,
1360 struct gen6_pipeline_session
*session
)
1362 memset(session
, 0, sizeof(*session
));
1363 session
->pipe_dirty
= ilo
->dirty
;
1364 session
->reduced_prim
= u_reduced_prim(ilo
->draw
->mode
);
1366 /* available space before the session */
1367 session
->init_cp_space
= ilo_cp_space(p
->cp
);
1369 session
->hw_ctx_changed
=
1370 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_HW
);
1372 if (session
->hw_ctx_changed
) {
1373 /* these should be enough to make everything uploaded */
1374 session
->batch_bo_changed
= true;
1375 session
->state_bo_changed
= true;
1376 session
->kernel_bo_changed
= true;
1377 session
->prim_changed
= true;
1378 session
->primitive_restart_changed
= true;
1382 * Any state that involves resources needs to be re-emitted when the
1383 * batch bo changed. This is because we do not pin the resources and
1384 * their offsets (or existence) may change between batch buffers.
1386 * Since we messed around with ILO_3D_PIPELINE_INVALIDATE_BATCH_BO in
1387 * handle_invalid_batch_bo(), use ILO_3D_PIPELINE_INVALIDATE_STATE_BO as
1388 * a temporary workaround.
1390 session
->batch_bo_changed
=
1391 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_STATE_BO
);
1393 session
->state_bo_changed
=
1394 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_STATE_BO
);
1395 session
->kernel_bo_changed
=
1396 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO
);
1397 session
->prim_changed
= (p
->state
.reduced_prim
!= session
->reduced_prim
);
1398 session
->primitive_restart_changed
=
1399 (p
->state
.primitive_restart
!= ilo
->draw
->primitive_restart
);
1404 gen6_pipeline_draw(struct ilo_3d_pipeline
*p
,
1405 const struct ilo_context
*ilo
,
1406 struct gen6_pipeline_session
*session
)
1408 /* force all states to be uploaded if the state bo changed */
1409 if (session
->state_bo_changed
)
1410 session
->pipe_dirty
= ILO_DIRTY_ALL
;
1412 session
->pipe_dirty
= ilo
->dirty
;
1414 session
->emit_draw_states(p
, ilo
, session
);
1416 /* force all commands to be uploaded if the HW context changed */
1417 if (session
->hw_ctx_changed
)
1418 session
->pipe_dirty
= ILO_DIRTY_ALL
;
1420 session
->pipe_dirty
= ilo
->dirty
;
1422 session
->emit_draw_commands(p
, ilo
, session
);
1426 gen6_pipeline_end(struct ilo_3d_pipeline
*p
,
1427 const struct ilo_context
*ilo
,
1428 struct gen6_pipeline_session
*session
)
1430 /* sanity check size estimation */
1431 assert(session
->init_cp_space
- ilo_cp_space(p
->cp
) <=
1432 ilo_3d_pipeline_estimate_size(p
, ILO_3D_PIPELINE_DRAW
, ilo
));
1434 p
->state
.reduced_prim
= session
->reduced_prim
;
1435 p
->state
.primitive_restart
= ilo
->draw
->primitive_restart
;
1439 ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline
*p
,
1440 const struct ilo_context
*ilo
)
1442 struct gen6_pipeline_session session
;
1444 gen6_pipeline_prepare(p
, ilo
, &session
);
1446 session
.emit_draw_states
= gen6_pipeline_states
;
1447 session
.emit_draw_commands
= gen6_pipeline_commands
;
1449 gen6_pipeline_draw(p
, ilo
, &session
);
1450 gen6_pipeline_end(p
, ilo
, &session
);
1454 ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline
*p
)
1456 if (p
->dev
->gen
== ILO_GEN(6))
1457 gen6_wa_pipe_control_post_sync(p
, false);
1459 gen6_emit_PIPE_CONTROL(p
->dev
,
1460 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
1461 GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
|
1462 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1463 GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE
|
1464 GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1465 GEN6_PIPE_CONTROL_WRITE_NONE
|
1466 GEN6_PIPE_CONTROL_CS_STALL
,
1467 0, 0, false, p
->cp
);
1471 ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline
*p
,
1472 struct intel_bo
*bo
, int index
)
1474 if (p
->dev
->gen
== ILO_GEN(6))
1475 gen6_wa_pipe_control_post_sync(p
, true);
1477 gen6_emit_PIPE_CONTROL(p
->dev
,
1478 GEN6_PIPE_CONTROL_WRITE_TIMESTAMP
,
1479 bo
, index
* sizeof(uint64_t),
1484 ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline
*p
,
1485 struct intel_bo
*bo
, int index
)
1487 if (p
->dev
->gen
== ILO_GEN(6))
1488 gen6_wa_pipe_control_post_sync(p
, false);
1490 gen6_emit_PIPE_CONTROL(p
->dev
,
1491 GEN6_PIPE_CONTROL_DEPTH_STALL
|
1492 GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT
,
1493 bo
, index
* sizeof(uint64_t),
1498 ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline
*p
,
1499 struct intel_bo
*bo
, int index
)
1502 GEN6_REG_IA_VERTICES_COUNT
,
1503 GEN6_REG_IA_PRIMITIVES_COUNT
,
1504 GEN6_REG_VS_INVOCATION_COUNT
,
1505 GEN6_REG_GS_INVOCATION_COUNT
,
1506 GEN6_REG_GS_PRIMITIVES_COUNT
,
1507 GEN6_REG_CL_INVOCATION_COUNT
,
1508 GEN6_REG_CL_PRIMITIVES_COUNT
,
1509 GEN6_REG_PS_INVOCATION_COUNT
,
1510 p
->dev
->gen
>= ILO_GEN(7) ? GEN6_REG_HS_INVOCATION_COUNT
: 0,
1511 p
->dev
->gen
>= ILO_GEN(7) ? GEN6_REG_DS_INVOCATION_COUNT
: 0,
1518 for (i
= 0; i
< Elements(regs
); i
++) {
1519 const uint32_t bo_offset
= (index
+ i
) * sizeof(uint64_t);
1522 /* store lower 32 bits */
1523 gen6_emit_MI_STORE_REGISTER_MEM(p
->dev
,
1524 bo
, bo_offset
, regs
[i
], p
->cp
);
1525 /* store higher 32 bits */
1526 gen6_emit_MI_STORE_REGISTER_MEM(p
->dev
,
1527 bo
, bo_offset
+ 4, regs
[i
] + 4, p
->cp
);
1530 gen6_emit_MI_STORE_DATA_IMM(p
->dev
,
1531 bo
, bo_offset
, 0, true, p
->cp
);
1537 gen6_rectlist_vs_to_sf(struct ilo_3d_pipeline
*p
,
1538 const struct ilo_blitter
*blitter
,
1539 struct gen6_rectlist_session
*session
)
1541 gen6_emit_3DSTATE_CONSTANT_VS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
1542 gen6_emit_3DSTATE_VS(p
->dev
, NULL
, 0, p
->cp
);
1544 gen6_wa_pipe_control_vs_const_flush(p
);
1546 gen6_emit_3DSTATE_CONSTANT_GS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
1547 gen6_emit_3DSTATE_GS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
1549 gen6_emit_3DSTATE_CLIP(p
->dev
, NULL
, NULL
, false, 0, p
->cp
);
1550 gen6_emit_3DSTATE_SF(p
->dev
, NULL
, NULL
, p
->cp
);
1554 gen6_rectlist_wm(struct ilo_3d_pipeline
*p
,
1555 const struct ilo_blitter
*blitter
,
1556 struct gen6_rectlist_session
*session
)
1560 switch (blitter
->op
) {
1561 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
1562 hiz_op
= GEN6_WM_DW4_DEPTH_CLEAR
;
1564 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
1565 hiz_op
= GEN6_WM_DW4_DEPTH_RESOLVE
;
1567 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
1568 hiz_op
= GEN6_WM_DW4_HIZ_RESOLVE
;
1575 gen6_emit_3DSTATE_CONSTANT_PS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
1577 gen6_wa_pipe_control_wm_max_threads_stall(p
);
1578 gen6_emit_3DSTATE_WM(p
->dev
, NULL
, 0, NULL
, false, false, hiz_op
, p
->cp
);
1582 gen6_rectlist_wm_depth(struct ilo_3d_pipeline
*p
,
1583 const struct ilo_blitter
*blitter
,
1584 struct gen6_rectlist_session
*session
)
1586 gen6_wa_pipe_control_wm_depth_flush(p
);
1588 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
1589 ILO_BLITTER_USE_FB_STENCIL
)) {
1590 gen6_emit_3DSTATE_DEPTH_BUFFER(p
->dev
,
1591 &blitter
->fb
.dst
.u
.zs
, p
->cp
);
1594 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
1595 gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p
->dev
,
1596 &blitter
->fb
.dst
.u
.zs
, p
->cp
);
1599 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
1600 gen6_emit_3DSTATE_STENCIL_BUFFER(p
->dev
,
1601 &blitter
->fb
.dst
.u
.zs
, p
->cp
);
1604 gen6_emit_3DSTATE_CLEAR_PARAMS(p
->dev
,
1605 blitter
->depth_clear_value
, p
->cp
);
1609 gen6_rectlist_wm_multisample(struct ilo_3d_pipeline
*p
,
1610 const struct ilo_blitter
*blitter
,
1611 struct gen6_rectlist_session
*session
)
1613 const uint32_t *packed_sample_pos
= (blitter
->fb
.num_samples
> 1) ?
1614 &p
->packed_sample_position_4x
: &p
->packed_sample_position_1x
;
1616 gen6_wa_pipe_control_wm_multisample_flush(p
);
1618 gen6_emit_3DSTATE_MULTISAMPLE(p
->dev
, blitter
->fb
.num_samples
,
1619 packed_sample_pos
, true, p
->cp
);
1621 gen6_emit_3DSTATE_SAMPLE_MASK(p
->dev
,
1622 (1 << blitter
->fb
.num_samples
) - 1, p
->cp
);
1626 gen6_rectlist_commands(struct ilo_3d_pipeline
*p
,
1627 const struct ilo_blitter
*blitter
,
1628 struct gen6_rectlist_session
*session
)
1630 gen6_wa_pipe_control_post_sync(p
, false);
1632 gen6_rectlist_wm_multisample(p
, blitter
, session
);
1634 gen6_emit_STATE_BASE_ADDRESS(p
->dev
,
1635 NULL
, /* General State Base */
1636 p
->cp
->bo
, /* Surface State Base */
1637 p
->cp
->bo
, /* Dynamic State Base */
1638 NULL
, /* Indirect Object Base */
1639 NULL
, /* Instruction Base */
1642 gen6_emit_3DSTATE_VERTEX_BUFFERS(p
->dev
,
1643 &blitter
->ve
, &blitter
->vb
, p
->cp
);
1645 gen6_emit_3DSTATE_VERTEX_ELEMENTS(p
->dev
,
1646 &blitter
->ve
, false, false, p
->cp
);
1648 gen6_emit_3DSTATE_URB(p
->dev
,
1649 p
->dev
->urb_size
, 0, blitter
->ve
.count
* 4 * sizeof(float), 0, p
->cp
);
1650 /* 3DSTATE_URB workaround */
1651 if (p
->state
.gs
.active
) {
1652 ilo_3d_pipeline_emit_flush_gen6(p
);
1653 p
->state
.gs
.active
= false;
1657 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
1658 gen6_emit_3DSTATE_CC_STATE_POINTERS(p
->dev
, 0,
1659 session
->DEPTH_STENCIL_STATE
, session
->COLOR_CALC_STATE
, p
->cp
);
1662 gen6_rectlist_vs_to_sf(p
, blitter
, session
);
1663 gen6_rectlist_wm(p
, blitter
, session
);
1665 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
1666 gen6_emit_3DSTATE_VIEWPORT_STATE_POINTERS(p
->dev
,
1667 0, 0, session
->CC_VIEWPORT
, p
->cp
);
1670 gen6_rectlist_wm_depth(p
, blitter
, session
);
1672 gen6_emit_3DSTATE_DRAWING_RECTANGLE(p
->dev
, 0, 0,
1673 blitter
->fb
.width
, blitter
->fb
.height
, p
->cp
);
1675 gen6_emit_3DPRIMITIVE(p
->dev
, &blitter
->draw
, NULL
, true, p
->cp
);
1679 gen6_rectlist_states(struct ilo_3d_pipeline
*p
,
1680 const struct ilo_blitter
*blitter
,
1681 struct gen6_rectlist_session
*session
)
1683 if (blitter
->uses
& ILO_BLITTER_USE_DSA
) {
1684 session
->DEPTH_STENCIL_STATE
=
1685 gen6_emit_DEPTH_STENCIL_STATE(p
->dev
, &blitter
->dsa
, p
->cp
);
1688 if (blitter
->uses
& ILO_BLITTER_USE_CC
) {
1689 session
->COLOR_CALC_STATE
=
1690 gen6_emit_COLOR_CALC_STATE(p
->dev
, &blitter
->cc
.stencil_ref
,
1691 blitter
->cc
.alpha_ref
, &blitter
->cc
.blend_color
, p
->cp
);
1694 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
1695 session
->CC_VIEWPORT
=
1696 gen6_emit_CC_VIEWPORT(p
->dev
, &blitter
->viewport
, 1, p
->cp
);
1701 ilo_3d_pipeline_emit_rectlist_gen6(struct ilo_3d_pipeline
*p
,
1702 const struct ilo_blitter
*blitter
)
1704 struct gen6_rectlist_session session
;
1706 memset(&session
, 0, sizeof(session
));
1707 gen6_rectlist_states(p
, blitter
, &session
);
1708 gen6_rectlist_commands(p
, blitter
, &session
);
1712 gen6_pipeline_max_command_size(const struct ilo_3d_pipeline
*p
)
1717 size
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
1718 size
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
1719 size
+= GEN6_PIPE_CONTROL__SIZE
* 5;
1722 GEN6_STATE_BASE_ADDRESS__SIZE
+
1723 GEN6_STATE_SIP__SIZE
+
1724 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
1725 GEN6_PIPELINE_SELECT__SIZE
+
1726 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
1727 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
1728 GEN6_3DSTATE_URB__SIZE
+
1729 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
1730 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
1731 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
1732 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
1733 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
1734 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
1735 GEN6_3DSTATE_VS__SIZE
+
1736 GEN6_3DSTATE_GS__SIZE
+
1737 GEN6_3DSTATE_CLIP__SIZE
+
1738 GEN6_3DSTATE_SF__SIZE
+
1739 GEN6_3DSTATE_WM__SIZE
+
1740 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
1741 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
1742 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
1743 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
1744 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
1745 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
1746 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
1747 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
1748 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
1749 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
1750 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
1751 GEN6_3DPRIMITIVE__SIZE
;
1758 gen6_pipeline_estimate_state_size(const struct ilo_3d_pipeline
*p
,
1759 const struct ilo_context
*ilo
)
1761 static int static_size
;
1765 /* 64 bytes, or 16 dwords */
1766 const int alignment
= 64 / 4;
1769 size
= alignment
- 1;
1772 size
+= align(GEN6_BLEND_STATE__SIZE
* ILO_MAX_DRAW_BUFFERS
, alignment
);
1773 size
+= align(GEN6_DEPTH_STENCIL_STATE__SIZE
, alignment
);
1774 size
+= align(GEN6_COLOR_CALC_STATE__SIZE
, alignment
);
1776 /* viewport arrays */
1777 if (p
->dev
->gen
>= ILO_GEN(7)) {
1779 align(GEN7_SF_CLIP_VIEWPORT__SIZE
* ILO_MAX_VIEWPORTS
, 16) +
1780 align(GEN6_CC_VIEWPORT__SIZE
* ILO_MAX_VIEWPORTS
, 8) +
1781 align(GEN6_SCISSOR_RECT__SIZE
* ILO_MAX_VIEWPORTS
, 8);
1785 align(GEN6_SF_VIEWPORT__SIZE
* ILO_MAX_VIEWPORTS
, 8) +
1786 align(GEN6_CLIP_VIEWPORT__SIZE
* ILO_MAX_VIEWPORTS
, 8) +
1787 align(GEN6_CC_VIEWPORT__SIZE
* ILO_MAX_VIEWPORTS
, 8) +
1788 align(GEN6_SCISSOR_RECT__SIZE
* ILO_MAX_VIEWPORTS
, 8);
1796 for (sh_type
= 0; sh_type
< PIPE_SHADER_TYPES
; sh_type
++) {
1797 const int alignment
= 32 / 4;
1798 int num_samplers
, num_surfaces
, pcb_size
;
1801 num_samplers
= ilo
->sampler
[sh_type
].count
;
1803 /* sampler views and constant buffers */
1804 num_surfaces
= ilo
->view
[sh_type
].count
+
1805 util_bitcount(ilo
->cbuf
[sh_type
].enabled_mask
);
1810 case PIPE_SHADER_VERTEX
:
1812 if (p
->dev
->gen
== ILO_GEN(6)) {
1813 const struct pipe_stream_output_info
*so_info
=
1814 ilo_shader_get_kernel_so_info(ilo
->vs
);
1816 /* stream outputs */
1817 num_surfaces
+= so_info
->num_outputs
;
1820 pcb_size
= ilo_shader_get_kernel_param(ilo
->vs
,
1821 ILO_KERNEL_PCB_CBUF0_SIZE
);
1822 pcb_size
+= ilo_shader_get_kernel_param(ilo
->vs
,
1823 ILO_KERNEL_VS_PCB_UCP_SIZE
);
1826 case PIPE_SHADER_GEOMETRY
:
1827 if (ilo
->gs
&& p
->dev
->gen
== ILO_GEN(6)) {
1828 const struct pipe_stream_output_info
*so_info
=
1829 ilo_shader_get_kernel_so_info(ilo
->gs
);
1831 /* stream outputs */
1832 num_surfaces
+= so_info
->num_outputs
;
1835 case PIPE_SHADER_FRAGMENT
:
1836 /* render targets */
1837 num_surfaces
+= ilo
->fb
.state
.nr_cbufs
;
1840 pcb_size
= ilo_shader_get_kernel_param(ilo
->fs
,
1841 ILO_KERNEL_PCB_CBUF0_SIZE
);
1848 /* SAMPLER_STATE array and SAMPLER_BORDER_COLORs */
1850 size
+= align(GEN6_SAMPLER_STATE__SIZE
* num_samplers
, alignment
) +
1851 align(GEN6_SAMPLER_BORDER_COLOR__SIZE
, alignment
) * num_samplers
;
1854 /* BINDING_TABLE_STATE and SURFACE_STATEs */
1856 size
+= align(num_surfaces
, alignment
) +
1857 align(GEN6_SURFACE_STATE__SIZE
, alignment
) * num_surfaces
;
1862 size
+= align(pcb_size
, alignment
);
1869 ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline
*p
,
1870 enum ilo_3d_pipeline_action action
,
1876 case ILO_3D_PIPELINE_DRAW
:
1878 const struct ilo_context
*ilo
= arg
;
1880 size
= gen6_pipeline_max_command_size(p
) +
1881 gen6_pipeline_estimate_state_size(p
, ilo
);
1884 case ILO_3D_PIPELINE_FLUSH
:
1885 size
= GEN6_PIPE_CONTROL__SIZE
* 3;
1887 case ILO_3D_PIPELINE_WRITE_TIMESTAMP
:
1888 size
= GEN6_PIPE_CONTROL__SIZE
* 2;
1890 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT
:
1891 size
= GEN6_PIPE_CONTROL__SIZE
* 3;
1893 case ILO_3D_PIPELINE_WRITE_STATISTICS
:
1895 const int num_regs
= 8;
1896 const int num_pads
= 3;
1898 size
= GEN6_PIPE_CONTROL__SIZE
;
1899 size
+= GEN6_MI_STORE_REGISTER_MEM__SIZE
* 2 * num_regs
;
1900 size
+= GEN6_MI_STORE_DATA_IMM__SIZE
* num_pads
;
1903 case ILO_3D_PIPELINE_RECTLIST
:
1904 size
= 64 + 256; /* states + commands */
1907 assert(!"unknown 3D pipeline action");
1916 ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline
*p
)
1918 p
->estimate_size
= ilo_3d_pipeline_estimate_size_gen6
;
1919 p
->emit_draw
= ilo_3d_pipeline_emit_draw_gen6
;
1920 p
->emit_flush
= ilo_3d_pipeline_emit_flush_gen6
;
1921 p
->emit_write_timestamp
= ilo_3d_pipeline_emit_write_timestamp_gen6
;
1922 p
->emit_write_depth_count
= ilo_3d_pipeline_emit_write_depth_count_gen6
;
1923 p
->emit_write_statistics
= ilo_3d_pipeline_emit_write_statistics_gen6
;
1924 p
->emit_rectlist
= ilo_3d_pipeline_emit_rectlist_gen6
;