2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "util/u_dual_blend.h"
29 #include "util/u_prim.h"
30 #include "intel_reg.h"
32 #include "ilo_context.h"
34 #include "ilo_gpe_gen6.h"
35 #include "ilo_shader.h"
36 #include "ilo_state.h"
37 #include "ilo_3d_pipeline.h"
38 #include "ilo_3d_pipeline_gen6.h"
41 * This should be called before any depth stall flush (including those
42 * produced by non-pipelined state commands) or cache flush on GEN6.
44 * \see intel_emit_post_sync_nonzero_flush()
47 gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline
*p
,
48 bool caller_post_sync
)
50 assert(p
->dev
->gen
== ILO_GEN(6));
53 if (p
->state
.has_gen6_wa_pipe_control
)
56 p
->state
.has_gen6_wa_pipe_control
= true;
59 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
61 * "Pipe-control with CS-stall bit set must be sent BEFORE the
62 * pipe-control with a post-sync op and no write-cache flushes."
64 * The workaround below necessitates this workaround.
66 p
->gen6_PIPE_CONTROL(p
->dev
,
67 PIPE_CONTROL_CS_STALL
|
68 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
69 NULL
, 0, false, p
->cp
);
71 /* the caller will emit the post-sync op */
76 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
78 * "Before any depth stall flush (including those produced by
79 * non-pipelined state commands), software needs to first send a
80 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
82 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
83 * PIPE_CONTROL with any non-zero post-sync-op is required."
85 p
->gen6_PIPE_CONTROL(p
->dev
,
86 PIPE_CONTROL_WRITE_IMMEDIATE
,
87 p
->workaround_bo
, 0, false, p
->cp
);
91 gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline
*p
)
93 assert(p
->dev
->gen
== ILO_GEN(6));
95 gen6_wa_pipe_control_post_sync(p
, false);
98 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
100 * "Driver must guarentee that all the caches in the depth pipe are
101 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
102 * requires driver to send a PIPE_CONTROL with a CS stall along with a
103 * Depth Flush prior to this command."
105 p
->gen6_PIPE_CONTROL(p
->dev
,
106 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
107 PIPE_CONTROL_CS_STALL
,
112 gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline
*p
)
114 assert(p
->dev
->gen
== ILO_GEN(6));
116 gen6_wa_pipe_control_post_sync(p
, false);
119 * According to intel_emit_depth_stall_flushes() of classic i965, we need
120 * to emit a sequence of PIPE_CONTROLs prior to emitting depth related
123 p
->gen6_PIPE_CONTROL(p
->dev
,
124 PIPE_CONTROL_DEPTH_STALL
,
125 NULL
, 0, false, p
->cp
);
127 p
->gen6_PIPE_CONTROL(p
->dev
,
128 PIPE_CONTROL_DEPTH_CACHE_FLUSH
,
129 NULL
, 0, false, p
->cp
);
131 p
->gen6_PIPE_CONTROL(p
->dev
,
132 PIPE_CONTROL_DEPTH_STALL
,
133 NULL
, 0, false, p
->cp
);
137 gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline
*p
)
139 assert(p
->dev
->gen
== ILO_GEN(6));
141 /* the post-sync workaround should cover this already */
142 if (p
->state
.has_gen6_wa_pipe_control
)
146 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
148 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
149 * field set (DW1 Bit 1), must be issued prior to any change to the
150 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
152 p
->gen6_PIPE_CONTROL(p
->dev
,
153 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
154 NULL
, 0, false, p
->cp
);
159 gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline
*p
)
161 assert(p
->dev
->gen
== ILO_GEN(6));
163 gen6_wa_pipe_control_post_sync(p
, false);
166 * According to upload_vs_state() of classic i965, we need to emit
167 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
168 * buffered by VS FF, to the point that the FF dies.
170 p
->gen6_PIPE_CONTROL(p
->dev
,
171 PIPE_CONTROL_DEPTH_STALL
|
172 PIPE_CONTROL_INSTRUCTION_FLUSH
|
173 PIPE_CONTROL_STATE_CACHE_INVALIDATE
,
174 NULL
, 0, false, p
->cp
);
177 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
180 gen6_pipeline_common_select(struct ilo_3d_pipeline
*p
,
181 const struct ilo_context
*ilo
,
182 struct gen6_pipeline_session
*session
)
184 /* PIPELINE_SELECT */
185 if (session
->hw_ctx_changed
) {
186 if (p
->dev
->gen
== ILO_GEN(6))
187 gen6_wa_pipe_control_post_sync(p
, false);
189 p
->gen6_PIPELINE_SELECT(p
->dev
, 0x0, p
->cp
);
194 gen6_pipeline_common_sip(struct ilo_3d_pipeline
*p
,
195 const struct ilo_context
*ilo
,
196 struct gen6_pipeline_session
*session
)
199 if (session
->hw_ctx_changed
) {
200 if (p
->dev
->gen
== ILO_GEN(6))
201 gen6_wa_pipe_control_post_sync(p
, false);
203 p
->gen6_STATE_SIP(p
->dev
, 0, p
->cp
);
208 gen6_pipeline_common_base_address(struct ilo_3d_pipeline
*p
,
209 const struct ilo_context
*ilo
,
210 struct gen6_pipeline_session
*session
)
212 /* STATE_BASE_ADDRESS */
213 if (session
->state_bo_changed
|| session
->instruction_bo_changed
) {
214 if (p
->dev
->gen
== ILO_GEN(6))
215 gen6_wa_pipe_control_post_sync(p
, false);
217 p
->gen6_STATE_BASE_ADDRESS(p
->dev
,
218 NULL
, p
->cp
->bo
, p
->cp
->bo
, NULL
, ilo
->shader_cache
->bo
,
222 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
224 * "The following commands must be reissued following any change to
225 * the base addresses:
227 * * 3DSTATE_BINDING_TABLE_POINTERS
228 * * 3DSTATE_SAMPLER_STATE_POINTERS
229 * * 3DSTATE_VIEWPORT_STATE_POINTERS
230 * * 3DSTATE_CC_POINTERS
231 * * MEDIA_STATE_POINTERS"
233 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
234 * reasonable to also reissue the command. Same to PCB.
236 session
->viewport_state_changed
= true;
238 session
->cc_state_blend_changed
= true;
239 session
->cc_state_dsa_changed
= true;
240 session
->cc_state_cc_changed
= true;
242 session
->scissor_state_changed
= true;
244 session
->binding_table_vs_changed
= true;
245 session
->binding_table_gs_changed
= true;
246 session
->binding_table_fs_changed
= true;
248 session
->sampler_state_vs_changed
= true;
249 session
->sampler_state_gs_changed
= true;
250 session
->sampler_state_fs_changed
= true;
252 session
->pcb_state_vs_changed
= true;
253 session
->pcb_state_gs_changed
= true;
254 session
->pcb_state_fs_changed
= true;
259 gen6_pipeline_common_urb(struct ilo_3d_pipeline
*p
,
260 const struct ilo_context
*ilo
,
261 struct gen6_pipeline_session
*session
)
264 if (DIRTY(VERTEX_ELEMENTS
) || DIRTY(VS
) || DIRTY(GS
)) {
265 const struct ilo_shader
*vs
= (ilo
->vs
) ? ilo
->vs
->shader
: NULL
;
266 const struct ilo_shader
*gs
= (ilo
->gs
) ? ilo
->gs
->shader
: NULL
;
267 const bool gs_active
= (gs
|| (vs
&& vs
->stream_output
));
268 int vs_entry_size
, gs_entry_size
;
269 int vs_total_size
, gs_total_size
;
271 vs_entry_size
= (vs
) ? vs
->out
.count
: 0;
274 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
275 * share VUE handles. The VUE allocation size must be large enough to
276 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
278 * I am not sure if the PRM explicitly states that VF and VS share VUE
279 * handles. But here is a citation that implies so:
281 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
283 * "Once a FF stage that spawn threads has sufficient input to
284 * initiate a thread, it must guarantee that it is safe to request
285 * the thread initiation. For all these FF stages, this check is
288 * - The availability of output URB entries:
289 * - VS: As the input URB entries are overwritten with the
290 * VS-generated output data, output URB availability isn't a
293 if (vs_entry_size
< ilo
->ve
->count
)
294 vs_entry_size
= ilo
->ve
->count
;
296 gs_entry_size
= (gs
) ? gs
->out
.count
:
297 (vs
&& vs
->stream_output
) ? vs_entry_size
: 0;
300 vs_entry_size
*= sizeof(float) * 4;
301 gs_entry_size
*= sizeof(float) * 4;
302 vs_total_size
= ilo
->dev
->urb_size
;
306 gs_total_size
= vs_total_size
;
312 p
->gen6_3DSTATE_URB(p
->dev
, vs_total_size
, gs_total_size
,
313 vs_entry_size
, gs_entry_size
, p
->cp
);
316 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
318 * "Because of a urb corruption caused by allocating a previous
319 * gsunit's urb entry to vsunit software is required to send a
320 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
321 * size == 0) plus a dummy DRAW call before any case where VS will
322 * be taking over GS URB space."
324 if (p
->state
.gs
.active
&& !gs_active
)
325 ilo_3d_pipeline_emit_flush_gen6(p
);
327 p
->state
.gs
.active
= gs_active
;
332 gen6_pipeline_common_pointers_1(struct ilo_3d_pipeline
*p
,
333 const struct ilo_context
*ilo
,
334 struct gen6_pipeline_session
*session
)
336 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
337 if (session
->viewport_state_changed
) {
338 p
->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p
->dev
,
339 p
->state
.CLIP_VIEWPORT
,
340 p
->state
.SF_VIEWPORT
,
341 p
->state
.CC_VIEWPORT
, p
->cp
);
346 gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline
*p
,
347 const struct ilo_context
*ilo
,
348 struct gen6_pipeline_session
*session
)
350 /* 3DSTATE_CC_STATE_POINTERS */
351 if (session
->cc_state_blend_changed
||
352 session
->cc_state_dsa_changed
||
353 session
->cc_state_cc_changed
) {
354 p
->gen6_3DSTATE_CC_STATE_POINTERS(p
->dev
,
355 p
->state
.BLEND_STATE
,
356 p
->state
.DEPTH_STENCIL_STATE
,
357 p
->state
.COLOR_CALC_STATE
, p
->cp
);
360 /* 3DSTATE_SAMPLER_STATE_POINTERS */
361 if (session
->sampler_state_vs_changed
||
362 session
->sampler_state_gs_changed
||
363 session
->sampler_state_fs_changed
) {
364 p
->gen6_3DSTATE_SAMPLER_STATE_POINTERS(p
->dev
,
365 p
->state
.vs
.SAMPLER_STATE
,
367 p
->state
.wm
.SAMPLER_STATE
, p
->cp
);
372 gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline
*p
,
373 const struct ilo_context
*ilo
,
374 struct gen6_pipeline_session
*session
)
376 /* 3DSTATE_SCISSOR_STATE_POINTERS */
377 if (session
->scissor_state_changed
) {
378 p
->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p
->dev
,
379 p
->state
.SCISSOR_RECT
, p
->cp
);
382 /* 3DSTATE_BINDING_TABLE_POINTERS */
383 if (session
->binding_table_vs_changed
||
384 session
->binding_table_gs_changed
||
385 session
->binding_table_fs_changed
) {
386 p
->gen6_3DSTATE_BINDING_TABLE_POINTERS(p
->dev
,
387 p
->state
.vs
.BINDING_TABLE_STATE
,
388 p
->state
.gs
.BINDING_TABLE_STATE
,
389 p
->state
.wm
.BINDING_TABLE_STATE
, p
->cp
);
394 gen6_pipeline_vf(struct ilo_3d_pipeline
*p
,
395 const struct ilo_context
*ilo
,
396 struct gen6_pipeline_session
*session
)
398 /* 3DSTATE_INDEX_BUFFER */
399 if (DIRTY(INDEX_BUFFER
)) {
400 p
->gen6_3DSTATE_INDEX_BUFFER(p
->dev
,
401 &ilo
->ib
.state
, session
->info
->primitive_restart
, p
->cp
);
404 /* 3DSTATE_VERTEX_BUFFERS */
405 if (DIRTY(VERTEX_BUFFERS
) || DIRTY(VERTEX_ELEMENTS
)) {
406 p
->gen6_3DSTATE_VERTEX_BUFFERS(p
->dev
,
407 ilo
->vb
.states
, ilo
->vb
.enabled_mask
, ilo
->ve
, p
->cp
);
410 /* 3DSTATE_VERTEX_ELEMENTS */
411 if (DIRTY(VERTEX_ELEMENTS
) || DIRTY(VS
)) {
412 const struct ilo_ve_state
*ve
= ilo
->ve
;
413 bool last_velement_edgeflag
= false;
414 bool prepend_generate_ids
= false;
417 const struct ilo_shader_info
*info
= &ilo
->vs
->info
;
419 if (info
->edgeflag_in
>= 0) {
420 /* we rely on the state tracker here */
421 assert(info
->edgeflag_in
== ve
->count
- 1);
422 last_velement_edgeflag
= true;
425 prepend_generate_ids
= (info
->has_instanceid
|| info
->has_vertexid
);
428 p
->gen6_3DSTATE_VERTEX_ELEMENTS(p
->dev
, ve
,
429 last_velement_edgeflag
, prepend_generate_ids
, p
->cp
);
434 gen6_pipeline_vf_statistics(struct ilo_3d_pipeline
*p
,
435 const struct ilo_context
*ilo
,
436 struct gen6_pipeline_session
*session
)
438 /* 3DSTATE_VF_STATISTICS */
439 if (session
->hw_ctx_changed
)
440 p
->gen6_3DSTATE_VF_STATISTICS(p
->dev
, false, p
->cp
);
444 gen6_pipeline_vf_draw(struct ilo_3d_pipeline
*p
,
445 const struct ilo_context
*ilo
,
446 struct gen6_pipeline_session
*session
)
449 p
->gen6_3DPRIMITIVE(p
->dev
, session
->info
, false, p
->cp
);
450 p
->state
.has_gen6_wa_pipe_control
= false;
454 gen6_pipeline_vs(struct ilo_3d_pipeline
*p
,
455 const struct ilo_context
*ilo
,
456 struct gen6_pipeline_session
*session
)
458 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(VERTEX_SAMPLERS
));
459 const bool emit_3dstate_constant_vs
= session
->pcb_state_vs_changed
;
462 * the classic i965 does this in upload_vs_state(), citing a spec that I
465 if (emit_3dstate_vs
&& p
->dev
->gen
== ILO_GEN(6))
466 gen6_wa_pipe_control_post_sync(p
, false);
468 /* 3DSTATE_CONSTANT_VS */
469 if (emit_3dstate_constant_vs
) {
470 p
->gen6_3DSTATE_CONSTANT_VS(p
->dev
,
471 &p
->state
.vs
.PUSH_CONSTANT_BUFFER
,
472 &p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
477 if (emit_3dstate_vs
) {
478 const struct ilo_shader
*vs
= (ilo
->vs
)? ilo
->vs
->shader
: NULL
;
479 const int num_samplers
= ilo
->sampler
[PIPE_SHADER_VERTEX
].count
;
481 p
->gen6_3DSTATE_VS(p
->dev
, vs
, num_samplers
, p
->cp
);
484 if (emit_3dstate_constant_vs
&& p
->dev
->gen
== ILO_GEN(6))
485 gen6_wa_pipe_control_vs_const_flush(p
);
489 gen6_pipeline_gs(struct ilo_3d_pipeline
*p
,
490 const struct ilo_context
*ilo
,
491 struct gen6_pipeline_session
*session
)
493 /* 3DSTATE_CONSTANT_GS */
494 if (session
->pcb_state_gs_changed
)
495 p
->gen6_3DSTATE_CONSTANT_GS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
498 if (DIRTY(GS
) || DIRTY(VS
) || session
->prim_changed
) {
499 const struct ilo_shader
*gs
= (ilo
->gs
)? ilo
->gs
->shader
: NULL
;
500 const struct ilo_shader
*vs
= (ilo
->vs
)? ilo
->vs
->shader
: NULL
;
501 const int num_vertices
= u_vertices_per_prim(session
->reduced_prim
);
504 assert(!gs
->pcb
.clip_state_size
);
506 p
->gen6_3DSTATE_GS(p
->dev
, gs
, vs
,
507 (vs
) ? vs
->cache_offset
+ vs
->gs_offsets
[num_vertices
- 1] : 0,
513 gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline
*p
,
514 const struct ilo_context
*ilo
,
515 struct gen6_pipeline_session
*session
)
517 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(STREAM_OUTPUT_TARGETS
)) {
518 const struct pipe_stream_output_info
*so_info
=
519 (ilo
->gs
) ? &ilo
->gs
->info
.stream_output
:
520 (ilo
->vs
) ? &ilo
->vs
->info
.stream_output
: NULL
;
521 unsigned max_svbi
= 0xffffffff;
524 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
525 const int output_buffer
= so_info
->output
[i
].output_buffer
;
526 const struct pipe_stream_output_target
*so
=
527 ilo
->so
.states
[output_buffer
];
528 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
529 const int elem_size
= so_info
->output
[i
].num_components
* 4;
537 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
539 count
= buf_size
/ struct_size
;
540 if (buf_size
% struct_size
>= elem_size
)
543 if (count
< max_svbi
)
547 if (p
->state
.so_max_vertices
!= max_svbi
) {
548 p
->state
.so_max_vertices
= max_svbi
;
557 gen6_pipeline_gs_svbi(struct ilo_3d_pipeline
*p
,
558 const struct ilo_context
*ilo
,
559 struct gen6_pipeline_session
*session
)
561 const bool emit
= gen6_pipeline_update_max_svbi(p
, ilo
, session
);
563 /* 3DSTATE_GS_SVB_INDEX */
565 if (p
->dev
->gen
== ILO_GEN(6))
566 gen6_wa_pipe_control_post_sync(p
, false);
568 p
->gen6_3DSTATE_GS_SVB_INDEX(p
->dev
,
569 0, p
->state
.so_num_vertices
, p
->state
.so_max_vertices
,
572 if (session
->hw_ctx_changed
) {
576 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
578 * "If a buffer is not enabled then the SVBI must be set to 0x0
579 * in order to not cause overflow in that SVBI."
581 * "If a buffer is not enabled then the MaxSVBI must be set to
582 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
584 for (i
= 1; i
< 4; i
++) {
585 p
->gen6_3DSTATE_GS_SVB_INDEX(p
->dev
,
586 i
, 0, 0xffffffff, false, p
->cp
);
593 gen6_pipeline_clip(struct ilo_3d_pipeline
*p
,
594 const struct ilo_context
*ilo
,
595 struct gen6_pipeline_session
*session
)
598 if (DIRTY(RASTERIZER
) || DIRTY(FS
) ||
599 DIRTY(VIEWPORT
) || DIRTY(FRAMEBUFFER
)) {
600 bool enable_guardband
= true;
604 * We do not do 2D clipping yet. Guard band test should only be enabled
605 * when the viewport is larger than the framebuffer.
607 for (i
= 0; i
< ilo
->viewport
.count
; i
++) {
608 const struct ilo_viewport_cso
*vp
= &ilo
->viewport
.cso
[i
];
610 if (vp
->min_x
> 0.0f
|| vp
->max_x
< ilo
->fb
.state
.width
||
611 vp
->min_y
> 0.0f
|| vp
->max_y
< ilo
->fb
.state
.height
) {
612 enable_guardband
= false;
617 p
->gen6_3DSTATE_CLIP(p
->dev
,
618 &ilo
->rasterizer
->state
,
619 (ilo
->fs
&& ilo
->fs
->shader
->in
.has_linear_interp
),
620 enable_guardband
, 1, p
->cp
);
625 gen6_pipeline_sf(struct ilo_3d_pipeline
*p
,
626 const struct ilo_context
*ilo
,
627 struct gen6_pipeline_session
*session
)
630 if (DIRTY(RASTERIZER
) || DIRTY(VS
) || DIRTY(GS
) || DIRTY(FS
)) {
631 const struct ilo_shader
*fs
= (ilo
->fs
)? ilo
->fs
->shader
: NULL
;
632 const struct ilo_shader
*last_sh
=
633 (ilo
->gs
)? ilo
->gs
->shader
:
634 (ilo
->vs
)? ilo
->vs
->shader
: NULL
;
636 p
->gen6_3DSTATE_SF(p
->dev
,
637 &ilo
->rasterizer
->state
, fs
, last_sh
, p
->cp
);
642 gen6_pipeline_sf_rect(struct ilo_3d_pipeline
*p
,
643 const struct ilo_context
*ilo
,
644 struct gen6_pipeline_session
*session
)
646 /* 3DSTATE_DRAWING_RECTANGLE */
647 if (DIRTY(FRAMEBUFFER
)) {
648 if (p
->dev
->gen
== ILO_GEN(6))
649 gen6_wa_pipe_control_post_sync(p
, false);
651 p
->gen6_3DSTATE_DRAWING_RECTANGLE(p
->dev
, 0, 0,
652 ilo
->fb
.state
.width
, ilo
->fb
.state
.height
, p
->cp
);
657 gen6_pipeline_wm(struct ilo_3d_pipeline
*p
,
658 const struct ilo_context
*ilo
,
659 struct gen6_pipeline_session
*session
)
661 /* 3DSTATE_CONSTANT_PS */
662 if (session
->pcb_state_fs_changed
)
663 p
->gen6_3DSTATE_CONSTANT_PS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
666 if (DIRTY(FS
) || DIRTY(FRAGMENT_SAMPLERS
) ||
667 DIRTY(BLEND
) || DIRTY(DEPTH_STENCIL_ALPHA
) ||
669 const struct ilo_shader
*fs
= (ilo
->fs
)? ilo
->fs
->shader
: NULL
;
670 const int num_samplers
= ilo
->sampler
[PIPE_SHADER_FRAGMENT
].count
;
671 const bool dual_blend
= ilo
->blend
->dual_blend
;
672 const bool cc_may_kill
= (ilo
->dsa
->state
.alpha
.enabled
||
673 ilo
->blend
->alpha_to_coverage
);
676 assert(!fs
->pcb
.clip_state_size
);
678 if (p
->dev
->gen
== ILO_GEN(6) && session
->hw_ctx_changed
)
679 gen6_wa_pipe_control_wm_max_threads_stall(p
);
681 p
->gen6_3DSTATE_WM(p
->dev
, fs
, num_samplers
,
682 &ilo
->rasterizer
->state
, dual_blend
, cc_may_kill
, p
->cp
);
687 gen6_pipeline_wm_multisample(struct ilo_3d_pipeline
*p
,
688 const struct ilo_context
*ilo
,
689 struct gen6_pipeline_session
*session
)
691 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
692 if (DIRTY(SAMPLE_MASK
) || DIRTY(FRAMEBUFFER
)) {
693 const uint32_t *packed_sample_pos
;
695 packed_sample_pos
= (ilo
->fb
.num_samples
> 1) ?
696 &p
->packed_sample_position_4x
: &p
->packed_sample_position_1x
;
698 if (p
->dev
->gen
== ILO_GEN(6)) {
699 gen6_wa_pipe_control_post_sync(p
, false);
700 gen6_wa_pipe_control_wm_multisample_flush(p
);
703 p
->gen6_3DSTATE_MULTISAMPLE(p
->dev
,
704 ilo
->fb
.num_samples
, packed_sample_pos
,
705 ilo
->rasterizer
->state
.half_pixel_center
, p
->cp
);
707 p
->gen6_3DSTATE_SAMPLE_MASK(p
->dev
,
708 (ilo
->fb
.num_samples
> 1) ? ilo
->sample_mask
: 0x1, p
->cp
);
713 gen6_pipeline_wm_depth(struct ilo_3d_pipeline
*p
,
714 const struct ilo_context
*ilo
,
715 struct gen6_pipeline_session
*session
)
717 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
718 if (DIRTY(FRAMEBUFFER
)) {
719 if (p
->dev
->gen
== ILO_GEN(6)) {
720 gen6_wa_pipe_control_post_sync(p
, false);
721 gen6_wa_pipe_control_wm_depth_flush(p
);
724 p
->gen6_3DSTATE_DEPTH_BUFFER(p
->dev
, ilo
->fb
.state
.zsbuf
, p
->cp
);
727 p
->gen6_3DSTATE_CLEAR_PARAMS(p
->dev
, 0, p
->cp
);
732 gen6_pipeline_wm_raster(struct ilo_3d_pipeline
*p
,
733 const struct ilo_context
*ilo
,
734 struct gen6_pipeline_session
*session
)
736 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
737 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
738 ilo
->rasterizer
->state
.poly_stipple_enable
) {
739 if (p
->dev
->gen
== ILO_GEN(6))
740 gen6_wa_pipe_control_post_sync(p
, false);
742 p
->gen6_3DSTATE_POLY_STIPPLE_PATTERN(p
->dev
,
743 &ilo
->poly_stipple
, p
->cp
);
745 p
->gen6_3DSTATE_POLY_STIPPLE_OFFSET(p
->dev
, 0, 0, p
->cp
);
748 /* 3DSTATE_LINE_STIPPLE */
749 if (DIRTY(RASTERIZER
) && ilo
->rasterizer
->state
.line_stipple_enable
) {
750 if (p
->dev
->gen
== ILO_GEN(6))
751 gen6_wa_pipe_control_post_sync(p
, false);
753 p
->gen6_3DSTATE_LINE_STIPPLE(p
->dev
,
754 ilo
->rasterizer
->state
.line_stipple_pattern
,
755 ilo
->rasterizer
->state
.line_stipple_factor
+ 1, p
->cp
);
758 /* 3DSTATE_AA_LINE_PARAMETERS */
759 if (DIRTY(RASTERIZER
) && ilo
->rasterizer
->state
.line_smooth
) {
760 if (p
->dev
->gen
== ILO_GEN(6))
761 gen6_wa_pipe_control_post_sync(p
, false);
763 p
->gen6_3DSTATE_AA_LINE_PARAMETERS(p
->dev
, p
->cp
);
768 gen6_pipeline_state_viewports(struct ilo_3d_pipeline
*p
,
769 const struct ilo_context
*ilo
,
770 struct gen6_pipeline_session
*session
)
772 /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
773 if (p
->dev
->gen
>= ILO_GEN(7) && DIRTY(VIEWPORT
)) {
774 p
->state
.SF_CLIP_VIEWPORT
= p
->gen7_SF_CLIP_VIEWPORT(p
->dev
,
775 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
777 p
->state
.CC_VIEWPORT
= p
->gen6_CC_VIEWPORT(p
->dev
,
778 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
780 session
->viewport_state_changed
= true;
782 /* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
783 else if (DIRTY(VIEWPORT
)) {
784 p
->state
.CLIP_VIEWPORT
= p
->gen6_CLIP_VIEWPORT(p
->dev
,
785 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
787 p
->state
.SF_VIEWPORT
= p
->gen6_SF_VIEWPORT(p
->dev
,
788 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
790 p
->state
.CC_VIEWPORT
= p
->gen6_CC_VIEWPORT(p
->dev
,
791 ilo
->viewport
.cso
, ilo
->viewport
.count
, p
->cp
);
793 session
->viewport_state_changed
= true;
798 gen6_pipeline_state_cc(struct ilo_3d_pipeline
*p
,
799 const struct ilo_context
*ilo
,
800 struct gen6_pipeline_session
*session
)
803 if (DIRTY(BLEND
) || DIRTY(FRAMEBUFFER
) || DIRTY(DEPTH_STENCIL_ALPHA
)) {
804 p
->state
.BLEND_STATE
= p
->gen6_BLEND_STATE(p
->dev
,
805 ilo
->blend
, &ilo
->fb
, &ilo
->dsa
->state
.alpha
, p
->cp
);
807 session
->cc_state_blend_changed
= true;
810 /* COLOR_CALC_STATE */
811 if (DIRTY(DEPTH_STENCIL_ALPHA
) || DIRTY(STENCIL_REF
) || DIRTY(BLEND_COLOR
)) {
812 p
->state
.COLOR_CALC_STATE
=
813 p
->gen6_COLOR_CALC_STATE(p
->dev
, &ilo
->stencil_ref
,
814 ilo
->dsa
->state
.alpha
.ref_value
, &ilo
->blend_color
, p
->cp
);
816 session
->cc_state_cc_changed
= true;
819 /* DEPTH_STENCIL_STATE */
820 if (DIRTY(DEPTH_STENCIL_ALPHA
)) {
821 p
->state
.DEPTH_STENCIL_STATE
=
822 p
->gen6_DEPTH_STENCIL_STATE(p
->dev
, &ilo
->dsa
->state
, p
->cp
);
824 session
->cc_state_dsa_changed
= true;
829 gen6_pipeline_state_scissors(struct ilo_3d_pipeline
*p
,
830 const struct ilo_context
*ilo
,
831 struct gen6_pipeline_session
*session
)
834 if (DIRTY(SCISSOR
) || DIRTY(VIEWPORT
)) {
835 /* there should be as many scissors as there are viewports */
836 p
->state
.SCISSOR_RECT
= p
->gen6_SCISSOR_RECT(p
->dev
,
837 &ilo
->scissor
, ilo
->viewport
.count
, p
->cp
);
839 session
->scissor_state_changed
= true;
844 gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline
*p
,
845 const struct ilo_context
*ilo
,
846 struct gen6_pipeline_session
*session
)
848 /* SURFACE_STATEs for render targets */
849 if (DIRTY(FRAMEBUFFER
)) {
850 const int offset
= ILO_WM_DRAW_SURFACE(0);
851 uint32_t *surface_state
= &p
->state
.wm
.SURFACE_STATE
[offset
];
854 for (i
= 0; i
< ilo
->fb
.state
.nr_cbufs
; i
++) {
855 const struct pipe_surface
*surface
= ilo
->fb
.state
.cbufs
[i
];
859 p
->gen6_surf_SURFACE_STATE(p
->dev
, surface
, p
->cp
);
863 * Upload at least one render target, as
864 * brw_update_renderbuffer_surfaces() does. I don't know why.
867 struct pipe_surface null_surface
;
869 memset(&null_surface
, 0, sizeof(null_surface
));
870 null_surface
.width
= ilo
->fb
.state
.width
;
871 null_surface
.height
= ilo
->fb
.state
.height
;
874 p
->gen6_surf_SURFACE_STATE(p
->dev
, &null_surface
, p
->cp
);
879 memset(&surface_state
[i
], 0, (ILO_MAX_DRAW_BUFFERS
- i
) * 4);
881 if (i
&& session
->num_surfaces
[PIPE_SHADER_FRAGMENT
] < offset
+ i
)
882 session
->num_surfaces
[PIPE_SHADER_FRAGMENT
] = offset
+ i
;
884 session
->binding_table_fs_changed
= true;
889 gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline
*p
,
890 const struct ilo_context
*ilo
,
891 struct gen6_pipeline_session
*session
)
893 const struct ilo_shader_state
*vs
= ilo
->vs
;
894 const struct ilo_shader_state
*gs
= ilo
->gs
;
895 const struct pipe_stream_output_target
**so_targets
=
896 (const struct pipe_stream_output_target
**) ilo
->so
.states
;
897 const int num_so_targets
= ilo
->so
.count
;
899 if (p
->dev
->gen
!= ILO_GEN(6))
902 /* SURFACE_STATEs for stream output targets */
903 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(STREAM_OUTPUT_TARGETS
)) {
904 const struct pipe_stream_output_info
*so_info
=
905 (gs
) ? &gs
->info
.stream_output
:
906 (vs
) ? &vs
->info
.stream_output
: NULL
;
907 const int offset
= ILO_GS_SO_SURFACE(0);
908 uint32_t *surface_state
= &p
->state
.gs
.SURFACE_STATE
[offset
];
911 for (i
= 0; so_info
&& i
< so_info
->num_outputs
; i
++) {
912 const int target
= so_info
->output
[i
].output_buffer
;
913 const struct pipe_stream_output_target
*so_target
=
914 (target
< num_so_targets
) ? so_targets
[target
] : NULL
;
917 surface_state
[i
] = p
->gen6_so_SURFACE_STATE(p
->dev
,
918 so_target
, so_info
, i
, p
->cp
);
921 surface_state
[i
] = 0;
925 memset(&surface_state
[i
], 0, (ILO_MAX_SO_BINDINGS
- i
) * 4);
927 if (i
&& session
->num_surfaces
[PIPE_SHADER_GEOMETRY
] < offset
+ i
)
928 session
->num_surfaces
[PIPE_SHADER_GEOMETRY
] = offset
+ i
;
930 session
->binding_table_gs_changed
= true;
935 gen6_pipeline_state_surfaces_view(struct ilo_3d_pipeline
*p
,
936 const struct ilo_context
*ilo
,
938 struct gen6_pipeline_session
*session
)
940 const struct pipe_sampler_view
**views
=
941 (const struct pipe_sampler_view
**) ilo
->view
[shader_type
].states
;
942 const int num_views
= ilo
->view
[shader_type
].count
;
943 uint32_t *surface_state
;
947 /* SURFACE_STATEs for sampler views */
948 switch (shader_type
) {
949 case PIPE_SHADER_VERTEX
:
950 if (DIRTY(VERTEX_SAMPLER_VIEWS
)) {
951 offset
= ILO_VS_TEXTURE_SURFACE(0);
952 surface_state
= &p
->state
.vs
.SURFACE_STATE
[offset
];
954 session
->binding_table_vs_changed
= true;
960 case PIPE_SHADER_FRAGMENT
:
961 if (DIRTY(FRAGMENT_SAMPLER_VIEWS
)) {
962 offset
= ILO_WM_TEXTURE_SURFACE(0);
963 surface_state
= &p
->state
.wm
.SURFACE_STATE
[offset
];
965 session
->binding_table_fs_changed
= true;
979 for (i
= 0; i
< num_views
; i
++) {
982 p
->gen6_view_SURFACE_STATE(p
->dev
, views
[i
], p
->cp
);
985 surface_state
[i
] = 0;
989 memset(&surface_state
[i
], 0, (ILO_MAX_SAMPLER_VIEWS
- i
) * 4);
991 if (i
&& session
->num_surfaces
[shader_type
] < offset
+ i
)
992 session
->num_surfaces
[shader_type
] = offset
+ i
;
996 gen6_pipeline_state_surfaces_const(struct ilo_3d_pipeline
*p
,
997 const struct ilo_context
*ilo
,
999 struct gen6_pipeline_session
*session
)
1001 const struct pipe_constant_buffer
*buffers
=
1002 ilo
->cbuf
[shader_type
].states
;
1003 const int num_buffers
= ilo
->cbuf
[shader_type
].count
;
1004 uint32_t *surface_state
;
1008 /* SURFACE_STATEs for constant buffers */
1009 switch (shader_type
) {
1010 case PIPE_SHADER_VERTEX
:
1011 if (DIRTY(CONSTANT_BUFFER
)) {
1012 offset
= ILO_VS_CONST_SURFACE(0);
1013 surface_state
= &p
->state
.vs
.SURFACE_STATE
[offset
];
1015 session
->binding_table_vs_changed
= true;
1021 case PIPE_SHADER_FRAGMENT
:
1022 if (DIRTY(CONSTANT_BUFFER
)) {
1023 offset
= ILO_WM_CONST_SURFACE(0);
1024 surface_state
= &p
->state
.wm
.SURFACE_STATE
[offset
];
1026 session
->binding_table_fs_changed
= true;
1040 for (i
= 0; i
< num_buffers
; i
++) {
1041 if (buffers
[i
].buffer
) {
1043 p
->gen6_cbuf_SURFACE_STATE(p
->dev
, &buffers
[i
], p
->cp
);
1046 surface_state
[i
] = 0;
1050 memset(&surface_state
[i
], 0, (ILO_MAX_CONST_BUFFERS
- i
) * 4);
1052 if (i
&& session
->num_surfaces
[shader_type
] < offset
+ i
)
1053 session
->num_surfaces
[shader_type
] = offset
+ i
;
1057 gen6_pipeline_state_binding_tables(struct ilo_3d_pipeline
*p
,
1058 const struct ilo_context
*ilo
,
1060 struct gen6_pipeline_session
*session
)
1062 uint32_t *binding_table_state
, *surface_state
;
1063 int *binding_table_state_size
, size
;
1066 /* BINDING_TABLE_STATE */
1067 switch (shader_type
) {
1068 case PIPE_SHADER_VERTEX
:
1069 surface_state
= p
->state
.vs
.SURFACE_STATE
;
1070 binding_table_state
= &p
->state
.vs
.BINDING_TABLE_STATE
;
1071 binding_table_state_size
= &p
->state
.vs
.BINDING_TABLE_STATE_size
;
1073 skip
= !session
->binding_table_vs_changed
;
1075 case PIPE_SHADER_GEOMETRY
:
1076 surface_state
= p
->state
.gs
.SURFACE_STATE
;
1077 binding_table_state
= &p
->state
.gs
.BINDING_TABLE_STATE
;
1078 binding_table_state_size
= &p
->state
.gs
.BINDING_TABLE_STATE_size
;
1080 skip
= !session
->binding_table_gs_changed
;
1082 case PIPE_SHADER_FRAGMENT
:
1083 surface_state
= p
->state
.wm
.SURFACE_STATE
;
1084 binding_table_state
= &p
->state
.wm
.BINDING_TABLE_STATE
;
1085 binding_table_state_size
= &p
->state
.wm
.BINDING_TABLE_STATE_size
;
1087 skip
= !session
->binding_table_fs_changed
;
1098 * If we have seemingly less SURFACE_STATEs than before, it could be that
1099 * we did not touch those reside at the tail in this upload. Loop over
1100 * them to figure out the real number of SURFACE_STATEs.
1102 for (size
= *binding_table_state_size
;
1103 size
> session
->num_surfaces
[shader_type
]; size
--) {
1104 if (surface_state
[size
- 1])
1107 if (size
< session
->num_surfaces
[shader_type
])
1108 size
= session
->num_surfaces
[shader_type
];
1110 *binding_table_state
= p
->gen6_BINDING_TABLE_STATE(p
->dev
,
1111 surface_state
, size
, p
->cp
);
1112 *binding_table_state_size
= size
;
1116 gen6_pipeline_state_samplers(struct ilo_3d_pipeline
*p
,
1117 const struct ilo_context
*ilo
,
1119 struct gen6_pipeline_session
*session
)
1121 const struct ilo_sampler_cso
* const *samplers
=
1122 ilo
->sampler
[shader_type
].cso
;
1123 const struct pipe_sampler_view
**views
=
1124 (const struct pipe_sampler_view
**) ilo
->view
[shader_type
].states
;
1125 const int num_samplers
= ilo
->sampler
[shader_type
].count
;
1126 const int num_views
= ilo
->view
[shader_type
].count
;
1127 uint32_t *sampler_state
, *border_color_state
;
1128 bool emit_border_color
= false;
1131 /* SAMPLER_BORDER_COLOR_STATE and SAMPLER_STATE */
1132 switch (shader_type
) {
1133 case PIPE_SHADER_VERTEX
:
1134 if (DIRTY(VERTEX_SAMPLERS
) || DIRTY(VERTEX_SAMPLER_VIEWS
)) {
1135 sampler_state
= &p
->state
.vs
.SAMPLER_STATE
;
1136 border_color_state
= p
->state
.vs
.SAMPLER_BORDER_COLOR_STATE
;
1138 if (DIRTY(VERTEX_SAMPLERS
))
1139 emit_border_color
= true;
1141 session
->sampler_state_vs_changed
= true;
1147 case PIPE_SHADER_FRAGMENT
:
1148 if (DIRTY(FRAGMENT_SAMPLERS
) || DIRTY(FRAGMENT_SAMPLER_VIEWS
)) {
1149 sampler_state
= &p
->state
.wm
.SAMPLER_STATE
;
1150 border_color_state
= p
->state
.wm
.SAMPLER_BORDER_COLOR_STATE
;
1152 if (DIRTY(FRAGMENT_SAMPLERS
))
1153 emit_border_color
= true;
1155 session
->sampler_state_fs_changed
= true;
1169 if (emit_border_color
) {
1172 for (i
= 0; i
< num_samplers
; i
++) {
1173 border_color_state
[i
] = (samplers
[i
]) ?
1174 p
->gen6_SAMPLER_BORDER_COLOR_STATE(p
->dev
,
1175 samplers
[i
], p
->cp
) : 0;
1179 /* should we take the minimum of num_samplers and num_views? */
1180 *sampler_state
= p
->gen6_SAMPLER_STATE(p
->dev
,
1183 MIN2(num_samplers
, num_views
), p
->cp
);
1187 gen6_pipeline_state_pcb(struct ilo_3d_pipeline
*p
,
1188 const struct ilo_context
*ilo
,
1189 struct gen6_pipeline_session
*session
)
1191 /* push constant buffer for VS */
1192 if (DIRTY(VS
) || DIRTY(CLIP
)) {
1193 const struct ilo_shader
*vs
= (ilo
->vs
)? ilo
->vs
->shader
: NULL
;
1195 if (vs
&& vs
->pcb
.clip_state_size
) {
1198 p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
= vs
->pcb
.clip_state_size
;
1199 p
->state
.vs
.PUSH_CONSTANT_BUFFER
=
1200 p
->gen6_push_constant_buffer(p
->dev
,
1201 p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
, &pcb
, p
->cp
);
1203 memcpy(pcb
, &ilo
->clip
, vs
->pcb
.clip_state_size
);
1206 p
->state
.vs
.PUSH_CONSTANT_BUFFER_size
= 0;
1207 p
->state
.vs
.PUSH_CONSTANT_BUFFER
= 0;
1210 session
->pcb_state_vs_changed
= true;
1217 gen6_pipeline_commands(struct ilo_3d_pipeline
*p
,
1218 const struct ilo_context
*ilo
,
1219 struct gen6_pipeline_session
*session
)
1222 * We try to keep the order of the commands match, as closely as possible,
1223 * that of the classic i965 driver. It allows us to compare the command
1226 gen6_pipeline_common_select(p
, ilo
, session
);
1227 gen6_pipeline_gs_svbi(p
, ilo
, session
);
1228 gen6_pipeline_common_sip(p
, ilo
, session
);
1229 gen6_pipeline_vf_statistics(p
, ilo
, session
);
1230 gen6_pipeline_common_base_address(p
, ilo
, session
);
1231 gen6_pipeline_common_pointers_1(p
, ilo
, session
);
1232 gen6_pipeline_common_urb(p
, ilo
, session
);
1233 gen6_pipeline_common_pointers_2(p
, ilo
, session
);
1234 gen6_pipeline_wm_multisample(p
, ilo
, session
);
1235 gen6_pipeline_vs(p
, ilo
, session
);
1236 gen6_pipeline_gs(p
, ilo
, session
);
1237 gen6_pipeline_clip(p
, ilo
, session
);
1238 gen6_pipeline_sf(p
, ilo
, session
);
1239 gen6_pipeline_wm(p
, ilo
, session
);
1240 gen6_pipeline_common_pointers_3(p
, ilo
, session
);
1241 gen6_pipeline_wm_depth(p
, ilo
, session
);
1242 gen6_pipeline_wm_raster(p
, ilo
, session
);
1243 gen6_pipeline_sf_rect(p
, ilo
, session
);
1244 gen6_pipeline_vf(p
, ilo
, session
);
1245 gen6_pipeline_vf_draw(p
, ilo
, session
);
1249 gen6_pipeline_states(struct ilo_3d_pipeline
*p
,
1250 const struct ilo_context
*ilo
,
1251 struct gen6_pipeline_session
*session
)
1255 gen6_pipeline_state_viewports(p
, ilo
, session
);
1256 gen6_pipeline_state_cc(p
, ilo
, session
);
1257 gen6_pipeline_state_scissors(p
, ilo
, session
);
1258 gen6_pipeline_state_pcb(p
, ilo
, session
);
1261 * upload all SURAFCE_STATEs together so that we know there are minimal
1264 gen6_pipeline_state_surfaces_rt(p
, ilo
, session
);
1265 gen6_pipeline_state_surfaces_so(p
, ilo
, session
);
1266 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
1267 gen6_pipeline_state_surfaces_view(p
, ilo
, shader_type
, session
);
1268 gen6_pipeline_state_surfaces_const(p
, ilo
, shader_type
, session
);
1271 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
1272 gen6_pipeline_state_samplers(p
, ilo
, shader_type
, session
);
1273 /* this must be called after all SURFACE_STATEs are uploaded */
1274 gen6_pipeline_state_binding_tables(p
, ilo
, shader_type
, session
);
1279 gen6_pipeline_prepare(const struct ilo_3d_pipeline
*p
,
1280 const struct ilo_context
*ilo
,
1281 const struct pipe_draw_info
*info
,
1282 struct gen6_pipeline_session
*session
)
1284 memset(session
, 0, sizeof(*session
));
1285 session
->info
= info
;
1286 session
->pipe_dirty
= ilo
->dirty
;
1287 session
->reduced_prim
= u_reduced_prim(info
->mode
);
1289 /* available space before the session */
1290 session
->init_cp_space
= ilo_cp_space(p
->cp
);
1292 session
->hw_ctx_changed
=
1293 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_HW
);
1295 if (session
->hw_ctx_changed
) {
1296 /* these should be enough to make everything uploaded */
1297 session
->state_bo_changed
= true;
1298 session
->instruction_bo_changed
= true;
1299 session
->prim_changed
= true;
1302 session
->state_bo_changed
=
1303 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_STATE_BO
);
1304 session
->instruction_bo_changed
=
1305 (p
->invalidate_flags
& ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO
);
1306 session
->prim_changed
= (p
->state
.reduced_prim
!= session
->reduced_prim
);
1311 gen6_pipeline_draw(struct ilo_3d_pipeline
*p
,
1312 const struct ilo_context
*ilo
,
1313 struct gen6_pipeline_session
*session
)
1315 /* force all states to be uploaded if the state bo changed */
1316 if (session
->state_bo_changed
)
1317 session
->pipe_dirty
= ILO_DIRTY_ALL
;
1319 session
->pipe_dirty
= ilo
->dirty
;
1321 session
->emit_draw_states(p
, ilo
, session
);
1323 /* force all commands to be uploaded if the HW context changed */
1324 if (session
->hw_ctx_changed
)
1325 session
->pipe_dirty
= ILO_DIRTY_ALL
;
1327 session
->pipe_dirty
= ilo
->dirty
;
1329 session
->emit_draw_commands(p
, ilo
, session
);
1333 gen6_pipeline_end(struct ilo_3d_pipeline
*p
,
1334 const struct ilo_context
*ilo
,
1335 struct gen6_pipeline_session
*session
)
1339 /* sanity check size estimation */
1340 used
= session
->init_cp_space
- ilo_cp_space(p
->cp
);
1341 estimate
= ilo_3d_pipeline_estimate_size(p
, ILO_3D_PIPELINE_DRAW
, ilo
);
1342 assert(used
<= estimate
);
1344 p
->state
.reduced_prim
= session
->reduced_prim
;
1348 ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline
*p
,
1349 const struct ilo_context
*ilo
,
1350 const struct pipe_draw_info
*info
)
1352 struct gen6_pipeline_session session
;
1354 gen6_pipeline_prepare(p
, ilo
, info
, &session
);
1356 session
.emit_draw_states
= gen6_pipeline_states
;
1357 session
.emit_draw_commands
= gen6_pipeline_commands
;
1359 gen6_pipeline_draw(p
, ilo
, &session
);
1360 gen6_pipeline_end(p
, ilo
, &session
);
1364 ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline
*p
)
1366 if (p
->dev
->gen
== ILO_GEN(6))
1367 gen6_wa_pipe_control_post_sync(p
, false);
1369 p
->gen6_PIPE_CONTROL(p
->dev
,
1370 PIPE_CONTROL_INSTRUCTION_FLUSH
|
1371 PIPE_CONTROL_WRITE_FLUSH
|
1372 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1373 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
1374 PIPE_CONTROL_TC_FLUSH
|
1375 PIPE_CONTROL_NO_WRITE
|
1376 PIPE_CONTROL_CS_STALL
,
1377 0, 0, false, p
->cp
);
1381 ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline
*p
,
1382 struct intel_bo
*bo
, int index
)
1384 if (p
->dev
->gen
== ILO_GEN(6))
1385 gen6_wa_pipe_control_post_sync(p
, true);
1387 p
->gen6_PIPE_CONTROL(p
->dev
,
1388 PIPE_CONTROL_WRITE_TIMESTAMP
,
1389 bo
, index
* sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE
,
1394 ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline
*p
,
1395 struct intel_bo
*bo
, int index
)
1397 if (p
->dev
->gen
== ILO_GEN(6))
1398 gen6_wa_pipe_control_post_sync(p
, false);
1400 p
->gen6_PIPE_CONTROL(p
->dev
,
1401 PIPE_CONTROL_DEPTH_STALL
|
1402 PIPE_CONTROL_WRITE_DEPTH_COUNT
,
1403 bo
, index
* sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE
,
1408 gen6_pipeline_estimate_commands(const struct ilo_3d_pipeline
*p
,
1409 const struct ilo_gpe_gen6
*gen6
,
1410 const struct ilo_context
*ilo
)
1413 enum ilo_gpe_gen6_command cmd
;
1418 for (cmd
= 0; cmd
< ILO_GPE_GEN6_COMMAND_COUNT
; cmd
++) {
1422 case ILO_GPE_GEN6_PIPE_CONTROL
:
1423 /* for the workaround */
1425 /* another one after 3DSTATE_URB */
1427 /* and another one after 3DSTATE_CONSTANT_VS */
1430 case ILO_GPE_GEN6_3DSTATE_GS_SVB_INDEX
:
1431 /* there are 4 SVBIs */
1434 case ILO_GPE_GEN6_3DSTATE_VERTEX_BUFFERS
:
1437 case ILO_GPE_GEN6_3DSTATE_VERTEX_ELEMENTS
:
1440 case ILO_GPE_GEN6_MEDIA_VFE_STATE
:
1441 case ILO_GPE_GEN6_MEDIA_CURBE_LOAD
:
1442 case ILO_GPE_GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD
:
1443 case ILO_GPE_GEN6_MEDIA_GATEWAY_STATE
:
1444 case ILO_GPE_GEN6_MEDIA_STATE_FLUSH
:
1445 case ILO_GPE_GEN6_MEDIA_OBJECT_WALKER
:
1446 /* media commands */
1455 size
+= gen6
->estimate_command_size(p
->dev
, cmd
, count
);
1462 gen6_pipeline_estimate_states(const struct ilo_3d_pipeline
*p
,
1463 const struct ilo_gpe_gen6
*gen6
,
1464 const struct ilo_context
*ilo
)
1466 static int static_size
;
1467 int shader_type
, count
, size
;
1471 enum ilo_gpe_gen6_state state
;
1473 } static_states
[] = {
1475 { ILO_GPE_GEN6_SF_VIEWPORT
, 1 },
1476 { ILO_GPE_GEN6_CLIP_VIEWPORT
, 1 },
1477 { ILO_GPE_GEN6_CC_VIEWPORT
, 1 },
1479 { ILO_GPE_GEN6_COLOR_CALC_STATE
, 1 },
1480 { ILO_GPE_GEN6_BLEND_STATE
, ILO_MAX_DRAW_BUFFERS
},
1481 { ILO_GPE_GEN6_DEPTH_STENCIL_STATE
, 1 },
1483 { ILO_GPE_GEN6_SCISSOR_RECT
, 1 },
1484 /* binding table (vs, gs, fs) */
1485 { ILO_GPE_GEN6_BINDING_TABLE_STATE
, ILO_MAX_VS_SURFACES
},
1486 { ILO_GPE_GEN6_BINDING_TABLE_STATE
, ILO_MAX_GS_SURFACES
},
1487 { ILO_GPE_GEN6_BINDING_TABLE_STATE
, ILO_MAX_WM_SURFACES
},
1491 for (i
= 0; i
< Elements(static_states
); i
++) {
1492 static_size
+= gen6
->estimate_state_size(p
->dev
,
1493 static_states
[i
].state
,
1494 static_states
[i
].count
);
1501 * render targets (fs)
1502 * stream outputs (gs)
1503 * sampler views (vs, fs)
1504 * constant buffers (vs, fs)
1506 count
= ilo
->fb
.state
.nr_cbufs
;
1509 count
+= ilo
->gs
->info
.stream_output
.num_outputs
;
1511 count
+= ilo
->vs
->info
.stream_output
.num_outputs
;
1513 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
1514 count
+= ilo
->view
[shader_type
].count
;
1515 count
+= ilo
->cbuf
[shader_type
].count
;
1519 size
+= gen6
->estimate_state_size(p
->dev
,
1520 ILO_GPE_GEN6_SURFACE_STATE
, count
);
1523 /* samplers (vs, fs) */
1524 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
1525 count
= ilo
->sampler
[shader_type
].count
;
1527 size
+= gen6
->estimate_state_size(p
->dev
,
1528 ILO_GPE_GEN6_SAMPLER_BORDER_COLOR_STATE
, count
);
1529 size
+= gen6
->estimate_state_size(p
->dev
,
1530 ILO_GPE_GEN6_SAMPLER_STATE
, count
);
1535 if (ilo
->vs
&& ilo
->vs
->shader
->pcb
.clip_state_size
) {
1536 const int pcb_size
= ilo
->vs
->shader
->pcb
.clip_state_size
;
1538 size
+= gen6
->estimate_state_size(p
->dev
,
1539 ILO_GPE_GEN6_PUSH_CONSTANT_BUFFER
, pcb_size
);
1546 ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline
*p
,
1547 enum ilo_3d_pipeline_action action
,
1550 const struct ilo_gpe_gen6
*gen6
= ilo_gpe_gen6_get();
1554 case ILO_3D_PIPELINE_DRAW
:
1556 const struct ilo_context
*ilo
= arg
;
1558 size
= gen6_pipeline_estimate_commands(p
, gen6
, ilo
) +
1559 gen6_pipeline_estimate_states(p
, gen6
, ilo
);
1562 case ILO_3D_PIPELINE_FLUSH
:
1563 size
= gen6
->estimate_command_size(p
->dev
,
1564 ILO_GPE_GEN6_PIPE_CONTROL
, 1) * 3;
1566 case ILO_3D_PIPELINE_WRITE_TIMESTAMP
:
1567 size
= gen6
->estimate_command_size(p
->dev
,
1568 ILO_GPE_GEN6_PIPE_CONTROL
, 1) * 2;
1570 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT
:
1571 size
= gen6
->estimate_command_size(p
->dev
,
1572 ILO_GPE_GEN6_PIPE_CONTROL
, 1) * 3;
1575 assert(!"unknown 3D pipeline action");
1584 ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline
*p
)
1586 const struct ilo_gpe_gen6
*gen6
= ilo_gpe_gen6_get();
1588 p
->estimate_size
= ilo_3d_pipeline_estimate_size_gen6
;
1589 p
->emit_draw
= ilo_3d_pipeline_emit_draw_gen6
;
1590 p
->emit_flush
= ilo_3d_pipeline_emit_flush_gen6
;
1591 p
->emit_write_timestamp
= ilo_3d_pipeline_emit_write_timestamp_gen6
;
1592 p
->emit_write_depth_count
= ilo_3d_pipeline_emit_write_depth_count_gen6
;
1594 #define GEN6_USE(p, name, from) \
1595 p->gen6_ ## name = from->emit_ ## name
1596 GEN6_USE(p
, STATE_BASE_ADDRESS
, gen6
);
1597 GEN6_USE(p
, STATE_SIP
, gen6
);
1598 GEN6_USE(p
, PIPELINE_SELECT
, gen6
);
1599 GEN6_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS
, gen6
);
1600 GEN6_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS
, gen6
);
1601 GEN6_USE(p
, 3DSTATE_URB
, gen6
);
1602 GEN6_USE(p
, 3DSTATE_VERTEX_BUFFERS
, gen6
);
1603 GEN6_USE(p
, 3DSTATE_VERTEX_ELEMENTS
, gen6
);
1604 GEN6_USE(p
, 3DSTATE_INDEX_BUFFER
, gen6
);
1605 GEN6_USE(p
, 3DSTATE_VF_STATISTICS
, gen6
);
1606 GEN6_USE(p
, 3DSTATE_VIEWPORT_STATE_POINTERS
, gen6
);
1607 GEN6_USE(p
, 3DSTATE_CC_STATE_POINTERS
, gen6
);
1608 GEN6_USE(p
, 3DSTATE_SCISSOR_STATE_POINTERS
, gen6
);
1609 GEN6_USE(p
, 3DSTATE_VS
, gen6
);
1610 GEN6_USE(p
, 3DSTATE_GS
, gen6
);
1611 GEN6_USE(p
, 3DSTATE_CLIP
, gen6
);
1612 GEN6_USE(p
, 3DSTATE_SF
, gen6
);
1613 GEN6_USE(p
, 3DSTATE_WM
, gen6
);
1614 GEN6_USE(p
, 3DSTATE_CONSTANT_VS
, gen6
);
1615 GEN6_USE(p
, 3DSTATE_CONSTANT_GS
, gen6
);
1616 GEN6_USE(p
, 3DSTATE_CONSTANT_PS
, gen6
);
1617 GEN6_USE(p
, 3DSTATE_SAMPLE_MASK
, gen6
);
1618 GEN6_USE(p
, 3DSTATE_DRAWING_RECTANGLE
, gen6
);
1619 GEN6_USE(p
, 3DSTATE_DEPTH_BUFFER
, gen6
);
1620 GEN6_USE(p
, 3DSTATE_POLY_STIPPLE_OFFSET
, gen6
);
1621 GEN6_USE(p
, 3DSTATE_POLY_STIPPLE_PATTERN
, gen6
);
1622 GEN6_USE(p
, 3DSTATE_LINE_STIPPLE
, gen6
);
1623 GEN6_USE(p
, 3DSTATE_AA_LINE_PARAMETERS
, gen6
);
1624 GEN6_USE(p
, 3DSTATE_GS_SVB_INDEX
, gen6
);
1625 GEN6_USE(p
, 3DSTATE_MULTISAMPLE
, gen6
);
1626 GEN6_USE(p
, 3DSTATE_STENCIL_BUFFER
, gen6
);
1627 GEN6_USE(p
, 3DSTATE_HIER_DEPTH_BUFFER
, gen6
);
1628 GEN6_USE(p
, 3DSTATE_CLEAR_PARAMS
, gen6
);
1629 GEN6_USE(p
, PIPE_CONTROL
, gen6
);
1630 GEN6_USE(p
, 3DPRIMITIVE
, gen6
);
1631 GEN6_USE(p
, INTERFACE_DESCRIPTOR_DATA
, gen6
);
1632 GEN6_USE(p
, SF_VIEWPORT
, gen6
);
1633 GEN6_USE(p
, CLIP_VIEWPORT
, gen6
);
1634 GEN6_USE(p
, CC_VIEWPORT
, gen6
);
1635 GEN6_USE(p
, COLOR_CALC_STATE
, gen6
);
1636 GEN6_USE(p
, BLEND_STATE
, gen6
);
1637 GEN6_USE(p
, DEPTH_STENCIL_STATE
, gen6
);
1638 GEN6_USE(p
, SCISSOR_RECT
, gen6
);
1639 GEN6_USE(p
, BINDING_TABLE_STATE
, gen6
);
1640 GEN6_USE(p
, surf_SURFACE_STATE
, gen6
);
1641 GEN6_USE(p
, view_SURFACE_STATE
, gen6
);
1642 GEN6_USE(p
, cbuf_SURFACE_STATE
, gen6
);
1643 GEN6_USE(p
, so_SURFACE_STATE
, gen6
);
1644 GEN6_USE(p
, SAMPLER_STATE
, gen6
);
1645 GEN6_USE(p
, SAMPLER_BORDER_COLOR_STATE
, gen6
);
1646 GEN6_USE(p
, push_constant_buffer
, gen6
);