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[mesa.git] / src / gallium / drivers / ilo / ilo_3d_pipeline_gen7.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "util/u_dual_blend.h"
29 #include "intel_reg.h"
30
31 #include "ilo_common.h"
32 #include "ilo_context.h"
33 #include "ilo_cp.h"
34 #include "ilo_gpe_gen7.h"
35 #include "ilo_shader.h"
36 #include "ilo_state.h"
37 #include "ilo_3d_pipeline.h"
38 #include "ilo_3d_pipeline_gen6.h"
39 #include "ilo_3d_pipeline_gen7.h"
40
41 static void
42 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
43 bool change_multisample_state,
44 bool change_depth_state)
45 {
46 struct intel_bo *bo = NULL;
47 uint32_t dw1 = PIPE_CONTROL_CS_STALL;
48
49 assert(p->dev->gen == ILO_GEN(7));
50
51 /* emit once */
52 if (p->state.has_gen6_wa_pipe_control)
53 return;
54 p->state.has_gen6_wa_pipe_control = true;
55
56 /*
57 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
58 *
59 * "Due to an HW issue driver needs to send a pipe control with stall
60 * when ever there is state change in depth bias related state"
61 *
62 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
63 *
64 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
65 * in the ring after this instruction
66 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
67 *
68 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
69 *
70 * "Driver must ierarchi that all the caches in the depth pipe are
71 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
72 * requires driver to send a PIPE_CONTROL with a CS stall along with a
73 * Depth Flush prior to this command.
74 *
75 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
76 *
77 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
78 * a post sync operation prior to the group of depth
79 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
80 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
81 */
82
83 if (change_multisample_state)
84 dw1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
85
86 if (change_depth_state) {
87 dw1 |= PIPE_CONTROL_WRITE_IMMEDIATE;
88 bo = p->workaround_bo;
89 }
90
91 gen6_emit_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
92 }
93
94 static void
95 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
96 {
97 assert(p->dev->gen == ILO_GEN(7));
98
99 /*
100 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
101 *
102 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
103 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
104 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
105 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
106 * needs to be sent before any combination of VS associated 3DSTATE."
107 */
108 gen6_emit_PIPE_CONTROL(p->dev,
109 PIPE_CONTROL_DEPTH_STALL |
110 PIPE_CONTROL_WRITE_IMMEDIATE,
111 p->workaround_bo, 0, false, p->cp);
112 }
113
114 static void
115 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
116 bool change_depth_buffer)
117 {
118 assert(p->dev->gen == ILO_GEN(7));
119
120 /*
121 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
122 *
123 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
124 * Enable bit set after all the following states are programmed:
125 *
126 * * 3DSTATE_PS
127 * * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
128 * * 3DSTATE_CONSTANT_PS
129 * * 3DSTATE_BINDING_TABLE_POINTERS_PS
130 * * 3DSTATE_SAMPLER_STATE_POINTERS_PS
131 * * 3DSTATE_CC_STATE_POINTERS
132 * * 3DSTATE_BLEND_STATE_POINTERS
133 * * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
134 *
135 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
136 *
137 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
138 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
139 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
140 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
141 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
142 * Depth Flush Bit set, followed by another pipelined depth stall
143 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
144 * guarantee that the pipeline from WM onwards is already flushed
145 * (e.g., via a preceding MI_FLUSH)."
146 */
147 gen6_emit_PIPE_CONTROL(p->dev,
148 PIPE_CONTROL_DEPTH_STALL,
149 NULL, 0, false, p->cp);
150
151 if (!change_depth_buffer)
152 return;
153
154 gen6_emit_PIPE_CONTROL(p->dev,
155 PIPE_CONTROL_DEPTH_CACHE_FLUSH,
156 NULL, 0, false, p->cp);
157
158 gen6_emit_PIPE_CONTROL(p->dev,
159 PIPE_CONTROL_DEPTH_STALL,
160 NULL, 0, false, p->cp);
161 }
162
163 static void
164 gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
165 {
166 assert(p->dev->gen == ILO_GEN(7));
167
168 /*
169 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
170 *
171 * "If this field (Maximum Number of Threads in 3DSTATE_WM) is changed
172 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
173 * Pixel Scoreboard set is required to be issued."
174 */
175 gen6_emit_PIPE_CONTROL(p->dev,
176 PIPE_CONTROL_STALL_AT_SCOREBOARD,
177 NULL, 0, false, p->cp);
178
179 }
180
181 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
182
183 static void
184 gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
185 const struct ilo_context *ilo,
186 struct gen6_pipeline_session *session)
187 {
188 /* 3DSTATE_URB_{VS,GS,HS,DS} */
189 if (DIRTY(VE) || DIRTY(VS)) {
190 /* the first 16KB are reserved for VS and PS PCBs */
191 const int offset = 16 * 1024;
192 int vs_entry_size, vs_total_size;
193
194 vs_entry_size = (ilo->vs) ?
195 ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
196
197 /*
198 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
199 *
200 * "Programming Restriction: As the VS URB entry serves as both the
201 * per-vertex input and output of the VS shader, the VS URB
202 * Allocation Size must be sized to the maximum of the vertex input
203 * and output structures."
204 */
205 if (vs_entry_size < ilo->ve->count)
206 vs_entry_size = ilo->ve->count;
207
208 vs_entry_size *= sizeof(float) * 4;
209 vs_total_size = ilo->dev->urb_size - offset;
210
211 gen7_wa_pipe_control_vs_depth_stall(p);
212
213 gen7_emit_3DSTATE_URB_VS(p->dev,
214 offset, vs_total_size, vs_entry_size, p->cp);
215
216 gen7_emit_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
217 gen7_emit_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
218 gen7_emit_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
219 }
220 }
221
222 static void
223 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
224 const struct ilo_context *ilo,
225 struct gen6_pipeline_session *session)
226 {
227 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
228 if (session->hw_ctx_changed) {
229 /*
230 * push constant buffers are only allowed to take up at most the first
231 * 16KB of the URB
232 */
233 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev,
234 0, 8192, p->cp);
235
236 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev,
237 8192, 8192, p->cp);
238
239 gen7_wa_pipe_control_cs_stall(p, true, true);
240 }
241 }
242
243 static void
244 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
245 const struct ilo_context *ilo,
246 struct gen6_pipeline_session *session)
247 {
248 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
249 if (session->viewport_state_changed) {
250 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
251 p->state.CC_VIEWPORT, p->cp);
252
253 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
254 p->state.SF_CLIP_VIEWPORT, p->cp);
255 }
256 }
257
258 static void
259 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
260 const struct ilo_context *ilo,
261 struct gen6_pipeline_session *session)
262 {
263 /* 3DSTATE_BLEND_STATE_POINTERS */
264 if (session->cc_state_blend_changed) {
265 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(p->dev,
266 p->state.BLEND_STATE, p->cp);
267 }
268
269 /* 3DSTATE_CC_STATE_POINTERS */
270 if (session->cc_state_cc_changed) {
271 gen7_emit_3DSTATE_CC_STATE_POINTERS(p->dev,
272 p->state.COLOR_CALC_STATE, p->cp);
273 }
274
275 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
276 if (session->cc_state_dsa_changed) {
277 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
278 p->state.DEPTH_STENCIL_STATE, p->cp);
279 }
280 }
281
282 static void
283 gen7_pipeline_vs(struct ilo_3d_pipeline *p,
284 const struct ilo_context *ilo,
285 struct gen6_pipeline_session *session)
286 {
287 const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
288 const bool emit_3dstate_sampler_state = session->sampler_state_vs_changed;
289 /* see gen6_pipeline_vs() */
290 const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
291 const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
292 session->kernel_bo_changed);
293
294 /* emit depth stall before any of the VS commands */
295 if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
296 emit_3dstate_constant_vs || emit_3dstate_vs)
297 gen7_wa_pipe_control_vs_depth_stall(p);
298
299 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
300 if (emit_3dstate_binding_table) {
301 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
302 p->state.vs.BINDING_TABLE_STATE, p->cp);
303 }
304
305 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
306 if (emit_3dstate_sampler_state) {
307 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
308 p->state.vs.SAMPLER_STATE, p->cp);
309 }
310
311 /* 3DSTATE_CONSTANT_VS */
312 if (emit_3dstate_constant_vs) {
313 gen7_emit_3DSTATE_CONSTANT_VS(p->dev,
314 &p->state.vs.PUSH_CONSTANT_BUFFER,
315 &p->state.vs.PUSH_CONSTANT_BUFFER_size,
316 1, p->cp);
317 }
318
319 /* 3DSTATE_VS */
320 if (emit_3dstate_vs) {
321 const int num_samplers = ilo->sampler[PIPE_SHADER_VERTEX].count;
322
323 gen6_emit_3DSTATE_VS(p->dev, ilo->vs, num_samplers, p->cp);
324 }
325 }
326
327 static void
328 gen7_pipeline_hs(struct ilo_3d_pipeline *p,
329 const struct ilo_context *ilo,
330 struct gen6_pipeline_session *session)
331 {
332 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
333 if (session->hw_ctx_changed) {
334 gen7_emit_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
335 gen7_emit_3DSTATE_HS(p->dev, NULL, 0, p->cp);
336 }
337
338 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
339 if (session->hw_ctx_changed)
340 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
341 }
342
343 static void
344 gen7_pipeline_te(struct ilo_3d_pipeline *p,
345 const struct ilo_context *ilo,
346 struct gen6_pipeline_session *session)
347 {
348 /* 3DSTATE_TE */
349 if (session->hw_ctx_changed)
350 gen7_emit_3DSTATE_TE(p->dev, p->cp);
351 }
352
353 static void
354 gen7_pipeline_ds(struct ilo_3d_pipeline *p,
355 const struct ilo_context *ilo,
356 struct gen6_pipeline_session *session)
357 {
358 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
359 if (session->hw_ctx_changed) {
360 gen7_emit_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
361 gen7_emit_3DSTATE_DS(p->dev, NULL, 0, p->cp);
362 }
363
364 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
365 if (session->hw_ctx_changed)
366 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
367
368 }
369
370 static void
371 gen7_pipeline_gs(struct ilo_3d_pipeline *p,
372 const struct ilo_context *ilo,
373 struct gen6_pipeline_session *session)
374 {
375 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
376 if (session->hw_ctx_changed) {
377 gen7_emit_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
378 gen7_emit_3DSTATE_GS(p->dev, NULL, 0, p->cp);
379 }
380
381 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
382 if (session->binding_table_gs_changed) {
383 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
384 p->state.gs.BINDING_TABLE_STATE, p->cp);
385 }
386 }
387
388 static void
389 gen7_pipeline_sol(struct ilo_3d_pipeline *p,
390 const struct ilo_context *ilo,
391 struct gen6_pipeline_session *session)
392 {
393 const struct pipe_stream_output_info *so_info;
394 const struct ilo_shader_state *shader;
395 bool dirty_sh = false;
396
397 if (ilo->gs) {
398 shader = ilo->gs;
399 dirty_sh = DIRTY(GS);
400 }
401 else {
402 shader = ilo->vs;
403 dirty_sh = DIRTY(VS);
404 }
405
406 so_info = ilo_shader_get_kernel_so_info(shader);
407
408 gen6_pipeline_update_max_svbi(p, ilo, session);
409
410 /* 3DSTATE_SO_BUFFER */
411 if ((DIRTY(SO) || dirty_sh || session->batch_bo_changed) &&
412 ilo->so.enabled) {
413 int i;
414
415 for (i = 0; i < ilo->so.count; i++) {
416 const int stride = so_info->stride[i] * 4; /* in bytes */
417 int base = 0;
418
419 /* reset HW write offsets and offset buffer base */
420 if (!p->cp->render_ctx) {
421 ilo_cp_set_one_off_flags(p->cp, INTEL_EXEC_GEN7_SOL_RESET);
422 base += p->state.so_num_vertices * stride;
423 }
424
425 gen7_emit_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
426 ilo->so.states[i], p->cp);
427 }
428
429 for (; i < 4; i++)
430 gen7_emit_3DSTATE_SO_BUFFER(p->dev, i, 0, 0, NULL, p->cp);
431 }
432
433 /* 3DSTATE_SO_DECL_LIST */
434 if (dirty_sh && ilo->so.enabled)
435 gen7_emit_3DSTATE_SO_DECL_LIST(p->dev, so_info, p->cp);
436
437 /* 3DSTATE_STREAMOUT */
438 if (DIRTY(SO) || DIRTY(RASTERIZER) || dirty_sh) {
439 const unsigned buffer_mask = (1 << ilo->so.count) - 1;
440 const int output_count = ilo_shader_get_kernel_param(shader,
441 ILO_KERNEL_OUTPUT_COUNT);
442
443 gen7_emit_3DSTATE_STREAMOUT(p->dev, buffer_mask, output_count,
444 ilo->rasterizer->state.rasterizer_discard, p->cp);
445 }
446 }
447
448 static void
449 gen7_pipeline_sf(struct ilo_3d_pipeline *p,
450 const struct ilo_context *ilo,
451 struct gen6_pipeline_session *session)
452 {
453 /* 3DSTATE_SBE */
454 if (DIRTY(RASTERIZER) || DIRTY(FS))
455 gen7_emit_3DSTATE_SBE(p->dev, ilo->rasterizer, ilo->fs, ilo->cp);
456
457 /* 3DSTATE_SF */
458 if (DIRTY(RASTERIZER) || DIRTY(FB)) {
459 gen7_wa_pipe_control_cs_stall(p, true, true);
460 gen7_emit_3DSTATE_SF(p->dev, ilo->rasterizer, ilo->fb.state.zsbuf, p->cp);
461 }
462 }
463
464 static void
465 gen7_pipeline_wm(struct ilo_3d_pipeline *p,
466 const struct ilo_context *ilo,
467 struct gen6_pipeline_session *session)
468 {
469 /* 3DSTATE_WM */
470 if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DSA) || DIRTY(RASTERIZER)) {
471 const bool cc_may_kill = (ilo->dsa->dw_alpha ||
472 ilo->blend->alpha_to_coverage);
473
474 if (p->dev->gen == ILO_GEN(7) && session->hw_ctx_changed)
475 gen7_wa_pipe_control_wm_max_threads_stall(p);
476
477 gen7_emit_3DSTATE_WM(p->dev, ilo->fs,
478 ilo->rasterizer, cc_may_kill, p->cp);
479 }
480
481 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
482 if (session->binding_table_fs_changed) {
483 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
484 p->state.wm.BINDING_TABLE_STATE, p->cp);
485 }
486
487 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
488 if (session->sampler_state_fs_changed) {
489 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
490 p->state.wm.SAMPLER_STATE, p->cp);
491 }
492
493 /* 3DSTATE_CONSTANT_PS */
494 if (session->pcb_state_fs_changed) {
495 gen7_emit_3DSTATE_CONSTANT_PS(p->dev,
496 &p->state.wm.PUSH_CONSTANT_BUFFER,
497 &p->state.wm.PUSH_CONSTANT_BUFFER_size,
498 1, p->cp);
499 }
500
501 /* 3DSTATE_PS */
502 if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) ||
503 session->kernel_bo_changed) {
504 const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
505 const bool dual_blend = ilo->blend->dual_blend;
506
507 gen7_emit_3DSTATE_PS(p->dev, ilo->fs, num_samplers, dual_blend, p->cp);
508 }
509
510 /* 3DSTATE_SCISSOR_STATE_POINTERS */
511 if (session->scissor_state_changed) {
512 gen6_emit_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
513 p->state.SCISSOR_RECT, p->cp);
514 }
515
516 /* XXX what is the best way to know if this workaround is needed? */
517 {
518 const bool emit_3dstate_ps =
519 (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND));
520 const bool emit_3dstate_depth_buffer =
521 (DIRTY(FB) || DIRTY(DSA) || session->state_bo_changed);
522
523 if (emit_3dstate_ps ||
524 emit_3dstate_depth_buffer ||
525 session->pcb_state_fs_changed ||
526 session->viewport_state_changed ||
527 session->binding_table_fs_changed ||
528 session->sampler_state_fs_changed ||
529 session->cc_state_cc_changed ||
530 session->cc_state_blend_changed ||
531 session->cc_state_dsa_changed)
532 gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
533 }
534
535 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
536 if (DIRTY(FB) || session->batch_bo_changed) {
537 const struct ilo_zs_surface *zs;
538
539 if (ilo->fb.state.zsbuf) {
540 const struct ilo_surface_cso *surface =
541 (const struct ilo_surface_cso *) ilo->fb.state.zsbuf;
542
543 assert(!surface->is_rt);
544 zs = &surface->u.zs;
545 }
546 else {
547 zs = &ilo->fb.null_zs;
548 }
549
550 gen6_emit_3DSTATE_DEPTH_BUFFER(p->dev, zs, p->cp);
551 gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p->dev, zs, p->cp);
552 gen6_emit_3DSTATE_STENCIL_BUFFER(p->dev, zs, p->cp);
553
554 /* TODO */
555 gen7_emit_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
556 }
557 }
558
559 static void
560 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
561 const struct ilo_context *ilo,
562 struct gen6_pipeline_session *session)
563 {
564 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
565 if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
566 const uint32_t *packed_sample_pos;
567
568 gen7_wa_pipe_control_cs_stall(p, true, true);
569
570 packed_sample_pos =
571 (ilo->fb.num_samples > 4) ? p->packed_sample_position_8x :
572 (ilo->fb.num_samples > 1) ? &p->packed_sample_position_4x :
573 &p->packed_sample_position_1x;
574
575 gen6_emit_3DSTATE_MULTISAMPLE(p->dev,
576 ilo->fb.num_samples, packed_sample_pos,
577 ilo->rasterizer->state.half_pixel_center, p->cp);
578
579 gen7_emit_3DSTATE_SAMPLE_MASK(p->dev,
580 (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1,
581 ilo->fb.num_samples, p->cp);
582 }
583 }
584
585 static void
586 gen7_pipeline_vf_draw(struct ilo_3d_pipeline *p,
587 const struct ilo_context *ilo,
588 struct gen6_pipeline_session *session)
589 {
590 /* 3DPRIMITIVE */
591 gen7_emit_3DPRIMITIVE(p->dev, ilo->draw, &ilo->ib, false, p->cp);
592 p->state.has_gen6_wa_pipe_control = false;
593 }
594
595 static void
596 gen7_pipeline_commands(struct ilo_3d_pipeline *p,
597 const struct ilo_context *ilo,
598 struct gen6_pipeline_session *session)
599 {
600 /*
601 * We try to keep the order of the commands match, as closely as possible,
602 * that of the classic i965 driver. It allows us to compare the command
603 * streams easily.
604 */
605 gen6_pipeline_common_select(p, ilo, session);
606 gen6_pipeline_common_sip(p, ilo, session);
607 gen6_pipeline_vf_statistics(p, ilo, session);
608 gen7_pipeline_common_pcb_alloc(p, ilo, session);
609 gen6_pipeline_common_base_address(p, ilo, session);
610 gen7_pipeline_common_pointers_1(p, ilo, session);
611 gen7_pipeline_common_urb(p, ilo, session);
612 gen7_pipeline_common_pointers_2(p, ilo, session);
613 gen7_pipeline_wm_multisample(p, ilo, session);
614 gen7_pipeline_gs(p, ilo, session);
615 gen7_pipeline_hs(p, ilo, session);
616 gen7_pipeline_te(p, ilo, session);
617 gen7_pipeline_ds(p, ilo, session);
618 gen7_pipeline_vs(p, ilo, session);
619 gen7_pipeline_sol(p, ilo, session);
620 gen6_pipeline_clip(p, ilo, session);
621 gen7_pipeline_sf(p, ilo, session);
622 gen7_pipeline_wm(p, ilo, session);
623 gen6_pipeline_wm_raster(p, ilo, session);
624 gen6_pipeline_sf_rect(p, ilo, session);
625 gen6_pipeline_vf(p, ilo, session);
626 gen7_pipeline_vf_draw(p, ilo, session);
627 }
628
629 static void
630 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline *p,
631 const struct ilo_context *ilo)
632 {
633 struct gen6_pipeline_session session;
634
635 gen6_pipeline_prepare(p, ilo, &session);
636
637 session.emit_draw_states = gen6_pipeline_states;
638 session.emit_draw_commands = gen7_pipeline_commands;
639
640 gen6_pipeline_draw(p, ilo, &session);
641 gen6_pipeline_end(p, ilo, &session);
642 }
643
644 static int
645 gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
646 const struct ilo_context *ilo)
647 {
648 static int size;
649 enum ilo_gpe_gen7_command cmd;
650
651 if (size)
652 return size;
653
654 for (cmd = 0; cmd < ILO_GPE_GEN7_COMMAND_COUNT; cmd++) {
655 int count;
656
657 switch (cmd) {
658 case ILO_GPE_GEN7_PIPE_CONTROL:
659 /* for the workaround */
660 count = 2;
661 /* another one after 3DSTATE_URB */
662 count += 1;
663 /* and another one after 3DSTATE_CONSTANT_VS */
664 count += 1;
665 break;
666 case ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS:
667 count = 33;
668 break;
669 case ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS:
670 count = 34;
671 break;
672 case ILO_GPE_GEN7_MEDIA_VFE_STATE:
673 case ILO_GPE_GEN7_MEDIA_CURBE_LOAD:
674 case ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD:
675 case ILO_GPE_GEN7_MEDIA_STATE_FLUSH:
676 case ILO_GPE_GEN7_GPGPU_WALKER:
677 /* media commands */
678 count = 0;
679 break;
680 default:
681 count = 1;
682 break;
683 }
684
685 if (count) {
686 size += ilo_gpe_gen7_estimate_command_size(p->dev,
687 cmd, count);
688 }
689 }
690
691 return size;
692 }
693
694 static int
695 gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
696 const struct ilo_context *ilo)
697 {
698 static int static_size;
699 int shader_type, count, size;
700
701 if (!static_size) {
702 struct {
703 enum ilo_gpe_gen7_state state;
704 int count;
705 } static_states[] = {
706 /* viewports */
707 { ILO_GPE_GEN7_SF_CLIP_VIEWPORT, 1 },
708 { ILO_GPE_GEN7_CC_VIEWPORT, 1 },
709 /* cc */
710 { ILO_GPE_GEN7_COLOR_CALC_STATE, 1 },
711 { ILO_GPE_GEN7_BLEND_STATE, ILO_MAX_DRAW_BUFFERS },
712 { ILO_GPE_GEN7_DEPTH_STENCIL_STATE, 1 },
713 /* scissors */
714 { ILO_GPE_GEN7_SCISSOR_RECT, 1 },
715 /* binding table (vs, gs, fs) */
716 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_VS_SURFACES },
717 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_GS_SURFACES },
718 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_WM_SURFACES },
719 };
720 int i;
721
722 for (i = 0; i < Elements(static_states); i++) {
723 static_size += ilo_gpe_gen7_estimate_state_size(p->dev,
724 static_states[i].state,
725 static_states[i].count);
726 }
727 }
728
729 size = static_size;
730
731 /*
732 * render targets (fs)
733 * sampler views (vs, fs)
734 * constant buffers (vs, fs)
735 */
736 count = ilo->fb.state.nr_cbufs;
737 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
738 count += ilo->view[shader_type].count;
739 count += util_bitcount(ilo->cbuf[shader_type].enabled_mask);
740 }
741
742 if (count) {
743 size += ilo_gpe_gen7_estimate_state_size(p->dev,
744 ILO_GPE_GEN7_SURFACE_STATE, count);
745 }
746
747 /* samplers (vs, fs) */
748 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
749 count = ilo->sampler[shader_type].count;
750 if (count) {
751 size += ilo_gpe_gen7_estimate_state_size(p->dev,
752 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE, count);
753 size += ilo_gpe_gen7_estimate_state_size(p->dev,
754 ILO_GPE_GEN7_SAMPLER_STATE, count);
755 }
756 }
757
758 /* pcb (vs) */
759 if (ilo->vs) {
760 const int cbuf0_size =
761 ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_PCB_CBUF0_SIZE);
762 const int ucp_size =
763 ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_PCB_UCP_SIZE);
764
765 size += ilo_gpe_gen7_estimate_state_size(p->dev,
766 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, cbuf0_size + ucp_size);
767 }
768
769 /* pcb (fs) */
770 if (ilo->fs) {
771 const int cbuf0_size =
772 ilo_shader_get_kernel_param(ilo->fs, ILO_KERNEL_PCB_CBUF0_SIZE);
773
774 size += ilo_gpe_gen7_estimate_state_size(p->dev,
775 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, cbuf0_size);
776 }
777
778 return size;
779 }
780
781 static int
782 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p,
783 enum ilo_3d_pipeline_action action,
784 const void *arg)
785 {
786 int size;
787
788 switch (action) {
789 case ILO_3D_PIPELINE_DRAW:
790 {
791 const struct ilo_context *ilo = arg;
792
793 size = gen7_pipeline_estimate_commands(p, ilo) +
794 gen7_pipeline_estimate_states(p, ilo);
795 }
796 break;
797 case ILO_3D_PIPELINE_FLUSH:
798 case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
799 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
800 size = ilo_gpe_gen7_estimate_command_size(p->dev,
801 ILO_GPE_GEN7_PIPE_CONTROL, 1);
802 break;
803 default:
804 assert(!"unknown 3D pipeline action");
805 size = 0;
806 break;
807 }
808
809 return size;
810 }
811
812 void
813 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
814 {
815 p->estimate_size = ilo_3d_pipeline_estimate_size_gen7;
816 p->emit_draw = ilo_3d_pipeline_emit_draw_gen7;
817 p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
818 p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
819 p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
820 }