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[mesa.git] / src / gallium / drivers / ilo / ilo_3d_pipeline_gen7.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "util/u_dual_blend.h"
29 #include "intel_reg.h"
30
31 #include "ilo_common.h"
32 #include "ilo_context.h"
33 #include "ilo_cp.h"
34 #include "ilo_gpe_gen7.h"
35 #include "ilo_shader.h"
36 #include "ilo_state.h"
37 #include "ilo_3d_pipeline.h"
38 #include "ilo_3d_pipeline_gen6.h"
39 #include "ilo_3d_pipeline_gen7.h"
40
41 static void
42 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
43 bool change_multisample_state,
44 bool change_depth_state)
45 {
46 struct intel_bo *bo = NULL;
47 uint32_t dw1 = PIPE_CONTROL_CS_STALL;
48
49 assert(p->dev->gen == ILO_GEN(7));
50
51 /* emit once */
52 if (p->state.has_gen6_wa_pipe_control)
53 return;
54 p->state.has_gen6_wa_pipe_control = true;
55
56 /*
57 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
58 *
59 * "Due to an HW issue driver needs to send a pipe control with stall
60 * when ever there is state change in depth bias related state"
61 *
62 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
63 *
64 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
65 * in the ring after this instruction
66 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
67 *
68 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
69 *
70 * "Driver must ierarchi that all the caches in the depth pipe are
71 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
72 * requires driver to send a PIPE_CONTROL with a CS stall along with a
73 * Depth Flush prior to this command.
74 *
75 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
76 *
77 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
78 * a post sync operation prior to the group of depth
79 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
80 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
81 */
82
83 if (change_multisample_state)
84 dw1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
85
86 if (change_depth_state) {
87 dw1 |= PIPE_CONTROL_WRITE_IMMEDIATE;
88 bo = p->workaround_bo;
89 }
90
91 p->gen6_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
92 }
93
94 static void
95 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
96 {
97 assert(p->dev->gen == ILO_GEN(7));
98
99 /*
100 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
101 *
102 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
103 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
104 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
105 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
106 * needs to be sent before any combination of VS associated 3DSTATE."
107 */
108 p->gen6_PIPE_CONTROL(p->dev,
109 PIPE_CONTROL_DEPTH_STALL |
110 PIPE_CONTROL_WRITE_IMMEDIATE,
111 p->workaround_bo, 0, false, p->cp);
112 }
113
114 static void
115 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
116 bool change_depth_buffer)
117 {
118 assert(p->dev->gen == ILO_GEN(7));
119
120 /*
121 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
122 *
123 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
124 * Enable bit set after all the following states are programmed:
125 *
126 * * 3DSTATE_PS
127 * * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
128 * * 3DSTATE_CONSTANT_PS
129 * * 3DSTATE_BINDING_TABLE_POINTERS_PS
130 * * 3DSTATE_SAMPLER_STATE_POINTERS_PS
131 * * 3DSTATE_CC_STATE_POINTERS
132 * * 3DSTATE_BLEND_STATE_POINTERS
133 * * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
134 *
135 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
136 *
137 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
138 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
139 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
140 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
141 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
142 * Depth Flush Bit set, followed by another pipelined depth stall
143 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
144 * guarantee that the pipeline from WM onwards is already flushed
145 * (e.g., via a preceding MI_FLUSH)."
146 */
147 p->gen6_PIPE_CONTROL(p->dev,
148 PIPE_CONTROL_DEPTH_STALL,
149 NULL, 0, false, p->cp);
150
151 if (!change_depth_buffer)
152 return;
153
154 p->gen6_PIPE_CONTROL(p->dev,
155 PIPE_CONTROL_DEPTH_CACHE_FLUSH,
156 NULL, 0, false, p->cp);
157
158 p->gen6_PIPE_CONTROL(p->dev,
159 PIPE_CONTROL_DEPTH_STALL,
160 NULL, 0, false, p->cp);
161 }
162
163 static void
164 gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
165 {
166 assert(p->dev->gen == ILO_GEN(7));
167
168 /*
169 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
170 *
171 * "If this field (Maximum Number of Threads in 3DSTATE_WM) is changed
172 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
173 * Pixel Scoreboard set is required to be issued."
174 */
175 p->gen6_PIPE_CONTROL(p->dev,
176 PIPE_CONTROL_STALL_AT_SCOREBOARD,
177 NULL, 0, false, p->cp);
178
179 }
180
181 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
182
183 static void
184 gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
185 const struct ilo_context *ilo,
186 struct gen6_pipeline_session *session)
187 {
188 /* 3DSTATE_URB_{VS,GS,HS,DS} */
189 if (DIRTY(VERTEX_ELEMENTS) || DIRTY(VS)) {
190 const struct ilo_shader *vs = (ilo->vs) ? ilo->vs->shader : NULL;
191 /* the first 16KB are reserved for VS and PS PCBs */
192 const int offset = 16 * 1024;
193 int vs_entry_size, vs_total_size;
194
195 vs_entry_size = (vs) ? vs->out.count : 0;
196
197 /*
198 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
199 *
200 * "Programming Restriction: As the VS URB entry serves as both the
201 * per-vertex input and output of the VS shader, the VS URB
202 * Allocation Size must be sized to the maximum of the vertex input
203 * and output structures."
204 */
205 if (vs_entry_size < ilo->ve->count)
206 vs_entry_size = ilo->ve->count;
207
208 vs_entry_size *= sizeof(float) * 4;
209 vs_total_size = ilo->dev->urb_size - offset;
210
211 gen7_wa_pipe_control_vs_depth_stall(p);
212
213 p->gen7_3DSTATE_URB_VS(p->dev,
214 offset, vs_total_size, vs_entry_size, p->cp);
215
216 p->gen7_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
217 p->gen7_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
218 p->gen7_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
219 }
220 }
221
222 static void
223 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
224 const struct ilo_context *ilo,
225 struct gen6_pipeline_session *session)
226 {
227 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
228 if (session->hw_ctx_changed) {
229 /*
230 * push constant buffers are only allowed to take up at most the first
231 * 16KB of the URB
232 */
233 p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev,
234 0, 8192, p->cp);
235
236 p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev,
237 8192, 8192, p->cp);
238
239 gen7_wa_pipe_control_cs_stall(p, true, true);
240 }
241 }
242
243 static void
244 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
245 const struct ilo_context *ilo,
246 struct gen6_pipeline_session *session)
247 {
248 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
249 if (session->viewport_state_changed) {
250 p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
251 p->state.CC_VIEWPORT, p->cp);
252
253 p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
254 p->state.SF_CLIP_VIEWPORT, p->cp);
255 }
256 }
257
258 static void
259 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
260 const struct ilo_context *ilo,
261 struct gen6_pipeline_session *session)
262 {
263 /* 3DSTATE_BLEND_STATE_POINTERS */
264 if (session->cc_state_blend_changed) {
265 p->gen7_3DSTATE_BLEND_STATE_POINTERS(p->dev,
266 p->state.BLEND_STATE, p->cp);
267 }
268
269 /* 3DSTATE_CC_STATE_POINTERS */
270 if (session->cc_state_cc_changed) {
271 p->gen7_3DSTATE_CC_STATE_POINTERS(p->dev,
272 p->state.COLOR_CALC_STATE, p->cp);
273 }
274
275 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
276 if (session->cc_state_dsa_changed) {
277 p->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
278 p->state.DEPTH_STENCIL_STATE, p->cp);
279 }
280 }
281
282 static void
283 gen7_pipeline_vs(struct ilo_3d_pipeline *p,
284 const struct ilo_context *ilo,
285 struct gen6_pipeline_session *session)
286 {
287 const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
288 const bool emit_3dstate_sampler_state = session->sampler_state_vs_changed;
289 /* see gen6_pipeline_vs() */
290 const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
291 const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(VERTEX_SAMPLERS));
292
293 /* emit depth stall before any of the VS commands */
294 if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
295 emit_3dstate_constant_vs || emit_3dstate_vs)
296 gen7_wa_pipe_control_vs_depth_stall(p);
297
298 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
299 if (emit_3dstate_binding_table) {
300 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
301 p->state.vs.BINDING_TABLE_STATE, p->cp);
302 }
303
304 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
305 if (emit_3dstate_sampler_state) {
306 p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
307 p->state.vs.SAMPLER_STATE, p->cp);
308 }
309
310 gen6_pipeline_vs(p, ilo, session);
311 }
312
313 static void
314 gen7_pipeline_hs(struct ilo_3d_pipeline *p,
315 const struct ilo_context *ilo,
316 struct gen6_pipeline_session *session)
317 {
318 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
319 if (session->hw_ctx_changed) {
320 p->gen7_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
321 p->gen7_3DSTATE_HS(p->dev, NULL, 0, 0, p->cp);
322 }
323
324 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
325 if (session->hw_ctx_changed)
326 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
327 }
328
329 static void
330 gen7_pipeline_te(struct ilo_3d_pipeline *p,
331 const struct ilo_context *ilo,
332 struct gen6_pipeline_session *session)
333 {
334 /* 3DSTATE_TE */
335 if (session->hw_ctx_changed)
336 p->gen7_3DSTATE_TE(p->dev, p->cp);
337 }
338
339 static void
340 gen7_pipeline_ds(struct ilo_3d_pipeline *p,
341 const struct ilo_context *ilo,
342 struct gen6_pipeline_session *session)
343 {
344 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
345 if (session->hw_ctx_changed) {
346 p->gen7_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
347 p->gen7_3DSTATE_DS(p->dev, NULL, 0, 0, p->cp);
348 }
349
350 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
351 if (session->hw_ctx_changed)
352 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
353
354 }
355
356 static void
357 gen7_pipeline_gs(struct ilo_3d_pipeline *p,
358 const struct ilo_context *ilo,
359 struct gen6_pipeline_session *session)
360 {
361 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
362 if (session->hw_ctx_changed) {
363 p->gen6_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
364 p->gen7_3DSTATE_GS(p->dev, NULL, 0, p->cp);
365 }
366
367 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
368 if (session->binding_table_gs_changed) {
369 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
370 p->state.gs.BINDING_TABLE_STATE, p->cp);
371 }
372 }
373
374 static void
375 gen7_pipeline_sol(struct ilo_3d_pipeline *p,
376 const struct ilo_context *ilo,
377 struct gen6_pipeline_session *session)
378 {
379 const struct pipe_stream_output_info *so_info;
380 const struct ilo_shader *sh;
381 bool dirty_sh = false;
382
383 if (ilo->gs) {
384 so_info = &ilo->gs->info.stream_output;
385 sh = ilo->gs->shader;
386 dirty_sh = DIRTY(GS);
387 }
388 else if (ilo->vs) {
389 so_info = &ilo->vs->info.stream_output;
390 sh = ilo->vs->shader;
391 dirty_sh = DIRTY(VS);
392 }
393
394 gen6_pipeline_update_max_svbi(p, ilo, session);
395
396 /* 3DSTATE_SO_BUFFER */
397 if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) && ilo->so.enabled) {
398 int i;
399
400 for (i = 0; i < ilo->so.count; i++) {
401 const int stride = so_info->stride[i] * 4; /* in bytes */
402 int base = 0;
403
404 /* reset HW write offsets and offset buffer base */
405 if (!p->cp->render_ctx) {
406 ilo_cp_set_one_off_flags(p->cp, INTEL_EXEC_GEN7_SOL_RESET);
407 base += p->state.so_num_vertices * stride;
408 }
409
410 p->gen7_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
411 ilo->so.states[i], p->cp);
412 }
413
414 for (; i < 4; i++)
415 p->gen7_3DSTATE_SO_BUFFER(p->dev, i, 0, 0, NULL, p->cp);
416 }
417
418 /* 3DSTATE_SO_DECL_LIST */
419 if (dirty_sh && ilo->so.enabled)
420 p->gen7_3DSTATE_SO_DECL_LIST(p->dev, so_info, sh, p->cp);
421
422 /* 3DSTATE_STREAMOUT */
423 if (DIRTY(STREAM_OUTPUT_TARGETS) || DIRTY(RASTERIZER) || dirty_sh) {
424 const unsigned buffer_mask = (1 << ilo->so.count) - 1;
425
426 p->gen7_3DSTATE_STREAMOUT(p->dev, buffer_mask, sh->out.count,
427 ilo->rasterizer->state.rasterizer_discard, p->cp);
428 }
429 }
430
431 static void
432 gen7_pipeline_sf(struct ilo_3d_pipeline *p,
433 const struct ilo_context *ilo,
434 struct gen6_pipeline_session *session)
435 {
436 /* 3DSTATE_SBE */
437 if (DIRTY(RASTERIZER) || DIRTY(VS) || DIRTY(GS) || DIRTY(FS)) {
438 const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
439 const struct ilo_shader *last_sh =
440 (ilo->gs)? ilo->gs->shader :
441 (ilo->vs)? ilo->vs->shader : NULL;
442
443 p->gen7_3DSTATE_SBE(p->dev,
444 &ilo->rasterizer->state, fs, last_sh, p->cp);
445 }
446
447 /* 3DSTATE_SF */
448 if (DIRTY(RASTERIZER) || DIRTY(FRAMEBUFFER)) {
449 gen7_wa_pipe_control_cs_stall(p, true, true);
450
451 p->gen7_3DSTATE_SF(p->dev,
452 &ilo->rasterizer->state, ilo->fb.state.zsbuf, p->cp);
453 }
454 }
455
456 static void
457 gen7_pipeline_wm(struct ilo_3d_pipeline *p,
458 const struct ilo_context *ilo,
459 struct gen6_pipeline_session *session)
460 {
461 /* 3DSTATE_WM */
462 if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DEPTH_STENCIL_ALPHA) ||
463 DIRTY(RASTERIZER)) {
464 const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
465 const bool cc_may_kill = (ilo->dsa->state.alpha.enabled ||
466 ilo->blend->state.alpha_to_coverage);
467
468 if (fs)
469 assert(!fs->pcb.clip_state_size);
470
471 if (p->dev->gen == ILO_GEN(7) && session->hw_ctx_changed)
472 gen7_wa_pipe_control_wm_max_threads_stall(p);
473
474 p->gen7_3DSTATE_WM(p->dev,
475 fs, &ilo->rasterizer->state, cc_may_kill, p->cp);
476 }
477
478 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
479 if (session->binding_table_fs_changed) {
480 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
481 p->state.wm.BINDING_TABLE_STATE, p->cp);
482 }
483
484 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
485 if (session->sampler_state_fs_changed) {
486 p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
487 p->state.wm.SAMPLER_STATE, p->cp);
488 }
489
490 /* 3DSTATE_CONSTANT_PS */
491 if (session->pcb_state_fs_changed)
492 p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
493
494 /* 3DSTATE_PS */
495 if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
496 DIRTY(BLEND)) {
497 const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
498 const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
499 const bool dual_blend =
500 (!ilo->blend->state.logicop_enable &&
501 ilo->blend->state.rt[0].blend_enable &&
502 util_blend_state_is_dual(&ilo->blend->state, 0));
503
504 if (fs)
505 assert(!fs->pcb.clip_state_size);
506
507 p->gen7_3DSTATE_PS(p->dev, fs, num_samplers, dual_blend, p->cp);
508 }
509
510 /* 3DSTATE_SCISSOR_STATE_POINTERS */
511 if (session->scissor_state_changed) {
512 p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
513 p->state.SCISSOR_RECT, p->cp);
514 }
515
516 /* XXX what is the best way to know if this workaround is needed? */
517 {
518 const bool emit_3dstate_ps = (DIRTY(FS) ||
519 DIRTY(FRAGMENT_SAMPLERS) ||
520 DIRTY(BLEND));
521 const bool emit_3dstate_depth_buffer =
522 (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
523 session->state_bo_changed);
524
525 if (emit_3dstate_ps ||
526 emit_3dstate_depth_buffer ||
527 session->pcb_state_fs_changed ||
528 session->viewport_state_changed ||
529 session->binding_table_fs_changed ||
530 session->sampler_state_fs_changed ||
531 session->cc_state_cc_changed ||
532 session->cc_state_blend_changed ||
533 session->cc_state_dsa_changed)
534 gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
535 }
536
537 /*
538 * glCopyPixels() with GL_DEPTH, which flushes the context before copying
539 * the depth buffer to a temporary texture, could not update the depth
540 * buffer _sometimes_. Reissuing 3DSTATE_DEPTH_BUFFER in the new batch
541 * makes the problem gone.
542 */
543
544 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
545 if (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
546 session->state_bo_changed) {
547 const bool hiz = false;
548
549 p->gen7_3DSTATE_DEPTH_BUFFER(p->dev,
550 ilo->fb.state.zsbuf, &ilo->dsa->state, hiz, p->cp);
551
552 p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev,
553 (hiz) ? ilo->fb.state.zsbuf : NULL, p->cp);
554
555 p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
556
557 /* TODO */
558 p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
559 }
560 }
561
562 static void
563 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
564 const struct ilo_context *ilo,
565 struct gen6_pipeline_session *session)
566 {
567 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
568 if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
569 const uint32_t *packed_sample_pos;
570
571 gen7_wa_pipe_control_cs_stall(p, true, true);
572
573 packed_sample_pos =
574 (ilo->fb.num_samples > 4) ? p->packed_sample_position_8x :
575 (ilo->fb.num_samples > 1) ? &p->packed_sample_position_4x :
576 &p->packed_sample_position_1x;
577
578 p->gen6_3DSTATE_MULTISAMPLE(p->dev,
579 ilo->fb.num_samples, packed_sample_pos,
580 ilo->rasterizer->state.half_pixel_center, p->cp);
581
582 p->gen7_3DSTATE_SAMPLE_MASK(p->dev,
583 (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1,
584 ilo->fb.num_samples, p->cp);
585 }
586 }
587
588 static void
589 gen7_pipeline_commands(struct ilo_3d_pipeline *p,
590 const struct ilo_context *ilo,
591 struct gen6_pipeline_session *session)
592 {
593 /*
594 * We try to keep the order of the commands match, as closely as possible,
595 * that of the classic i965 driver. It allows us to compare the command
596 * streams easily.
597 */
598 gen6_pipeline_common_select(p, ilo, session);
599 gen6_pipeline_common_sip(p, ilo, session);
600 gen6_pipeline_vf_statistics(p, ilo, session);
601 gen7_pipeline_common_pcb_alloc(p, ilo, session);
602 gen6_pipeline_common_base_address(p, ilo, session);
603 gen7_pipeline_common_pointers_1(p, ilo, session);
604 gen7_pipeline_common_urb(p, ilo, session);
605 gen7_pipeline_common_pointers_2(p, ilo, session);
606 gen7_pipeline_wm_multisample(p, ilo, session);
607 gen7_pipeline_gs(p, ilo, session);
608 gen7_pipeline_hs(p, ilo, session);
609 gen7_pipeline_te(p, ilo, session);
610 gen7_pipeline_ds(p, ilo, session);
611 gen7_pipeline_vs(p, ilo, session);
612 gen7_pipeline_sol(p, ilo, session);
613 gen6_pipeline_clip(p, ilo, session);
614 gen7_pipeline_sf(p, ilo, session);
615 gen7_pipeline_wm(p, ilo, session);
616 gen6_pipeline_wm_raster(p, ilo, session);
617 gen6_pipeline_sf_rect(p, ilo, session);
618 gen6_pipeline_vf(p, ilo, session);
619 gen6_pipeline_vf_draw(p, ilo, session);
620 }
621
622 static void
623 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline *p,
624 const struct ilo_context *ilo,
625 const struct pipe_draw_info *info)
626 {
627 struct gen6_pipeline_session session;
628
629 gen6_pipeline_prepare(p, ilo, info, &session);
630
631 session.emit_draw_states = gen6_pipeline_states;
632 session.emit_draw_commands = gen7_pipeline_commands;
633
634 gen6_pipeline_draw(p, ilo, &session);
635 gen6_pipeline_end(p, ilo, &session);
636 }
637
638 static int
639 gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
640 const struct ilo_gpe_gen7 *gen7,
641 const struct ilo_context *ilo)
642 {
643 static int size;
644 enum ilo_gpe_gen7_command cmd;
645
646 if (size)
647 return size;
648
649 for (cmd = 0; cmd < ILO_GPE_GEN7_COMMAND_COUNT; cmd++) {
650 int count;
651
652 switch (cmd) {
653 case ILO_GPE_GEN7_PIPE_CONTROL:
654 /* for the workaround */
655 count = 2;
656 /* another one after 3DSTATE_URB */
657 count += 1;
658 /* and another one after 3DSTATE_CONSTANT_VS */
659 count += 1;
660 break;
661 case ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS:
662 count = 33;
663 break;
664 case ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS:
665 count = 34;
666 break;
667 case ILO_GPE_GEN7_MEDIA_VFE_STATE:
668 case ILO_GPE_GEN7_MEDIA_CURBE_LOAD:
669 case ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD:
670 case ILO_GPE_GEN7_MEDIA_STATE_FLUSH:
671 case ILO_GPE_GEN7_GPGPU_WALKER:
672 /* media commands */
673 count = 0;
674 break;
675 default:
676 count = 1;
677 break;
678 }
679
680 if (count) {
681 size += gen7->estimate_command_size(p->dev,
682 cmd, count);
683 }
684 }
685
686 return size;
687 }
688
689 static int
690 gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
691 const struct ilo_gpe_gen7 *gen7,
692 const struct ilo_context *ilo)
693 {
694 static int static_size;
695 int shader_type, count, size;
696
697 if (!static_size) {
698 struct {
699 enum ilo_gpe_gen7_state state;
700 int count;
701 } static_states[] = {
702 /* viewports */
703 { ILO_GPE_GEN7_SF_CLIP_VIEWPORT, 1 },
704 { ILO_GPE_GEN7_CC_VIEWPORT, 1 },
705 /* cc */
706 { ILO_GPE_GEN7_COLOR_CALC_STATE, 1 },
707 { ILO_GPE_GEN7_BLEND_STATE, ILO_MAX_DRAW_BUFFERS },
708 { ILO_GPE_GEN7_DEPTH_STENCIL_STATE, 1 },
709 /* scissors */
710 { ILO_GPE_GEN7_SCISSOR_RECT, 1 },
711 /* binding table (vs, gs, fs) */
712 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_VS_SURFACES },
713 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_GS_SURFACES },
714 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_WM_SURFACES },
715 };
716 int i;
717
718 for (i = 0; i < Elements(static_states); i++) {
719 static_size += gen7->estimate_state_size(p->dev,
720 static_states[i].state,
721 static_states[i].count);
722 }
723 }
724
725 size = static_size;
726
727 /*
728 * render targets (fs)
729 * sampler views (vs, fs)
730 * constant buffers (vs, fs)
731 */
732 count = ilo->fb.state.nr_cbufs;
733 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
734 count += ilo->view[shader_type].count;
735 count += ilo->cbuf[shader_type].count;
736 }
737
738 if (count) {
739 size += gen7->estimate_state_size(p->dev,
740 ILO_GPE_GEN7_SURFACE_STATE, count);
741 }
742
743 /* samplers (vs, fs) */
744 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
745 count = ilo->sampler[shader_type].count;
746 if (count) {
747 size += gen7->estimate_state_size(p->dev,
748 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE, count);
749 size += gen7->estimate_state_size(p->dev,
750 ILO_GPE_GEN7_SAMPLER_STATE, count);
751 }
752 }
753
754 /* pcb (vs) */
755 if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
756 const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
757
758 size += gen7->estimate_state_size(p->dev,
759 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, pcb_size);
760 }
761
762 return size;
763 }
764
765 static int
766 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p,
767 enum ilo_3d_pipeline_action action,
768 const void *arg)
769 {
770 const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
771 int size;
772
773 switch (action) {
774 case ILO_3D_PIPELINE_DRAW:
775 {
776 const struct ilo_context *ilo = arg;
777
778 size = gen7_pipeline_estimate_commands(p, gen7, ilo) +
779 gen7_pipeline_estimate_states(p, gen7, ilo);
780 }
781 break;
782 case ILO_3D_PIPELINE_FLUSH:
783 case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
784 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
785 size = gen7->estimate_command_size(p->dev,
786 ILO_GPE_GEN7_PIPE_CONTROL, 1);
787 break;
788 default:
789 assert(!"unknown 3D pipeline action");
790 size = 0;
791 break;
792 }
793
794 return size;
795 }
796
797 void
798 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
799 {
800 const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
801
802 p->estimate_size = ilo_3d_pipeline_estimate_size_gen7;
803 p->emit_draw = ilo_3d_pipeline_emit_draw_gen7;
804 p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
805 p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
806 p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
807
808 #define GEN6_USE(p, name, from) \
809 p->gen6_ ## name = from->emit_ ## name
810 GEN6_USE(p, STATE_BASE_ADDRESS, gen7);
811 GEN6_USE(p, STATE_SIP, gen7);
812 GEN6_USE(p, PIPELINE_SELECT, gen7);
813 GEN6_USE(p, 3DSTATE_VERTEX_BUFFERS, gen7);
814 GEN6_USE(p, 3DSTATE_VERTEX_ELEMENTS, gen7);
815 GEN6_USE(p, 3DSTATE_INDEX_BUFFER, gen7);
816 GEN6_USE(p, 3DSTATE_VF_STATISTICS, gen7);
817 GEN6_USE(p, 3DSTATE_SCISSOR_STATE_POINTERS, gen7);
818 GEN6_USE(p, 3DSTATE_VS, gen7);
819 GEN6_USE(p, 3DSTATE_CLIP, gen7);
820 GEN6_USE(p, 3DSTATE_CONSTANT_VS, gen7);
821 GEN6_USE(p, 3DSTATE_CONSTANT_GS, gen7);
822 GEN6_USE(p, 3DSTATE_CONSTANT_PS, gen7);
823 GEN6_USE(p, 3DSTATE_DRAWING_RECTANGLE, gen7);
824 GEN6_USE(p, 3DSTATE_POLY_STIPPLE_OFFSET, gen7);
825 GEN6_USE(p, 3DSTATE_POLY_STIPPLE_PATTERN, gen7);
826 GEN6_USE(p, 3DSTATE_LINE_STIPPLE, gen7);
827 GEN6_USE(p, 3DSTATE_AA_LINE_PARAMETERS, gen7);
828 GEN6_USE(p, 3DSTATE_MULTISAMPLE, gen7);
829 GEN6_USE(p, 3DSTATE_STENCIL_BUFFER, gen7);
830 GEN6_USE(p, 3DSTATE_HIER_DEPTH_BUFFER, gen7);
831 GEN6_USE(p, 3DSTATE_CLEAR_PARAMS, gen7);
832 GEN6_USE(p, PIPE_CONTROL, gen7);
833 GEN6_USE(p, 3DPRIMITIVE, gen7);
834 GEN6_USE(p, INTERFACE_DESCRIPTOR_DATA, gen7);
835 GEN6_USE(p, CC_VIEWPORT, gen7);
836 GEN6_USE(p, COLOR_CALC_STATE, gen7);
837 GEN6_USE(p, BLEND_STATE, gen7);
838 GEN6_USE(p, DEPTH_STENCIL_STATE, gen7);
839 GEN6_USE(p, SCISSOR_RECT, gen7);
840 GEN6_USE(p, BINDING_TABLE_STATE, gen7);
841 GEN6_USE(p, surf_SURFACE_STATE, gen7);
842 GEN6_USE(p, view_SURFACE_STATE, gen7);
843 GEN6_USE(p, cbuf_SURFACE_STATE, gen7);
844 GEN6_USE(p, SAMPLER_STATE, gen7);
845 GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen7);
846 GEN6_USE(p, push_constant_buffer, gen7);
847 #undef GEN6_USE
848
849 #define GEN7_USE(p, name, from) \
850 p->gen7_ ## name = from->emit_ ## name
851 GEN7_USE(p, 3DSTATE_DEPTH_BUFFER, gen7);
852 GEN7_USE(p, 3DSTATE_CC_STATE_POINTERS, gen7);
853 GEN7_USE(p, 3DSTATE_GS, gen7);
854 GEN7_USE(p, 3DSTATE_SF, gen7);
855 GEN7_USE(p, 3DSTATE_WM, gen7);
856 GEN7_USE(p, 3DSTATE_SAMPLE_MASK, gen7);
857 GEN7_USE(p, 3DSTATE_CONSTANT_HS, gen7);
858 GEN7_USE(p, 3DSTATE_CONSTANT_DS, gen7);
859 GEN7_USE(p, 3DSTATE_HS, gen7);
860 GEN7_USE(p, 3DSTATE_TE, gen7);
861 GEN7_USE(p, 3DSTATE_DS, gen7);
862 GEN7_USE(p, 3DSTATE_STREAMOUT, gen7);
863 GEN7_USE(p, 3DSTATE_SBE, gen7);
864 GEN7_USE(p, 3DSTATE_PS, gen7);
865 GEN7_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, gen7);
866 GEN7_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS_CC, gen7);
867 GEN7_USE(p, 3DSTATE_BLEND_STATE_POINTERS, gen7);
868 GEN7_USE(p, 3DSTATE_DEPTH_STENCIL_STATE_POINTERS, gen7);
869 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_VS, gen7);
870 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_HS, gen7);
871 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_DS, gen7);
872 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_GS, gen7);
873 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_PS, gen7);
874 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_VS, gen7);
875 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_HS, gen7);
876 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_DS, gen7);
877 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_GS, gen7);
878 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_PS, gen7);
879 GEN7_USE(p, 3DSTATE_URB_VS, gen7);
880 GEN7_USE(p, 3DSTATE_URB_HS, gen7);
881 GEN7_USE(p, 3DSTATE_URB_DS, gen7);
882 GEN7_USE(p, 3DSTATE_URB_GS, gen7);
883 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_VS, gen7);
884 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_HS, gen7);
885 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, gen7);
886 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_GS, gen7);
887 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_PS, gen7);
888 GEN7_USE(p, 3DSTATE_SO_DECL_LIST, gen7);
889 GEN7_USE(p, 3DSTATE_SO_BUFFER, gen7);
890 GEN7_USE(p, SF_CLIP_VIEWPORT, gen7);
891 #undef GEN7_USE
892 }