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[mesa.git] / src / gallium / drivers / ilo / ilo_3d_pipeline_gen7.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30
31 #include "ilo_blitter.h"
32 #include "ilo_context.h"
33 #include "ilo_cp.h"
34 #include "ilo_gpe_gen7.h"
35 #include "ilo_shader.h"
36 #include "ilo_state.h"
37 #include "ilo_3d_pipeline.h"
38 #include "ilo_3d_pipeline_gen6.h"
39 #include "ilo_3d_pipeline_gen7.h"
40
41 static void
42 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
43 bool change_multisample_state,
44 bool change_depth_state)
45 {
46 struct intel_bo *bo = NULL;
47 uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
48
49 assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
50
51 /* emit once */
52 if (p->state.has_gen6_wa_pipe_control)
53 return;
54 p->state.has_gen6_wa_pipe_control = true;
55
56 /*
57 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
58 *
59 * "Due to an HW issue driver needs to send a pipe control with stall
60 * when ever there is state change in depth bias related state"
61 *
62 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
63 *
64 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
65 * in the ring after this instruction
66 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
67 *
68 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
69 *
70 * "Driver must ierarchi that all the caches in the depth pipe are
71 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
72 * requires driver to send a PIPE_CONTROL with a CS stall along with a
73 * Depth Flush prior to this command.
74 *
75 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
76 *
77 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
78 * a post sync operation prior to the group of depth
79 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
80 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
81 */
82
83 if (change_multisample_state)
84 dw1 |= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH;
85
86 if (change_depth_state) {
87 dw1 |= GEN6_PIPE_CONTROL_WRITE_IMM;
88 bo = p->workaround_bo;
89 }
90
91 gen6_emit_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
92 }
93
94 static void
95 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
96 {
97 assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
98
99 /*
100 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
101 *
102 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
103 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
104 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
105 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
106 * needs to be sent before any combination of VS associated 3DSTATE."
107 */
108 gen6_emit_PIPE_CONTROL(p->dev,
109 GEN6_PIPE_CONTROL_DEPTH_STALL |
110 GEN6_PIPE_CONTROL_WRITE_IMM,
111 p->workaround_bo, 0, false, p->cp);
112 }
113
114 static void
115 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
116 bool change_depth_buffer)
117 {
118 assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
119
120 /*
121 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
122 *
123 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
124 * Enable bit set after all the following states are programmed:
125 *
126 * * 3DSTATE_PS
127 * * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
128 * * 3DSTATE_CONSTANT_PS
129 * * 3DSTATE_BINDING_TABLE_POINTERS_PS
130 * * 3DSTATE_SAMPLER_STATE_POINTERS_PS
131 * * 3DSTATE_CC_STATE_POINTERS
132 * * 3DSTATE_BLEND_STATE_POINTERS
133 * * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
134 *
135 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
136 *
137 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
138 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
139 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
140 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
141 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
142 * Depth Flush Bit set, followed by another pipelined depth stall
143 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
144 * guarantee that the pipeline from WM onwards is already flushed
145 * (e.g., via a preceding MI_FLUSH)."
146 */
147 gen6_emit_PIPE_CONTROL(p->dev,
148 GEN6_PIPE_CONTROL_DEPTH_STALL,
149 NULL, 0, false, p->cp);
150
151 if (!change_depth_buffer)
152 return;
153
154 gen6_emit_PIPE_CONTROL(p->dev,
155 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH,
156 NULL, 0, false, p->cp);
157
158 gen6_emit_PIPE_CONTROL(p->dev,
159 GEN6_PIPE_CONTROL_DEPTH_STALL,
160 NULL, 0, false, p->cp);
161 }
162
163 static void
164 gen7_wa_pipe_control_ps_max_threads_stall(struct ilo_3d_pipeline *p)
165 {
166 assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
167
168 /*
169 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
170 *
171 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
172 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
173 * Pixel Scoreboard set is required to be issued."
174 */
175 gen6_emit_PIPE_CONTROL(p->dev,
176 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
177 NULL, 0, false, p->cp);
178
179 }
180
181 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
182
183 static void
184 gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
185 const struct ilo_context *ilo,
186 struct gen6_pipeline_session *session)
187 {
188 /* 3DSTATE_URB_{VS,GS,HS,DS} */
189 if (DIRTY(VE) || DIRTY(VS)) {
190 /* the first 16KB are reserved for VS and PS PCBs */
191 const int offset =
192 (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
193 int vs_entry_size, vs_total_size;
194
195 vs_entry_size = (ilo->vs) ?
196 ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
197
198 /*
199 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
200 *
201 * "Programming Restriction: As the VS URB entry serves as both the
202 * per-vertex input and output of the VS shader, the VS URB
203 * Allocation Size must be sized to the maximum of the vertex input
204 * and output structures."
205 */
206 if (vs_entry_size < ilo->ve->count)
207 vs_entry_size = ilo->ve->count;
208
209 vs_entry_size *= sizeof(float) * 4;
210 vs_total_size = ilo->dev->urb_size - offset;
211
212 gen7_wa_pipe_control_vs_depth_stall(p);
213
214 gen7_emit_3DSTATE_URB_VS(p->dev,
215 offset, vs_total_size, vs_entry_size, p->cp);
216
217 gen7_emit_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
218 gen7_emit_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
219 gen7_emit_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
220 }
221 }
222
223 static void
224 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
225 const struct ilo_context *ilo,
226 struct gen6_pipeline_session *session)
227 {
228 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
229 if (session->hw_ctx_changed) {
230 /*
231 * Push constant buffers are only allowed to take up at most the first
232 * 16KB of the URB. Split the space evenly for VS and FS.
233 */
234 const int max_size =
235 (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
236 const int size = max_size / 2;
237 int offset = 0;
238
239 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev, offset, size, p->cp);
240 offset += size;
241
242 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev, offset, size, p->cp);
243
244 if (p->dev->gen == ILO_GEN(7))
245 gen7_wa_pipe_control_cs_stall(p, true, true);
246 }
247 }
248
249 static void
250 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
251 const struct ilo_context *ilo,
252 struct gen6_pipeline_session *session)
253 {
254 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
255 if (session->viewport_state_changed) {
256 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
257 p->state.CC_VIEWPORT, p->cp);
258
259 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
260 p->state.SF_CLIP_VIEWPORT, p->cp);
261 }
262 }
263
264 static void
265 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
266 const struct ilo_context *ilo,
267 struct gen6_pipeline_session *session)
268 {
269 /* 3DSTATE_BLEND_STATE_POINTERS */
270 if (session->cc_state_blend_changed) {
271 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(p->dev,
272 p->state.BLEND_STATE, p->cp);
273 }
274
275 /* 3DSTATE_CC_STATE_POINTERS */
276 if (session->cc_state_cc_changed) {
277 gen7_emit_3DSTATE_CC_STATE_POINTERS(p->dev,
278 p->state.COLOR_CALC_STATE, p->cp);
279 }
280
281 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
282 if (session->cc_state_dsa_changed) {
283 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
284 p->state.DEPTH_STENCIL_STATE, p->cp);
285 }
286 }
287
288 static void
289 gen7_pipeline_vs(struct ilo_3d_pipeline *p,
290 const struct ilo_context *ilo,
291 struct gen6_pipeline_session *session)
292 {
293 const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
294 const bool emit_3dstate_sampler_state = session->sampler_state_vs_changed;
295 /* see gen6_pipeline_vs() */
296 const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
297 const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
298 session->kernel_bo_changed);
299
300 /* emit depth stall before any of the VS commands */
301 if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
302 emit_3dstate_constant_vs || emit_3dstate_vs)
303 gen7_wa_pipe_control_vs_depth_stall(p);
304
305 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
306 if (emit_3dstate_binding_table) {
307 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
308 p->state.vs.BINDING_TABLE_STATE, p->cp);
309 }
310
311 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
312 if (emit_3dstate_sampler_state) {
313 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
314 p->state.vs.SAMPLER_STATE, p->cp);
315 }
316
317 /* 3DSTATE_CONSTANT_VS */
318 if (emit_3dstate_constant_vs) {
319 gen7_emit_3DSTATE_CONSTANT_VS(p->dev,
320 &p->state.vs.PUSH_CONSTANT_BUFFER,
321 &p->state.vs.PUSH_CONSTANT_BUFFER_size,
322 1, p->cp);
323 }
324
325 /* 3DSTATE_VS */
326 if (emit_3dstate_vs) {
327 const int num_samplers = ilo->sampler[PIPE_SHADER_VERTEX].count;
328
329 gen6_emit_3DSTATE_VS(p->dev, ilo->vs, num_samplers, p->cp);
330 }
331 }
332
333 static void
334 gen7_pipeline_hs(struct ilo_3d_pipeline *p,
335 const struct ilo_context *ilo,
336 struct gen6_pipeline_session *session)
337 {
338 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
339 if (session->hw_ctx_changed) {
340 gen7_emit_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
341 gen7_emit_3DSTATE_HS(p->dev, NULL, 0, p->cp);
342 }
343
344 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
345 if (session->hw_ctx_changed)
346 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
347 }
348
349 static void
350 gen7_pipeline_te(struct ilo_3d_pipeline *p,
351 const struct ilo_context *ilo,
352 struct gen6_pipeline_session *session)
353 {
354 /* 3DSTATE_TE */
355 if (session->hw_ctx_changed)
356 gen7_emit_3DSTATE_TE(p->dev, p->cp);
357 }
358
359 static void
360 gen7_pipeline_ds(struct ilo_3d_pipeline *p,
361 const struct ilo_context *ilo,
362 struct gen6_pipeline_session *session)
363 {
364 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
365 if (session->hw_ctx_changed) {
366 gen7_emit_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
367 gen7_emit_3DSTATE_DS(p->dev, NULL, 0, p->cp);
368 }
369
370 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
371 if (session->hw_ctx_changed)
372 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
373
374 }
375
376 static void
377 gen7_pipeline_gs(struct ilo_3d_pipeline *p,
378 const struct ilo_context *ilo,
379 struct gen6_pipeline_session *session)
380 {
381 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
382 if (session->hw_ctx_changed) {
383 gen7_emit_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
384 gen7_emit_3DSTATE_GS(p->dev, NULL, 0, p->cp);
385 }
386
387 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
388 if (session->binding_table_gs_changed) {
389 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
390 p->state.gs.BINDING_TABLE_STATE, p->cp);
391 }
392 }
393
394 static void
395 gen7_pipeline_sol(struct ilo_3d_pipeline *p,
396 const struct ilo_context *ilo,
397 struct gen6_pipeline_session *session)
398 {
399 const struct pipe_stream_output_info *so_info;
400 const struct ilo_shader_state *shader;
401 bool dirty_sh = false;
402
403 if (ilo->gs) {
404 shader = ilo->gs;
405 dirty_sh = DIRTY(GS);
406 }
407 else {
408 shader = ilo->vs;
409 dirty_sh = DIRTY(VS);
410 }
411
412 so_info = ilo_shader_get_kernel_so_info(shader);
413
414 gen6_pipeline_update_max_svbi(p, ilo, session);
415
416 /* 3DSTATE_SO_BUFFER */
417 if ((DIRTY(SO) || dirty_sh || session->batch_bo_changed) &&
418 ilo->so.enabled) {
419 int i;
420
421 for (i = 0; i < ilo->so.count; i++) {
422 const int stride = so_info->stride[i] * 4; /* in bytes */
423 int base = 0;
424
425 gen7_emit_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
426 ilo->so.states[i], p->cp);
427 }
428
429 for (; i < 4; i++)
430 gen7_emit_3DSTATE_SO_BUFFER(p->dev, i, 0, 0, NULL, p->cp);
431 }
432
433 /* 3DSTATE_SO_DECL_LIST */
434 if (dirty_sh && ilo->so.enabled)
435 gen7_emit_3DSTATE_SO_DECL_LIST(p->dev, so_info, p->cp);
436
437 /* 3DSTATE_STREAMOUT */
438 if (DIRTY(SO) || DIRTY(RASTERIZER) || dirty_sh) {
439 const unsigned buffer_mask = (1 << ilo->so.count) - 1;
440 const int output_count = ilo_shader_get_kernel_param(shader,
441 ILO_KERNEL_OUTPUT_COUNT);
442
443 gen7_emit_3DSTATE_STREAMOUT(p->dev, buffer_mask, output_count,
444 ilo->rasterizer->state.rasterizer_discard, p->cp);
445 }
446 }
447
448 static void
449 gen7_pipeline_sf(struct ilo_3d_pipeline *p,
450 const struct ilo_context *ilo,
451 struct gen6_pipeline_session *session)
452 {
453 /* 3DSTATE_SBE */
454 if (DIRTY(RASTERIZER) || DIRTY(FS))
455 gen7_emit_3DSTATE_SBE(p->dev, ilo->rasterizer, ilo->fs, ilo->cp);
456
457 /* 3DSTATE_SF */
458 if (DIRTY(RASTERIZER) || DIRTY(FB)) {
459 struct pipe_surface *zs = ilo->fb.state.zsbuf;
460
461 gen7_wa_pipe_control_cs_stall(p, true, true);
462 gen7_emit_3DSTATE_SF(p->dev, ilo->rasterizer,
463 (zs) ? zs->format : PIPE_FORMAT_NONE, p->cp);
464 }
465 }
466
467 static void
468 gen7_pipeline_wm(struct ilo_3d_pipeline *p,
469 const struct ilo_context *ilo,
470 struct gen6_pipeline_session *session)
471 {
472 /* 3DSTATE_WM */
473 if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DSA) || DIRTY(RASTERIZER)) {
474 const bool cc_may_kill = (ilo->dsa->dw_alpha ||
475 ilo->blend->alpha_to_coverage);
476
477 gen7_emit_3DSTATE_WM(p->dev, ilo->fs,
478 ilo->rasterizer, cc_may_kill, 0, p->cp);
479 }
480
481 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
482 if (session->binding_table_fs_changed) {
483 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
484 p->state.wm.BINDING_TABLE_STATE, p->cp);
485 }
486
487 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
488 if (session->sampler_state_fs_changed) {
489 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
490 p->state.wm.SAMPLER_STATE, p->cp);
491 }
492
493 /* 3DSTATE_CONSTANT_PS */
494 if (session->pcb_state_fs_changed) {
495 gen7_emit_3DSTATE_CONSTANT_PS(p->dev,
496 &p->state.wm.PUSH_CONSTANT_BUFFER,
497 &p->state.wm.PUSH_CONSTANT_BUFFER_size,
498 1, p->cp);
499 }
500
501 /* 3DSTATE_PS */
502 if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) ||
503 session->kernel_bo_changed) {
504 const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
505 const bool dual_blend = ilo->blend->dual_blend;
506
507 if ((p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5)) &&
508 session->hw_ctx_changed)
509 gen7_wa_pipe_control_ps_max_threads_stall(p);
510
511 gen7_emit_3DSTATE_PS(p->dev, ilo->fs, num_samplers, dual_blend, p->cp);
512 }
513
514 /* 3DSTATE_SCISSOR_STATE_POINTERS */
515 if (session->scissor_state_changed) {
516 gen6_emit_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
517 p->state.SCISSOR_RECT, p->cp);
518 }
519
520 /* XXX what is the best way to know if this workaround is needed? */
521 {
522 const bool emit_3dstate_ps =
523 (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND));
524 const bool emit_3dstate_depth_buffer =
525 (DIRTY(FB) || DIRTY(DSA) || session->state_bo_changed);
526
527 if (emit_3dstate_ps ||
528 emit_3dstate_depth_buffer ||
529 session->pcb_state_fs_changed ||
530 session->viewport_state_changed ||
531 session->binding_table_fs_changed ||
532 session->sampler_state_fs_changed ||
533 session->cc_state_cc_changed ||
534 session->cc_state_blend_changed ||
535 session->cc_state_dsa_changed)
536 gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
537 }
538
539 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
540 if (DIRTY(FB) || session->batch_bo_changed) {
541 const struct ilo_zs_surface *zs;
542 uint32_t clear_params;
543
544 if (ilo->fb.state.zsbuf) {
545 const struct ilo_surface_cso *surface =
546 (const struct ilo_surface_cso *) ilo->fb.state.zsbuf;
547 const struct ilo_texture_slice *slice =
548 ilo_texture_get_slice(ilo_texture(surface->base.texture),
549 surface->base.u.tex.level, surface->base.u.tex.first_layer);
550
551 assert(!surface->is_rt);
552 zs = &surface->u.zs;
553 clear_params = slice->clear_value;
554 }
555 else {
556 zs = &ilo->fb.null_zs;
557 clear_params = 0;
558 }
559
560 gen6_emit_3DSTATE_DEPTH_BUFFER(p->dev, zs, p->cp);
561 gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p->dev, zs, p->cp);
562 gen6_emit_3DSTATE_STENCIL_BUFFER(p->dev, zs, p->cp);
563 gen7_emit_3DSTATE_CLEAR_PARAMS(p->dev, clear_params, p->cp);
564 }
565 }
566
567 static void
568 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
569 const struct ilo_context *ilo,
570 struct gen6_pipeline_session *session)
571 {
572 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
573 if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
574 const uint32_t *packed_sample_pos;
575
576 gen7_wa_pipe_control_cs_stall(p, true, true);
577
578 packed_sample_pos =
579 (ilo->fb.num_samples > 4) ? p->packed_sample_position_8x :
580 (ilo->fb.num_samples > 1) ? &p->packed_sample_position_4x :
581 &p->packed_sample_position_1x;
582
583 gen6_emit_3DSTATE_MULTISAMPLE(p->dev,
584 ilo->fb.num_samples, packed_sample_pos,
585 ilo->rasterizer->state.half_pixel_center, p->cp);
586
587 gen7_emit_3DSTATE_SAMPLE_MASK(p->dev,
588 (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1,
589 ilo->fb.num_samples, p->cp);
590 }
591 }
592
593 static void
594 gen7_pipeline_vf_draw(struct ilo_3d_pipeline *p,
595 const struct ilo_context *ilo,
596 struct gen6_pipeline_session *session)
597 {
598 /* 3DPRIMITIVE */
599 gen7_emit_3DPRIMITIVE(p->dev, ilo->draw, &ilo->ib, false, p->cp);
600 p->state.has_gen6_wa_pipe_control = false;
601 }
602
603 static void
604 gen7_pipeline_commands(struct ilo_3d_pipeline *p,
605 const struct ilo_context *ilo,
606 struct gen6_pipeline_session *session)
607 {
608 /*
609 * We try to keep the order of the commands match, as closely as possible,
610 * that of the classic i965 driver. It allows us to compare the command
611 * streams easily.
612 */
613 gen6_pipeline_common_select(p, ilo, session);
614 gen6_pipeline_common_sip(p, ilo, session);
615 gen6_pipeline_vf_statistics(p, ilo, session);
616 gen7_pipeline_common_pcb_alloc(p, ilo, session);
617 gen6_pipeline_common_base_address(p, ilo, session);
618 gen7_pipeline_common_pointers_1(p, ilo, session);
619 gen7_pipeline_common_urb(p, ilo, session);
620 gen7_pipeline_common_pointers_2(p, ilo, session);
621 gen7_pipeline_wm_multisample(p, ilo, session);
622 gen7_pipeline_gs(p, ilo, session);
623 gen7_pipeline_hs(p, ilo, session);
624 gen7_pipeline_te(p, ilo, session);
625 gen7_pipeline_ds(p, ilo, session);
626 gen7_pipeline_vs(p, ilo, session);
627 gen7_pipeline_sol(p, ilo, session);
628 gen6_pipeline_clip(p, ilo, session);
629 gen7_pipeline_sf(p, ilo, session);
630 gen7_pipeline_wm(p, ilo, session);
631 gen6_pipeline_wm_raster(p, ilo, session);
632 gen6_pipeline_sf_rect(p, ilo, session);
633 gen6_pipeline_vf(p, ilo, session);
634 gen7_pipeline_vf_draw(p, ilo, session);
635 }
636
637 static void
638 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline *p,
639 const struct ilo_context *ilo)
640 {
641 struct gen6_pipeline_session session;
642
643 gen6_pipeline_prepare(p, ilo, &session);
644
645 session.emit_draw_states = gen6_pipeline_states;
646 session.emit_draw_commands = gen7_pipeline_commands;
647
648 gen6_pipeline_draw(p, ilo, &session);
649 gen6_pipeline_end(p, ilo, &session);
650 }
651
652 static void
653 gen7_rectlist_pcb_alloc(struct ilo_3d_pipeline *p,
654 const struct ilo_blitter *blitter,
655 struct gen6_rectlist_session *session)
656 {
657 /*
658 * Push constant buffers are only allowed to take up at most the first
659 * 16KB of the URB. Split the space evenly for VS and FS.
660 */
661 const int max_size =
662 (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
663 const int size = max_size / 2;
664 int offset = 0;
665
666 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev, offset, size, p->cp);
667 offset += size;
668
669 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev, offset, size, p->cp);
670
671 gen7_wa_pipe_control_cs_stall(p, true, true);
672 }
673
674 static void
675 gen7_rectlist_urb(struct ilo_3d_pipeline *p,
676 const struct ilo_blitter *blitter,
677 struct gen6_rectlist_session *session)
678 {
679 /* the first 16KB are reserved for VS and PS PCBs */
680 const int offset =
681 (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
682
683 gen7_emit_3DSTATE_URB_VS(p->dev, offset, p->dev->urb_size - offset,
684 blitter->ve.count * 4 * sizeof(float), p->cp);
685
686 gen7_emit_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
687 gen7_emit_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
688 gen7_emit_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
689 }
690
691 static void
692 gen7_rectlist_vs_to_sf(struct ilo_3d_pipeline *p,
693 const struct ilo_blitter *blitter,
694 struct gen6_rectlist_session *session)
695 {
696 gen7_emit_3DSTATE_CONSTANT_VS(p->dev, NULL, NULL, 0, p->cp);
697 gen6_emit_3DSTATE_VS(p->dev, NULL, 0, p->cp);
698
699 gen7_emit_3DSTATE_CONSTANT_HS(p->dev, NULL, NULL, 0, p->cp);
700 gen7_emit_3DSTATE_HS(p->dev, NULL, 0, p->cp);
701
702 gen7_emit_3DSTATE_TE(p->dev, p->cp);
703
704 gen7_emit_3DSTATE_CONSTANT_DS(p->dev, NULL, NULL, 0, p->cp);
705 gen7_emit_3DSTATE_DS(p->dev, NULL, 0, p->cp);
706
707 gen7_emit_3DSTATE_CONSTANT_GS(p->dev, NULL, NULL, 0, p->cp);
708 gen7_emit_3DSTATE_GS(p->dev, NULL, 0, p->cp);
709
710 gen7_emit_3DSTATE_STREAMOUT(p->dev, 0x0, 0, false, p->cp);
711
712 gen6_emit_3DSTATE_CLIP(p->dev, NULL, NULL, false, 0, p->cp);
713
714 gen7_wa_pipe_control_cs_stall(p, true, true);
715
716 gen7_emit_3DSTATE_SF(p->dev, NULL, blitter->fb.dst.base.format, p->cp);
717 gen7_emit_3DSTATE_SBE(p->dev, NULL, NULL, p->cp);
718 }
719
720 static void
721 gen7_rectlist_wm(struct ilo_3d_pipeline *p,
722 const struct ilo_blitter *blitter,
723 struct gen6_rectlist_session *session)
724 {
725 uint32_t hiz_op;
726
727 switch (blitter->op) {
728 case ILO_BLITTER_RECTLIST_CLEAR_ZS:
729 hiz_op = GEN7_WM_DW1_DEPTH_CLEAR;
730 break;
731 case ILO_BLITTER_RECTLIST_RESOLVE_Z:
732 hiz_op = GEN7_WM_DW1_DEPTH_RESOLVE;
733 break;
734 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
735 hiz_op = GEN7_WM_DW1_HIZ_RESOLVE;
736 break;
737 default:
738 hiz_op = 0;
739 break;
740 }
741
742 gen7_emit_3DSTATE_WM(p->dev, NULL, NULL, false, hiz_op, p->cp);
743
744 gen7_emit_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
745
746 gen7_wa_pipe_control_ps_max_threads_stall(p);
747 gen7_emit_3DSTATE_PS(p->dev, NULL, 0, false, p->cp);
748 }
749
750 static void
751 gen7_rectlist_wm_depth(struct ilo_3d_pipeline *p,
752 const struct ilo_blitter *blitter,
753 struct gen6_rectlist_session *session)
754 {
755 gen7_wa_pipe_control_wm_depth_stall(p, true);
756
757 if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
758 ILO_BLITTER_USE_FB_STENCIL)) {
759 gen6_emit_3DSTATE_DEPTH_BUFFER(p->dev,
760 &blitter->fb.dst.u.zs, p->cp);
761 }
762
763 if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
764 gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p->dev,
765 &blitter->fb.dst.u.zs, p->cp);
766 }
767
768 if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
769 gen6_emit_3DSTATE_STENCIL_BUFFER(p->dev,
770 &blitter->fb.dst.u.zs, p->cp);
771 }
772
773 gen7_emit_3DSTATE_CLEAR_PARAMS(p->dev,
774 blitter->depth_clear_value, p->cp);
775 }
776
777 static void
778 gen7_rectlist_wm_multisample(struct ilo_3d_pipeline *p,
779 const struct ilo_blitter *blitter,
780 struct gen6_rectlist_session *session)
781 {
782 const uint32_t *packed_sample_pos =
783 (blitter->fb.num_samples > 4) ? p->packed_sample_position_8x :
784 (blitter->fb.num_samples > 1) ? &p->packed_sample_position_4x :
785 &p->packed_sample_position_1x;
786
787 gen7_wa_pipe_control_cs_stall(p, true, true);
788
789 gen6_emit_3DSTATE_MULTISAMPLE(p->dev, blitter->fb.num_samples,
790 packed_sample_pos, true, p->cp);
791
792 gen7_emit_3DSTATE_SAMPLE_MASK(p->dev,
793 (1 << blitter->fb.num_samples) - 1, blitter->fb.num_samples, p->cp);
794 }
795
796 static void
797 gen7_rectlist_commands(struct ilo_3d_pipeline *p,
798 const struct ilo_blitter *blitter,
799 struct gen6_rectlist_session *session)
800 {
801 gen7_rectlist_wm_multisample(p, blitter, session);
802
803 gen6_emit_STATE_BASE_ADDRESS(p->dev,
804 NULL, /* General State Base */
805 p->cp->bo, /* Surface State Base */
806 p->cp->bo, /* Dynamic State Base */
807 NULL, /* Indirect Object Base */
808 NULL, /* Instruction Base */
809 0, 0, 0, 0, p->cp);
810
811 gen6_emit_3DSTATE_VERTEX_BUFFERS(p->dev,
812 &blitter->ve, &blitter->vb, p->cp);
813
814 gen6_emit_3DSTATE_VERTEX_ELEMENTS(p->dev,
815 &blitter->ve, false, false, p->cp);
816
817 gen7_rectlist_pcb_alloc(p, blitter, session);
818
819 /* needed for any VS-related commands */
820 gen7_wa_pipe_control_vs_depth_stall(p);
821
822 gen7_rectlist_urb(p, blitter, session);
823
824 if (blitter->uses & ILO_BLITTER_USE_DSA) {
825 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
826 session->DEPTH_STENCIL_STATE, p->cp);
827 }
828
829 if (blitter->uses & ILO_BLITTER_USE_CC) {
830 gen7_emit_3DSTATE_CC_STATE_POINTERS(p->dev,
831 session->COLOR_CALC_STATE, p->cp);
832 }
833
834 gen7_rectlist_vs_to_sf(p, blitter, session);
835 gen7_rectlist_wm(p, blitter, session);
836
837 if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
838 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
839 session->CC_VIEWPORT, p->cp);
840 }
841
842 gen7_rectlist_wm_depth(p, blitter, session);
843
844 gen6_emit_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
845 blitter->fb.width, blitter->fb.height, p->cp);
846
847 gen7_emit_3DPRIMITIVE(p->dev, &blitter->draw, NULL, true, p->cp);
848 }
849
850 static void
851 gen7_rectlist_states(struct ilo_3d_pipeline *p,
852 const struct ilo_blitter *blitter,
853 struct gen6_rectlist_session *session)
854 {
855 if (blitter->uses & ILO_BLITTER_USE_DSA) {
856 session->DEPTH_STENCIL_STATE =
857 gen6_emit_DEPTH_STENCIL_STATE(p->dev, &blitter->dsa, p->cp);
858 }
859
860 if (blitter->uses & ILO_BLITTER_USE_CC) {
861 session->COLOR_CALC_STATE =
862 gen6_emit_COLOR_CALC_STATE(p->dev, &blitter->cc.stencil_ref,
863 blitter->cc.alpha_ref, &blitter->cc.blend_color, p->cp);
864 }
865
866 if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
867 session->CC_VIEWPORT =
868 gen6_emit_CC_VIEWPORT(p->dev, &blitter->viewport, 1, p->cp);
869 }
870 }
871
872 static void
873 ilo_3d_pipeline_emit_rectlist_gen7(struct ilo_3d_pipeline *p,
874 const struct ilo_blitter *blitter)
875 {
876 struct gen6_rectlist_session session;
877
878 memset(&session, 0, sizeof(session));
879 gen7_rectlist_states(p, blitter, &session);
880 gen7_rectlist_commands(p, blitter, &session);
881 }
882
883 static int
884 gen7_pipeline_max_command_size(const struct ilo_3d_pipeline *p)
885 {
886 static int size;
887
888 if (!size) {
889 size += GEN7_3DSTATE_URB_ANY__SIZE * 4;
890 size += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
891 size += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
892 size += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
893 size += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
894 size += GEN6_PIPE_CONTROL__SIZE * 5;
895
896 size +=
897 GEN6_STATE_BASE_ADDRESS__SIZE +
898 GEN6_STATE_SIP__SIZE +
899 GEN6_3DSTATE_VF_STATISTICS__SIZE +
900 GEN6_PIPELINE_SELECT__SIZE +
901 GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
902 GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
903 GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
904 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
905 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
906 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
907 GEN6_3DSTATE_INDEX_BUFFER__SIZE +
908 GEN75_3DSTATE_VF__SIZE +
909 GEN6_3DSTATE_VS__SIZE +
910 GEN6_3DSTATE_GS__SIZE +
911 GEN6_3DSTATE_CLIP__SIZE +
912 GEN6_3DSTATE_SF__SIZE +
913 GEN6_3DSTATE_WM__SIZE +
914 GEN6_3DSTATE_SAMPLE_MASK__SIZE +
915 GEN7_3DSTATE_HS__SIZE +
916 GEN7_3DSTATE_TE__SIZE +
917 GEN7_3DSTATE_DS__SIZE +
918 GEN7_3DSTATE_STREAMOUT__SIZE +
919 GEN7_3DSTATE_SBE__SIZE +
920 GEN7_3DSTATE_PS__SIZE +
921 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
922 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
923 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
924 GEN6_3DSTATE_LINE_STIPPLE__SIZE +
925 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
926 GEN6_3DSTATE_MULTISAMPLE__SIZE +
927 GEN7_3DSTATE_SO_DECL_LIST__SIZE +
928 GEN6_3DPRIMITIVE__SIZE;
929 }
930
931 return size;
932 }
933
934 static int
935 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p,
936 enum ilo_3d_pipeline_action action,
937 const void *arg)
938 {
939 int size;
940
941 switch (action) {
942 case ILO_3D_PIPELINE_DRAW:
943 {
944 const struct ilo_context *ilo = arg;
945
946 size = gen7_pipeline_max_command_size(p) +
947 gen6_pipeline_estimate_state_size(p, ilo);
948 }
949 break;
950 case ILO_3D_PIPELINE_FLUSH:
951 case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
952 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
953 size = GEN6_PIPE_CONTROL__SIZE;
954 break;
955 case ILO_3D_PIPELINE_WRITE_STATISTICS:
956 {
957 const int num_regs = 10;
958 const int num_pads = 1;
959
960 size = GEN6_PIPE_CONTROL__SIZE;
961 size += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs;
962 size += GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
963 }
964 break;
965 case ILO_3D_PIPELINE_RECTLIST:
966 size = 64 + 256; /* states + commands */
967 break;
968 default:
969 assert(!"unknown 3D pipeline action");
970 size = 0;
971 break;
972 }
973
974 return size;
975 }
976
977 void
978 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
979 {
980 p->estimate_size = ilo_3d_pipeline_estimate_size_gen7;
981 p->emit_draw = ilo_3d_pipeline_emit_draw_gen7;
982 p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
983 p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
984 p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
985 p->emit_write_statistics = ilo_3d_pipeline_emit_write_statistics_gen6;
986 p->emit_rectlist = ilo_3d_pipeline_emit_rectlist_gen7;
987 }