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[mesa.git] / src / gallium / drivers / ilo / ilo_3d_pipeline_gen7.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "util/u_dual_blend.h"
29 #include "intel_reg.h"
30
31 #include "shader/ilo_shader_internal.h"
32 #include "ilo_common.h"
33 #include "ilo_context.h"
34 #include "ilo_cp.h"
35 #include "ilo_gpe_gen7.h"
36 #include "ilo_shader.h"
37 #include "ilo_state.h"
38 #include "ilo_3d_pipeline.h"
39 #include "ilo_3d_pipeline_gen6.h"
40 #include "ilo_3d_pipeline_gen7.h"
41
42 static void
43 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
44 bool change_multisample_state,
45 bool change_depth_state)
46 {
47 struct intel_bo *bo = NULL;
48 uint32_t dw1 = PIPE_CONTROL_CS_STALL;
49
50 assert(p->dev->gen == ILO_GEN(7));
51
52 /* emit once */
53 if (p->state.has_gen6_wa_pipe_control)
54 return;
55 p->state.has_gen6_wa_pipe_control = true;
56
57 /*
58 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
59 *
60 * "Due to an HW issue driver needs to send a pipe control with stall
61 * when ever there is state change in depth bias related state"
62 *
63 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
64 *
65 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
66 * in the ring after this instruction
67 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
68 *
69 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
70 *
71 * "Driver must ierarchi that all the caches in the depth pipe are
72 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
73 * requires driver to send a PIPE_CONTROL with a CS stall along with a
74 * Depth Flush prior to this command.
75 *
76 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
77 *
78 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
79 * a post sync operation prior to the group of depth
80 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
81 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
82 */
83
84 if (change_multisample_state)
85 dw1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
86
87 if (change_depth_state) {
88 dw1 |= PIPE_CONTROL_WRITE_IMMEDIATE;
89 bo = p->workaround_bo;
90 }
91
92 p->gen6_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
93 }
94
95 static void
96 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
97 {
98 assert(p->dev->gen == ILO_GEN(7));
99
100 /*
101 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
102 *
103 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
104 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
105 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
106 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
107 * needs to be sent before any combination of VS associated 3DSTATE."
108 */
109 p->gen6_PIPE_CONTROL(p->dev,
110 PIPE_CONTROL_DEPTH_STALL |
111 PIPE_CONTROL_WRITE_IMMEDIATE,
112 p->workaround_bo, 0, false, p->cp);
113 }
114
115 static void
116 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
117 bool change_depth_buffer)
118 {
119 assert(p->dev->gen == ILO_GEN(7));
120
121 /*
122 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
123 *
124 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
125 * Enable bit set after all the following states are programmed:
126 *
127 * * 3DSTATE_PS
128 * * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
129 * * 3DSTATE_CONSTANT_PS
130 * * 3DSTATE_BINDING_TABLE_POINTERS_PS
131 * * 3DSTATE_SAMPLER_STATE_POINTERS_PS
132 * * 3DSTATE_CC_STATE_POINTERS
133 * * 3DSTATE_BLEND_STATE_POINTERS
134 * * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
135 *
136 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
137 *
138 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
139 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
140 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
141 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
142 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
143 * Depth Flush Bit set, followed by another pipelined depth stall
144 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
145 * guarantee that the pipeline from WM onwards is already flushed
146 * (e.g., via a preceding MI_FLUSH)."
147 */
148 p->gen6_PIPE_CONTROL(p->dev,
149 PIPE_CONTROL_DEPTH_STALL,
150 NULL, 0, false, p->cp);
151
152 if (!change_depth_buffer)
153 return;
154
155 p->gen6_PIPE_CONTROL(p->dev,
156 PIPE_CONTROL_DEPTH_CACHE_FLUSH,
157 NULL, 0, false, p->cp);
158
159 p->gen6_PIPE_CONTROL(p->dev,
160 PIPE_CONTROL_DEPTH_STALL,
161 NULL, 0, false, p->cp);
162 }
163
164 static void
165 gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
166 {
167 assert(p->dev->gen == ILO_GEN(7));
168
169 /*
170 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
171 *
172 * "If this field (Maximum Number of Threads in 3DSTATE_WM) is changed
173 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
174 * Pixel Scoreboard set is required to be issued."
175 */
176 p->gen6_PIPE_CONTROL(p->dev,
177 PIPE_CONTROL_STALL_AT_SCOREBOARD,
178 NULL, 0, false, p->cp);
179
180 }
181
182 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
183
184 static void
185 gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
186 const struct ilo_context *ilo,
187 struct gen6_pipeline_session *session)
188 {
189 /* 3DSTATE_URB_{VS,GS,HS,DS} */
190 if (DIRTY(VERTEX_ELEMENTS) || DIRTY(VS)) {
191 const struct ilo_shader *vs = (ilo->vs) ? ilo->vs->shader : NULL;
192 /* the first 16KB are reserved for VS and PS PCBs */
193 const int offset = 16 * 1024;
194 int vs_entry_size, vs_total_size;
195
196 vs_entry_size = (vs) ? vs->out.count : 0;
197
198 /*
199 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
200 *
201 * "Programming Restriction: As the VS URB entry serves as both the
202 * per-vertex input and output of the VS shader, the VS URB
203 * Allocation Size must be sized to the maximum of the vertex input
204 * and output structures."
205 */
206 if (vs_entry_size < ilo->ve->count)
207 vs_entry_size = ilo->ve->count;
208
209 vs_entry_size *= sizeof(float) * 4;
210 vs_total_size = ilo->dev->urb_size - offset;
211
212 gen7_wa_pipe_control_vs_depth_stall(p);
213
214 p->gen7_3DSTATE_URB_VS(p->dev,
215 offset, vs_total_size, vs_entry_size, p->cp);
216
217 p->gen7_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
218 p->gen7_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
219 p->gen7_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
220 }
221 }
222
223 static void
224 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
225 const struct ilo_context *ilo,
226 struct gen6_pipeline_session *session)
227 {
228 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
229 if (session->hw_ctx_changed) {
230 /*
231 * push constant buffers are only allowed to take up at most the first
232 * 16KB of the URB
233 */
234 p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev,
235 0, 8192, p->cp);
236
237 p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev,
238 8192, 8192, p->cp);
239
240 gen7_wa_pipe_control_cs_stall(p, true, true);
241 }
242 }
243
244 static void
245 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
246 const struct ilo_context *ilo,
247 struct gen6_pipeline_session *session)
248 {
249 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
250 if (session->viewport_state_changed) {
251 p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
252 p->state.CC_VIEWPORT, p->cp);
253
254 p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
255 p->state.SF_CLIP_VIEWPORT, p->cp);
256 }
257 }
258
259 static void
260 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
261 const struct ilo_context *ilo,
262 struct gen6_pipeline_session *session)
263 {
264 /* 3DSTATE_BLEND_STATE_POINTERS */
265 if (session->cc_state_blend_changed) {
266 p->gen7_3DSTATE_BLEND_STATE_POINTERS(p->dev,
267 p->state.BLEND_STATE, p->cp);
268 }
269
270 /* 3DSTATE_CC_STATE_POINTERS */
271 if (session->cc_state_cc_changed) {
272 p->gen7_3DSTATE_CC_STATE_POINTERS(p->dev,
273 p->state.COLOR_CALC_STATE, p->cp);
274 }
275
276 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
277 if (session->cc_state_dsa_changed) {
278 p->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
279 p->state.DEPTH_STENCIL_STATE, p->cp);
280 }
281 }
282
283 static void
284 gen7_pipeline_vs(struct ilo_3d_pipeline *p,
285 const struct ilo_context *ilo,
286 struct gen6_pipeline_session *session)
287 {
288 const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
289 const bool emit_3dstate_sampler_state = session->sampler_state_vs_changed;
290 /* see gen6_pipeline_vs() */
291 const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
292 const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(VERTEX_SAMPLERS));
293
294 /* emit depth stall before any of the VS commands */
295 if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
296 emit_3dstate_constant_vs || emit_3dstate_vs)
297 gen7_wa_pipe_control_vs_depth_stall(p);
298
299 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
300 if (emit_3dstate_binding_table) {
301 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
302 p->state.vs.BINDING_TABLE_STATE, p->cp);
303 }
304
305 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
306 if (emit_3dstate_sampler_state) {
307 p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
308 p->state.vs.SAMPLER_STATE, p->cp);
309 }
310
311 gen6_pipeline_vs(p, ilo, session);
312 }
313
314 static void
315 gen7_pipeline_hs(struct ilo_3d_pipeline *p,
316 const struct ilo_context *ilo,
317 struct gen6_pipeline_session *session)
318 {
319 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
320 if (session->hw_ctx_changed) {
321 p->gen7_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
322 p->gen7_3DSTATE_HS(p->dev, NULL, 0, 0, p->cp);
323 }
324
325 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
326 if (session->hw_ctx_changed)
327 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
328 }
329
330 static void
331 gen7_pipeline_te(struct ilo_3d_pipeline *p,
332 const struct ilo_context *ilo,
333 struct gen6_pipeline_session *session)
334 {
335 /* 3DSTATE_TE */
336 if (session->hw_ctx_changed)
337 p->gen7_3DSTATE_TE(p->dev, p->cp);
338 }
339
340 static void
341 gen7_pipeline_ds(struct ilo_3d_pipeline *p,
342 const struct ilo_context *ilo,
343 struct gen6_pipeline_session *session)
344 {
345 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
346 if (session->hw_ctx_changed) {
347 p->gen7_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
348 p->gen7_3DSTATE_DS(p->dev, NULL, 0, 0, p->cp);
349 }
350
351 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
352 if (session->hw_ctx_changed)
353 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
354
355 }
356
357 static void
358 gen7_pipeline_gs(struct ilo_3d_pipeline *p,
359 const struct ilo_context *ilo,
360 struct gen6_pipeline_session *session)
361 {
362 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
363 if (session->hw_ctx_changed) {
364 p->gen6_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
365 p->gen7_3DSTATE_GS(p->dev, NULL, 0, p->cp);
366 }
367
368 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
369 if (session->binding_table_gs_changed) {
370 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
371 p->state.gs.BINDING_TABLE_STATE, p->cp);
372 }
373 }
374
375 static void
376 gen7_pipeline_sol(struct ilo_3d_pipeline *p,
377 const struct ilo_context *ilo,
378 struct gen6_pipeline_session *session)
379 {
380 const struct pipe_stream_output_info *so_info;
381 const struct ilo_shader *sh;
382 bool dirty_sh = false;
383
384 if (ilo->gs) {
385 so_info = &ilo->gs->info.stream_output;
386 sh = ilo->gs->shader;
387 dirty_sh = DIRTY(GS);
388 }
389 else {
390 so_info = &ilo->vs->info.stream_output;
391 sh = ilo->vs->shader;
392 dirty_sh = DIRTY(VS);
393 }
394
395 gen6_pipeline_update_max_svbi(p, ilo, session);
396
397 /* 3DSTATE_SO_BUFFER */
398 if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh ||
399 session->batch_bo_changed) && ilo->so.enabled) {
400 int i;
401
402 for (i = 0; i < ilo->so.count; i++) {
403 const int stride = so_info->stride[i] * 4; /* in bytes */
404 int base = 0;
405
406 /* reset HW write offsets and offset buffer base */
407 if (!p->cp->render_ctx) {
408 ilo_cp_set_one_off_flags(p->cp, INTEL_EXEC_GEN7_SOL_RESET);
409 base += p->state.so_num_vertices * stride;
410 }
411
412 p->gen7_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
413 ilo->so.states[i], p->cp);
414 }
415
416 for (; i < 4; i++)
417 p->gen7_3DSTATE_SO_BUFFER(p->dev, i, 0, 0, NULL, p->cp);
418 }
419
420 /* 3DSTATE_SO_DECL_LIST */
421 if (dirty_sh && ilo->so.enabled)
422 p->gen7_3DSTATE_SO_DECL_LIST(p->dev, so_info, sh, p->cp);
423
424 /* 3DSTATE_STREAMOUT */
425 if (DIRTY(STREAM_OUTPUT_TARGETS) || DIRTY(RASTERIZER) || dirty_sh) {
426 const unsigned buffer_mask = (1 << ilo->so.count) - 1;
427
428 p->gen7_3DSTATE_STREAMOUT(p->dev, buffer_mask, sh->out.count,
429 ilo->rasterizer->state.rasterizer_discard, p->cp);
430 }
431 }
432
433 static void
434 gen7_pipeline_sf(struct ilo_3d_pipeline *p,
435 const struct ilo_context *ilo,
436 struct gen6_pipeline_session *session)
437 {
438 /* 3DSTATE_SBE */
439 if (DIRTY(RASTERIZER) || DIRTY(VS) || DIRTY(GS) || DIRTY(FS)) {
440 const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
441 const struct ilo_shader *last_sh =
442 (ilo->gs)? ilo->gs->shader :
443 (ilo->vs)? ilo->vs->shader : NULL;
444
445 p->gen7_3DSTATE_SBE(p->dev,
446 &ilo->rasterizer->state, fs, last_sh, p->cp);
447 }
448
449 /* 3DSTATE_SF */
450 if (DIRTY(RASTERIZER) || DIRTY(FRAMEBUFFER)) {
451 gen7_wa_pipe_control_cs_stall(p, true, true);
452 p->gen7_3DSTATE_SF(p->dev, ilo->rasterizer, ilo->fb.state.zsbuf, p->cp);
453 }
454 }
455
456 static void
457 gen7_pipeline_wm(struct ilo_3d_pipeline *p,
458 const struct ilo_context *ilo,
459 struct gen6_pipeline_session *session)
460 {
461 /* 3DSTATE_WM */
462 if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DEPTH_STENCIL_ALPHA) ||
463 DIRTY(RASTERIZER)) {
464 const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
465 const bool cc_may_kill = (ilo->dsa->alpha.enabled ||
466 ilo->blend->alpha_to_coverage);
467
468 if (fs)
469 assert(!fs->pcb.clip_state_size);
470
471 if (p->dev->gen == ILO_GEN(7) && session->hw_ctx_changed)
472 gen7_wa_pipe_control_wm_max_threads_stall(p);
473
474 p->gen7_3DSTATE_WM(p->dev,
475 fs, &ilo->rasterizer->state, cc_may_kill, p->cp);
476 }
477
478 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
479 if (session->binding_table_fs_changed) {
480 p->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
481 p->state.wm.BINDING_TABLE_STATE, p->cp);
482 }
483
484 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
485 if (session->sampler_state_fs_changed) {
486 p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
487 p->state.wm.SAMPLER_STATE, p->cp);
488 }
489
490 /* 3DSTATE_CONSTANT_PS */
491 if (session->pcb_state_fs_changed)
492 p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
493
494 /* 3DSTATE_PS */
495 if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
496 DIRTY(BLEND) || session->kernel_bo_changed) {
497 const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
498 const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
499 const bool dual_blend = ilo->blend->dual_blend;
500
501 if (fs)
502 assert(!fs->pcb.clip_state_size);
503
504 p->gen7_3DSTATE_PS(p->dev, fs, num_samplers, dual_blend, p->cp);
505 }
506
507 /* 3DSTATE_SCISSOR_STATE_POINTERS */
508 if (session->scissor_state_changed) {
509 p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
510 p->state.SCISSOR_RECT, p->cp);
511 }
512
513 /* XXX what is the best way to know if this workaround is needed? */
514 {
515 const bool emit_3dstate_ps = (DIRTY(FS) ||
516 DIRTY(FRAGMENT_SAMPLERS) ||
517 DIRTY(BLEND));
518 const bool emit_3dstate_depth_buffer =
519 (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
520 session->state_bo_changed);
521
522 if (emit_3dstate_ps ||
523 emit_3dstate_depth_buffer ||
524 session->pcb_state_fs_changed ||
525 session->viewport_state_changed ||
526 session->binding_table_fs_changed ||
527 session->sampler_state_fs_changed ||
528 session->cc_state_cc_changed ||
529 session->cc_state_blend_changed ||
530 session->cc_state_dsa_changed)
531 gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
532 }
533
534 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
535 if (DIRTY(FRAMEBUFFER) || session->batch_bo_changed) {
536 const struct ilo_zs_surface *zs;
537
538 if (ilo->fb.state.zsbuf) {
539 const struct ilo_surface_cso *surface =
540 (const struct ilo_surface_cso *) ilo->fb.state.zsbuf;
541
542 assert(!surface->is_rt);
543 zs = &surface->u.zs;
544 }
545 else {
546 zs = &ilo->fb.null_zs;
547 }
548
549 p->gen7_3DSTATE_DEPTH_BUFFER(p->dev, zs, p->cp);
550 p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev, zs, p->cp);
551 p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, zs, p->cp);
552
553 /* TODO */
554 p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
555 }
556 }
557
558 static void
559 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
560 const struct ilo_context *ilo,
561 struct gen6_pipeline_session *session)
562 {
563 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
564 if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
565 const uint32_t *packed_sample_pos;
566
567 gen7_wa_pipe_control_cs_stall(p, true, true);
568
569 packed_sample_pos =
570 (ilo->fb.num_samples > 4) ? p->packed_sample_position_8x :
571 (ilo->fb.num_samples > 1) ? &p->packed_sample_position_4x :
572 &p->packed_sample_position_1x;
573
574 p->gen6_3DSTATE_MULTISAMPLE(p->dev,
575 ilo->fb.num_samples, packed_sample_pos,
576 ilo->rasterizer->state.half_pixel_center, p->cp);
577
578 p->gen7_3DSTATE_SAMPLE_MASK(p->dev,
579 (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1,
580 ilo->fb.num_samples, p->cp);
581 }
582 }
583
584 static void
585 gen7_pipeline_commands(struct ilo_3d_pipeline *p,
586 const struct ilo_context *ilo,
587 struct gen6_pipeline_session *session)
588 {
589 /*
590 * We try to keep the order of the commands match, as closely as possible,
591 * that of the classic i965 driver. It allows us to compare the command
592 * streams easily.
593 */
594 gen6_pipeline_common_select(p, ilo, session);
595 gen6_pipeline_common_sip(p, ilo, session);
596 gen6_pipeline_vf_statistics(p, ilo, session);
597 gen7_pipeline_common_pcb_alloc(p, ilo, session);
598 gen6_pipeline_common_base_address(p, ilo, session);
599 gen7_pipeline_common_pointers_1(p, ilo, session);
600 gen7_pipeline_common_urb(p, ilo, session);
601 gen7_pipeline_common_pointers_2(p, ilo, session);
602 gen7_pipeline_wm_multisample(p, ilo, session);
603 gen7_pipeline_gs(p, ilo, session);
604 gen7_pipeline_hs(p, ilo, session);
605 gen7_pipeline_te(p, ilo, session);
606 gen7_pipeline_ds(p, ilo, session);
607 gen7_pipeline_vs(p, ilo, session);
608 gen7_pipeline_sol(p, ilo, session);
609 gen6_pipeline_clip(p, ilo, session);
610 gen7_pipeline_sf(p, ilo, session);
611 gen7_pipeline_wm(p, ilo, session);
612 gen6_pipeline_wm_raster(p, ilo, session);
613 gen6_pipeline_sf_rect(p, ilo, session);
614 gen6_pipeline_vf(p, ilo, session);
615 gen6_pipeline_vf_draw(p, ilo, session);
616 }
617
618 static void
619 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline *p,
620 const struct ilo_context *ilo,
621 const struct pipe_draw_info *info)
622 {
623 struct gen6_pipeline_session session;
624
625 gen6_pipeline_prepare(p, ilo, info, &session);
626
627 session.emit_draw_states = gen6_pipeline_states;
628 session.emit_draw_commands = gen7_pipeline_commands;
629
630 gen6_pipeline_draw(p, ilo, &session);
631 gen6_pipeline_end(p, ilo, &session);
632 }
633
634 static int
635 gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
636 const struct ilo_gpe_gen7 *gen7,
637 const struct ilo_context *ilo)
638 {
639 static int size;
640 enum ilo_gpe_gen7_command cmd;
641
642 if (size)
643 return size;
644
645 for (cmd = 0; cmd < ILO_GPE_GEN7_COMMAND_COUNT; cmd++) {
646 int count;
647
648 switch (cmd) {
649 case ILO_GPE_GEN7_PIPE_CONTROL:
650 /* for the workaround */
651 count = 2;
652 /* another one after 3DSTATE_URB */
653 count += 1;
654 /* and another one after 3DSTATE_CONSTANT_VS */
655 count += 1;
656 break;
657 case ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS:
658 count = 33;
659 break;
660 case ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS:
661 count = 34;
662 break;
663 case ILO_GPE_GEN7_MEDIA_VFE_STATE:
664 case ILO_GPE_GEN7_MEDIA_CURBE_LOAD:
665 case ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD:
666 case ILO_GPE_GEN7_MEDIA_STATE_FLUSH:
667 case ILO_GPE_GEN7_GPGPU_WALKER:
668 /* media commands */
669 count = 0;
670 break;
671 default:
672 count = 1;
673 break;
674 }
675
676 if (count) {
677 size += gen7->estimate_command_size(p->dev,
678 cmd, count);
679 }
680 }
681
682 return size;
683 }
684
685 static int
686 gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
687 const struct ilo_gpe_gen7 *gen7,
688 const struct ilo_context *ilo)
689 {
690 static int static_size;
691 int shader_type, count, size;
692
693 if (!static_size) {
694 struct {
695 enum ilo_gpe_gen7_state state;
696 int count;
697 } static_states[] = {
698 /* viewports */
699 { ILO_GPE_GEN7_SF_CLIP_VIEWPORT, 1 },
700 { ILO_GPE_GEN7_CC_VIEWPORT, 1 },
701 /* cc */
702 { ILO_GPE_GEN7_COLOR_CALC_STATE, 1 },
703 { ILO_GPE_GEN7_BLEND_STATE, ILO_MAX_DRAW_BUFFERS },
704 { ILO_GPE_GEN7_DEPTH_STENCIL_STATE, 1 },
705 /* scissors */
706 { ILO_GPE_GEN7_SCISSOR_RECT, 1 },
707 /* binding table (vs, gs, fs) */
708 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_VS_SURFACES },
709 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_GS_SURFACES },
710 { ILO_GPE_GEN7_BINDING_TABLE_STATE, ILO_MAX_WM_SURFACES },
711 };
712 int i;
713
714 for (i = 0; i < Elements(static_states); i++) {
715 static_size += gen7->estimate_state_size(p->dev,
716 static_states[i].state,
717 static_states[i].count);
718 }
719 }
720
721 size = static_size;
722
723 /*
724 * render targets (fs)
725 * sampler views (vs, fs)
726 * constant buffers (vs, fs)
727 */
728 count = ilo->fb.state.nr_cbufs;
729 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
730 count += ilo->view[shader_type].count;
731 count += ilo->cbuf[shader_type].count;
732 }
733
734 if (count) {
735 size += gen7->estimate_state_size(p->dev,
736 ILO_GPE_GEN7_SURFACE_STATE, count);
737 }
738
739 /* samplers (vs, fs) */
740 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
741 count = ilo->sampler[shader_type].count;
742 if (count) {
743 size += gen7->estimate_state_size(p->dev,
744 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE, count);
745 size += gen7->estimate_state_size(p->dev,
746 ILO_GPE_GEN7_SAMPLER_STATE, count);
747 }
748 }
749
750 /* pcb (vs) */
751 if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
752 const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
753
754 size += gen7->estimate_state_size(p->dev,
755 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, pcb_size);
756 }
757
758 return size;
759 }
760
761 static int
762 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p,
763 enum ilo_3d_pipeline_action action,
764 const void *arg)
765 {
766 const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
767 int size;
768
769 switch (action) {
770 case ILO_3D_PIPELINE_DRAW:
771 {
772 const struct ilo_context *ilo = arg;
773
774 size = gen7_pipeline_estimate_commands(p, gen7, ilo) +
775 gen7_pipeline_estimate_states(p, gen7, ilo);
776 }
777 break;
778 case ILO_3D_PIPELINE_FLUSH:
779 case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
780 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
781 size = gen7->estimate_command_size(p->dev,
782 ILO_GPE_GEN7_PIPE_CONTROL, 1);
783 break;
784 default:
785 assert(!"unknown 3D pipeline action");
786 size = 0;
787 break;
788 }
789
790 return size;
791 }
792
793 void
794 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
795 {
796 const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
797
798 p->estimate_size = ilo_3d_pipeline_estimate_size_gen7;
799 p->emit_draw = ilo_3d_pipeline_emit_draw_gen7;
800 p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
801 p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
802 p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
803
804 #define GEN6_USE(p, name, from) \
805 p->gen6_ ## name = from->emit_ ## name
806 GEN6_USE(p, STATE_BASE_ADDRESS, gen7);
807 GEN6_USE(p, STATE_SIP, gen7);
808 GEN6_USE(p, PIPELINE_SELECT, gen7);
809 GEN6_USE(p, 3DSTATE_VERTEX_BUFFERS, gen7);
810 GEN6_USE(p, 3DSTATE_VERTEX_ELEMENTS, gen7);
811 GEN6_USE(p, 3DSTATE_INDEX_BUFFER, gen7);
812 GEN6_USE(p, 3DSTATE_VF_STATISTICS, gen7);
813 GEN6_USE(p, 3DSTATE_SCISSOR_STATE_POINTERS, gen7);
814 GEN6_USE(p, 3DSTATE_VS, gen7);
815 GEN6_USE(p, 3DSTATE_CLIP, gen7);
816 GEN6_USE(p, 3DSTATE_CONSTANT_VS, gen7);
817 GEN6_USE(p, 3DSTATE_CONSTANT_GS, gen7);
818 GEN6_USE(p, 3DSTATE_CONSTANT_PS, gen7);
819 GEN6_USE(p, 3DSTATE_DRAWING_RECTANGLE, gen7);
820 GEN6_USE(p, 3DSTATE_POLY_STIPPLE_OFFSET, gen7);
821 GEN6_USE(p, 3DSTATE_POLY_STIPPLE_PATTERN, gen7);
822 GEN6_USE(p, 3DSTATE_LINE_STIPPLE, gen7);
823 GEN6_USE(p, 3DSTATE_AA_LINE_PARAMETERS, gen7);
824 GEN6_USE(p, 3DSTATE_MULTISAMPLE, gen7);
825 GEN6_USE(p, 3DSTATE_STENCIL_BUFFER, gen7);
826 GEN6_USE(p, 3DSTATE_HIER_DEPTH_BUFFER, gen7);
827 GEN6_USE(p, 3DSTATE_CLEAR_PARAMS, gen7);
828 GEN6_USE(p, PIPE_CONTROL, gen7);
829 GEN6_USE(p, 3DPRIMITIVE, gen7);
830 GEN6_USE(p, INTERFACE_DESCRIPTOR_DATA, gen7);
831 GEN6_USE(p, CC_VIEWPORT, gen7);
832 GEN6_USE(p, COLOR_CALC_STATE, gen7);
833 GEN6_USE(p, BLEND_STATE, gen7);
834 GEN6_USE(p, DEPTH_STENCIL_STATE, gen7);
835 GEN6_USE(p, SCISSOR_RECT, gen7);
836 GEN6_USE(p, BINDING_TABLE_STATE, gen7);
837 GEN6_USE(p, SURFACE_STATE, gen7);
838 GEN6_USE(p, SAMPLER_STATE, gen7);
839 GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen7);
840 GEN6_USE(p, push_constant_buffer, gen7);
841 #undef GEN6_USE
842
843 #define GEN7_USE(p, name, from) \
844 p->gen7_ ## name = from->emit_ ## name
845 GEN7_USE(p, 3DSTATE_DEPTH_BUFFER, gen7);
846 GEN7_USE(p, 3DSTATE_CC_STATE_POINTERS, gen7);
847 GEN7_USE(p, 3DSTATE_GS, gen7);
848 GEN7_USE(p, 3DSTATE_SF, gen7);
849 GEN7_USE(p, 3DSTATE_WM, gen7);
850 GEN7_USE(p, 3DSTATE_SAMPLE_MASK, gen7);
851 GEN7_USE(p, 3DSTATE_CONSTANT_HS, gen7);
852 GEN7_USE(p, 3DSTATE_CONSTANT_DS, gen7);
853 GEN7_USE(p, 3DSTATE_HS, gen7);
854 GEN7_USE(p, 3DSTATE_TE, gen7);
855 GEN7_USE(p, 3DSTATE_DS, gen7);
856 GEN7_USE(p, 3DSTATE_STREAMOUT, gen7);
857 GEN7_USE(p, 3DSTATE_SBE, gen7);
858 GEN7_USE(p, 3DSTATE_PS, gen7);
859 GEN7_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, gen7);
860 GEN7_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS_CC, gen7);
861 GEN7_USE(p, 3DSTATE_BLEND_STATE_POINTERS, gen7);
862 GEN7_USE(p, 3DSTATE_DEPTH_STENCIL_STATE_POINTERS, gen7);
863 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_VS, gen7);
864 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_HS, gen7);
865 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_DS, gen7);
866 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_GS, gen7);
867 GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_PS, gen7);
868 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_VS, gen7);
869 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_HS, gen7);
870 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_DS, gen7);
871 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_GS, gen7);
872 GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_PS, gen7);
873 GEN7_USE(p, 3DSTATE_URB_VS, gen7);
874 GEN7_USE(p, 3DSTATE_URB_HS, gen7);
875 GEN7_USE(p, 3DSTATE_URB_DS, gen7);
876 GEN7_USE(p, 3DSTATE_URB_GS, gen7);
877 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_VS, gen7);
878 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_HS, gen7);
879 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, gen7);
880 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_GS, gen7);
881 GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_PS, gen7);
882 GEN7_USE(p, 3DSTATE_SO_DECL_LIST, gen7);
883 GEN7_USE(p, 3DSTATE_SO_BUFFER, gen7);
884 GEN7_USE(p, SF_CLIP_VIEWPORT, gen7);
885 #undef GEN7_USE
886 }