2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "util/u_dual_blend.h"
29 #include "intel_reg.h"
31 #include "ilo_common.h"
32 #include "ilo_context.h"
34 #include "ilo_gpe_gen7.h"
35 #include "ilo_shader.h"
36 #include "ilo_state.h"
37 #include "ilo_3d_pipeline.h"
38 #include "ilo_3d_pipeline_gen6.h"
39 #include "ilo_3d_pipeline_gen7.h"
42 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline
*p
,
43 bool change_multisample_state
,
44 bool change_depth_state
)
46 struct intel_bo
*bo
= NULL
;
47 uint32_t dw1
= PIPE_CONTROL_CS_STALL
;
49 assert(p
->dev
->gen
== ILO_GEN(7));
52 if (p
->state
.has_gen6_wa_pipe_control
)
54 p
->state
.has_gen6_wa_pipe_control
= true;
57 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
59 * "Due to an HW issue driver needs to send a pipe control with stall
60 * when ever there is state change in depth bias related state"
62 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
64 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
65 * in the ring after this instruction
66 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
68 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
70 * "Driver must ierarchi that all the caches in the depth pipe are
71 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
72 * requires driver to send a PIPE_CONTROL with a CS stall along with a
73 * Depth Flush prior to this command.
75 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
77 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
78 * a post sync operation prior to the group of depth
79 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
80 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
83 if (change_multisample_state
)
84 dw1
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
86 if (change_depth_state
) {
87 dw1
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
88 bo
= p
->workaround_bo
;
91 p
->gen6_PIPE_CONTROL(p
->dev
, dw1
, bo
, 0, false, p
->cp
);
95 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline
*p
)
97 assert(p
->dev
->gen
== ILO_GEN(7));
100 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
102 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
103 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
104 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
105 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
106 * needs to be sent before any combination of VS associated 3DSTATE."
108 p
->gen6_PIPE_CONTROL(p
->dev
,
109 PIPE_CONTROL_DEPTH_STALL
|
110 PIPE_CONTROL_WRITE_IMMEDIATE
,
111 p
->workaround_bo
, 0, false, p
->cp
);
115 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline
*p
,
116 bool change_depth_buffer
)
118 assert(p
->dev
->gen
== ILO_GEN(7));
121 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
123 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
124 * Enable bit set after all the following states are programmed:
127 * * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
128 * * 3DSTATE_CONSTANT_PS
129 * * 3DSTATE_BINDING_TABLE_POINTERS_PS
130 * * 3DSTATE_SAMPLER_STATE_POINTERS_PS
131 * * 3DSTATE_CC_STATE_POINTERS
132 * * 3DSTATE_BLEND_STATE_POINTERS
133 * * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
135 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
137 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
138 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
139 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
140 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
141 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
142 * Depth Flush Bit set, followed by another pipelined depth stall
143 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
144 * guarantee that the pipeline from WM onwards is already flushed
145 * (e.g., via a preceding MI_FLUSH)."
147 p
->gen6_PIPE_CONTROL(p
->dev
,
148 PIPE_CONTROL_DEPTH_STALL
,
149 NULL
, 0, false, p
->cp
);
151 if (!change_depth_buffer
)
154 p
->gen6_PIPE_CONTROL(p
->dev
,
155 PIPE_CONTROL_DEPTH_CACHE_FLUSH
,
156 NULL
, 0, false, p
->cp
);
158 p
->gen6_PIPE_CONTROL(p
->dev
,
159 PIPE_CONTROL_DEPTH_STALL
,
160 NULL
, 0, false, p
->cp
);
164 gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline
*p
)
166 assert(p
->dev
->gen
== ILO_GEN(7));
169 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
171 * "If this field (Maximum Number of Threads in 3DSTATE_WM) is changed
172 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
173 * Pixel Scoreboard set is required to be issued."
175 p
->gen6_PIPE_CONTROL(p
->dev
,
176 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
177 NULL
, 0, false, p
->cp
);
181 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
184 gen7_pipeline_common_urb(struct ilo_3d_pipeline
*p
,
185 const struct ilo_context
*ilo
,
186 struct gen6_pipeline_session
*session
)
188 /* 3DSTATE_URB_{VS,GS,HS,DS} */
189 if (DIRTY(VERTEX_ELEMENTS
) || DIRTY(VS
)) {
190 const struct ilo_shader
*vs
= (ilo
->vs
) ? ilo
->vs
->shader
: NULL
;
191 /* the first 16KB are reserved for VS and PS PCBs */
192 const int offset
= 16 * 1024;
193 int vs_entry_size
, vs_total_size
;
195 vs_entry_size
= (vs
) ? vs
->out
.count
: 0;
198 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
200 * "Programming Restriction: As the VS URB entry serves as both the
201 * per-vertex input and output of the VS shader, the VS URB
202 * Allocation Size must be sized to the maximum of the vertex input
203 * and output structures."
205 if (vs_entry_size
< ilo
->vertex_elements
->num_elements
)
206 vs_entry_size
= ilo
->vertex_elements
->num_elements
;
208 vs_entry_size
*= sizeof(float) * 4;
209 vs_total_size
= ilo
->dev
->urb_size
- offset
;
211 gen7_wa_pipe_control_vs_depth_stall(p
);
213 p
->gen7_3DSTATE_URB_VS(p
->dev
,
214 offset
, vs_total_size
, vs_entry_size
, p
->cp
);
216 p
->gen7_3DSTATE_URB_GS(p
->dev
, offset
, 0, 0, p
->cp
);
217 p
->gen7_3DSTATE_URB_HS(p
->dev
, offset
, 0, 0, p
->cp
);
218 p
->gen7_3DSTATE_URB_DS(p
->dev
, offset
, 0, 0, p
->cp
);
223 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline
*p
,
224 const struct ilo_context
*ilo
,
225 struct gen6_pipeline_session
*session
)
227 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
228 if (session
->hw_ctx_changed
) {
230 * push constant buffers are only allowed to take up at most the first
233 p
->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p
->dev
,
236 p
->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p
->dev
,
239 gen7_wa_pipe_control_cs_stall(p
, true, true);
244 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline
*p
,
245 const struct ilo_context
*ilo
,
246 struct gen6_pipeline_session
*session
)
248 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
249 if (session
->viewport_state_changed
) {
250 p
->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p
->dev
,
251 p
->state
.CC_VIEWPORT
, p
->cp
);
253 p
->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p
->dev
,
254 p
->state
.SF_CLIP_VIEWPORT
, p
->cp
);
259 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline
*p
,
260 const struct ilo_context
*ilo
,
261 struct gen6_pipeline_session
*session
)
263 /* 3DSTATE_BLEND_STATE_POINTERS */
264 if (session
->cc_state_blend_changed
) {
265 p
->gen7_3DSTATE_BLEND_STATE_POINTERS(p
->dev
,
266 p
->state
.BLEND_STATE
, p
->cp
);
269 /* 3DSTATE_CC_STATE_POINTERS */
270 if (session
->cc_state_cc_changed
) {
271 p
->gen7_3DSTATE_CC_STATE_POINTERS(p
->dev
,
272 p
->state
.COLOR_CALC_STATE
, p
->cp
);
275 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
276 if (session
->cc_state_dsa_changed
) {
277 p
->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p
->dev
,
278 p
->state
.DEPTH_STENCIL_STATE
, p
->cp
);
283 gen7_pipeline_vs(struct ilo_3d_pipeline
*p
,
284 const struct ilo_context
*ilo
,
285 struct gen6_pipeline_session
*session
)
287 const bool emit_3dstate_binding_table
= session
->binding_table_vs_changed
;
288 const bool emit_3dstate_sampler_state
= session
->sampler_state_vs_changed
;
289 /* see gen6_pipeline_vs() */
290 const bool emit_3dstate_constant_vs
= session
->pcb_state_vs_changed
;
291 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(VERTEX_SAMPLERS
));
293 /* emit depth stall before any of the VS commands */
294 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
295 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
296 gen7_wa_pipe_control_vs_depth_stall(p
);
298 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
299 if (emit_3dstate_binding_table
) {
300 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p
->dev
,
301 p
->state
.vs
.BINDING_TABLE_STATE
, p
->cp
);
304 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
305 if (emit_3dstate_sampler_state
) {
306 p
->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p
->dev
,
307 p
->state
.vs
.SAMPLER_STATE
, p
->cp
);
310 gen6_pipeline_vs(p
, ilo
, session
);
314 gen7_pipeline_hs(struct ilo_3d_pipeline
*p
,
315 const struct ilo_context
*ilo
,
316 struct gen6_pipeline_session
*session
)
318 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
319 if (session
->hw_ctx_changed
) {
320 p
->gen7_3DSTATE_CONSTANT_HS(p
->dev
, 0, 0, 0, p
->cp
);
321 p
->gen7_3DSTATE_HS(p
->dev
, NULL
, 0, 0, p
->cp
);
324 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
325 if (session
->hw_ctx_changed
)
326 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p
->dev
, 0, p
->cp
);
330 gen7_pipeline_te(struct ilo_3d_pipeline
*p
,
331 const struct ilo_context
*ilo
,
332 struct gen6_pipeline_session
*session
)
335 if (session
->hw_ctx_changed
)
336 p
->gen7_3DSTATE_TE(p
->dev
, p
->cp
);
340 gen7_pipeline_ds(struct ilo_3d_pipeline
*p
,
341 const struct ilo_context
*ilo
,
342 struct gen6_pipeline_session
*session
)
344 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
345 if (session
->hw_ctx_changed
) {
346 p
->gen7_3DSTATE_CONSTANT_DS(p
->dev
, 0, 0, 0, p
->cp
);
347 p
->gen7_3DSTATE_DS(p
->dev
, NULL
, 0, 0, p
->cp
);
350 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
351 if (session
->hw_ctx_changed
)
352 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p
->dev
, 0, p
->cp
);
357 gen7_pipeline_gs(struct ilo_3d_pipeline
*p
,
358 const struct ilo_context
*ilo
,
359 struct gen6_pipeline_session
*session
)
361 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
362 if (session
->hw_ctx_changed
) {
363 p
->gen6_3DSTATE_CONSTANT_GS(p
->dev
, 0, 0, 0, p
->cp
);
364 p
->gen7_3DSTATE_GS(p
->dev
, NULL
, 0, p
->cp
);
367 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
368 if (session
->binding_table_gs_changed
) {
369 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p
->dev
,
370 p
->state
.gs
.BINDING_TABLE_STATE
, p
->cp
);
375 gen7_pipeline_sol(struct ilo_3d_pipeline
*p
,
376 const struct ilo_context
*ilo
,
377 struct gen6_pipeline_session
*session
)
379 const struct pipe_stream_output_info
*so_info
;
380 const struct ilo_shader
*sh
;
381 bool dirty_sh
= false;
384 so_info
= &ilo
->gs
->info
.stream_output
;
385 sh
= ilo
->gs
->shader
;
386 dirty_sh
= DIRTY(GS
);
389 so_info
= &ilo
->vs
->info
.stream_output
;
390 sh
= ilo
->vs
->shader
;
391 dirty_sh
= DIRTY(VS
);
394 gen6_pipeline_update_max_svbi(p
, ilo
, session
);
396 /* 3DSTATE_SO_BUFFER */
397 if (DIRTY(STREAM_OUTPUT_TARGETS
) || dirty_sh
) {
400 for (i
= 0; i
< ilo
->stream_output_targets
.num_targets
; i
++) {
401 const int stride
= so_info
->stride
[i
] * 4; /* in bytes */
404 /* reset HW write offsets and offset buffer base */
405 if (!p
->cp
->hw_ctx
) {
406 ilo_cp_set_one_off_flags(p
->cp
, INTEL_EXEC_GEN7_SOL_RESET
);
407 base
+= p
->state
.so_num_vertices
* stride
;
410 p
->gen7_3DSTATE_SO_BUFFER(p
->dev
, i
, base
, stride
,
411 ilo
->stream_output_targets
.targets
[i
], p
->cp
);
415 p
->gen7_3DSTATE_SO_BUFFER(p
->dev
, i
, 0, 0, NULL
, p
->cp
);
418 /* 3DSTATE_SO_DECL_LIST */
420 p
->gen7_3DSTATE_SO_DECL_LIST(p
->dev
, so_info
, sh
, p
->cp
);
422 /* 3DSTATE_STREAMOUT */
423 if (DIRTY(STREAM_OUTPUT_TARGETS
) || DIRTY(RASTERIZER
) || dirty_sh
) {
424 const unsigned buffer_mask
=
425 (1 << ilo
->stream_output_targets
.num_targets
) - 1;
427 p
->gen7_3DSTATE_STREAMOUT(p
->dev
, buffer_mask
, sh
->out
.count
,
428 ilo
->rasterizer
->rasterizer_discard
, p
->cp
);
433 gen7_pipeline_sf(struct ilo_3d_pipeline
*p
,
434 const struct ilo_context
*ilo
,
435 struct gen6_pipeline_session
*session
)
438 if (DIRTY(RASTERIZER
) || DIRTY(VS
) || DIRTY(GS
) || DIRTY(FS
)) {
439 const struct ilo_shader
*fs
= (ilo
->fs
)? ilo
->fs
->shader
: NULL
;
440 const struct ilo_shader
*last_sh
=
441 (ilo
->gs
)? ilo
->gs
->shader
:
442 (ilo
->vs
)? ilo
->vs
->shader
: NULL
;
444 p
->gen7_3DSTATE_SBE(p
->dev
,
445 ilo
->rasterizer
, fs
, last_sh
, p
->cp
);
449 if (DIRTY(RASTERIZER
) || DIRTY(FRAMEBUFFER
)) {
450 gen7_wa_pipe_control_cs_stall(p
, true, true);
452 p
->gen7_3DSTATE_SF(p
->dev
,
453 ilo
->rasterizer
, ilo
->framebuffer
.zsbuf
, p
->cp
);
458 gen7_pipeline_wm(struct ilo_3d_pipeline
*p
,
459 const struct ilo_context
*ilo
,
460 struct gen6_pipeline_session
*session
)
463 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DEPTH_STENCIL_ALPHA
) ||
465 const struct ilo_shader
*fs
= (ilo
->fs
)? ilo
->fs
->shader
: NULL
;
466 const bool cc_may_kill
= (ilo
->depth_stencil_alpha
->alpha
.enabled
||
467 ilo
->blend
->alpha_to_coverage
);
470 assert(!fs
->pcb
.clip_state_size
);
472 if (p
->dev
->gen
== ILO_GEN(7) && session
->hw_ctx_changed
)
473 gen7_wa_pipe_control_wm_max_threads_stall(p
);
475 p
->gen7_3DSTATE_WM(p
->dev
,
476 fs
, ilo
->rasterizer
, cc_may_kill
, p
->cp
);
479 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
480 if (session
->binding_table_fs_changed
) {
481 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p
->dev
,
482 p
->state
.wm
.BINDING_TABLE_STATE
, p
->cp
);
485 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
486 if (session
->sampler_state_fs_changed
) {
487 p
->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p
->dev
,
488 p
->state
.wm
.SAMPLER_STATE
, p
->cp
);
491 /* 3DSTATE_CONSTANT_PS */
492 if (session
->pcb_state_fs_changed
)
493 p
->gen6_3DSTATE_CONSTANT_PS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
496 if (DIRTY(FS
) || DIRTY(FRAGMENT_SAMPLERS
) ||
498 const struct ilo_shader
*fs
= (ilo
->fs
)? ilo
->fs
->shader
: NULL
;
499 const int num_samplers
=
500 ilo
->samplers
[PIPE_SHADER_FRAGMENT
].num_samplers
;
501 const bool dual_blend
= (!ilo
->blend
->logicop_enable
&&
502 ilo
->blend
->rt
[0].blend_enable
&&
503 util_blend_state_is_dual(ilo
->blend
, 0));
506 assert(!fs
->pcb
.clip_state_size
);
508 p
->gen7_3DSTATE_PS(p
->dev
, fs
, num_samplers
, dual_blend
, p
->cp
);
511 /* 3DSTATE_SCISSOR_STATE_POINTERS */
512 if (session
->scissor_state_changed
) {
513 p
->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p
->dev
,
514 p
->state
.SCISSOR_RECT
, p
->cp
);
517 /* XXX what is the best way to know if this workaround is needed? */
519 const bool emit_3dstate_ps
= (DIRTY(FS
) ||
520 DIRTY(FRAGMENT_SAMPLERS
) ||
522 const bool emit_3dstate_depth_buffer
=
523 (DIRTY(FRAMEBUFFER
) || DIRTY(DEPTH_STENCIL_ALPHA
) ||
524 session
->state_bo_changed
);
526 if (emit_3dstate_ps
||
527 emit_3dstate_depth_buffer
||
528 session
->pcb_state_fs_changed
||
529 session
->viewport_state_changed
||
530 session
->binding_table_fs_changed
||
531 session
->sampler_state_fs_changed
||
532 session
->cc_state_cc_changed
||
533 session
->cc_state_blend_changed
||
534 session
->cc_state_dsa_changed
)
535 gen7_wa_pipe_control_wm_depth_stall(p
, emit_3dstate_depth_buffer
);
539 * glCopyPixels() with GL_DEPTH, which flushes the context before copying
540 * the depth buffer to a temporary texture, could not update the depth
541 * buffer _sometimes_. Reissuing 3DSTATE_DEPTH_BUFFER in the new batch
542 * makes the problem gone.
545 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
546 if (DIRTY(FRAMEBUFFER
) || DIRTY(DEPTH_STENCIL_ALPHA
) ||
547 session
->state_bo_changed
) {
548 const bool hiz
= false;
550 p
->gen7_3DSTATE_DEPTH_BUFFER(p
->dev
,
551 ilo
->framebuffer
.zsbuf
,
552 ilo
->depth_stencil_alpha
,
555 p
->gen6_3DSTATE_HIER_DEPTH_BUFFER(p
->dev
,
556 (hiz
) ? ilo
->framebuffer
.zsbuf
: NULL
, p
->cp
);
558 p
->gen6_3DSTATE_STENCIL_BUFFER(p
->dev
, ilo
->framebuffer
.zsbuf
, p
->cp
);
561 p
->gen6_3DSTATE_CLEAR_PARAMS(p
->dev
, 0, p
->cp
);
566 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline
*p
,
567 const struct ilo_context
*ilo
,
568 struct gen6_pipeline_session
*session
)
570 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
571 if (DIRTY(SAMPLE_MASK
) || DIRTY(FRAMEBUFFER
)) {
572 const uint32_t *packed_sample_pos
;
575 gen7_wa_pipe_control_cs_stall(p
, true, true);
577 if (ilo
->framebuffer
.nr_cbufs
)
578 num_samples
= ilo
->framebuffer
.cbufs
[0]->texture
->nr_samples
;
581 (num_samples
> 4) ? p
->packed_sample_position_8x
:
582 (num_samples
> 1) ? &p
->packed_sample_position_4x
:
583 &p
->packed_sample_position_1x
;
585 p
->gen6_3DSTATE_MULTISAMPLE(p
->dev
, num_samples
, packed_sample_pos
,
586 ilo
->rasterizer
->half_pixel_center
, p
->cp
);
588 p
->gen7_3DSTATE_SAMPLE_MASK(p
->dev
,
589 (num_samples
> 1) ? ilo
->sample_mask
: 0x1,
595 gen7_pipeline_commands(struct ilo_3d_pipeline
*p
,
596 const struct ilo_context
*ilo
,
597 struct gen6_pipeline_session
*session
)
600 * We try to keep the order of the commands match, as closely as possible,
601 * that of the classic i965 driver. It allows us to compare the command
604 gen6_pipeline_common_select(p
, ilo
, session
);
605 gen6_pipeline_common_sip(p
, ilo
, session
);
606 gen6_pipeline_vf_statistics(p
, ilo
, session
);
607 gen7_pipeline_common_pcb_alloc(p
, ilo
, session
);
608 gen6_pipeline_common_base_address(p
, ilo
, session
);
609 gen7_pipeline_common_pointers_1(p
, ilo
, session
);
610 gen7_pipeline_common_urb(p
, ilo
, session
);
611 gen7_pipeline_common_pointers_2(p
, ilo
, session
);
612 gen7_pipeline_wm_multisample(p
, ilo
, session
);
613 gen7_pipeline_gs(p
, ilo
, session
);
614 gen7_pipeline_hs(p
, ilo
, session
);
615 gen7_pipeline_te(p
, ilo
, session
);
616 gen7_pipeline_ds(p
, ilo
, session
);
617 gen7_pipeline_vs(p
, ilo
, session
);
618 gen7_pipeline_sol(p
, ilo
, session
);
619 gen6_pipeline_clip(p
, ilo
, session
);
620 gen7_pipeline_sf(p
, ilo
, session
);
621 gen7_pipeline_wm(p
, ilo
, session
);
622 gen6_pipeline_wm_raster(p
, ilo
, session
);
623 gen6_pipeline_sf_rect(p
, ilo
, session
);
624 gen6_pipeline_vf(p
, ilo
, session
);
625 gen6_pipeline_vf_draw(p
, ilo
, session
);
629 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline
*p
,
630 const struct ilo_context
*ilo
,
631 const struct pipe_draw_info
*info
)
633 struct gen6_pipeline_session session
;
635 gen6_pipeline_prepare(p
, ilo
, info
, &session
);
637 session
.emit_draw_states
= gen6_pipeline_states
;
638 session
.emit_draw_commands
= gen7_pipeline_commands
;
640 gen6_pipeline_draw(p
, ilo
, &session
);
641 gen6_pipeline_end(p
, ilo
, &session
);
645 gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline
*p
,
646 const struct ilo_gpe_gen7
*gen7
,
647 const struct ilo_context
*ilo
)
650 enum ilo_gpe_gen7_command cmd
;
655 for (cmd
= 0; cmd
< ILO_GPE_GEN7_COMMAND_COUNT
; cmd
++) {
659 case ILO_GPE_GEN7_PIPE_CONTROL
:
660 /* for the workaround */
662 /* another one after 3DSTATE_URB */
664 /* and another one after 3DSTATE_CONSTANT_VS */
667 case ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS
:
670 case ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS
:
673 case ILO_GPE_GEN7_MEDIA_VFE_STATE
:
674 case ILO_GPE_GEN7_MEDIA_CURBE_LOAD
:
675 case ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD
:
676 case ILO_GPE_GEN7_MEDIA_STATE_FLUSH
:
677 case ILO_GPE_GEN7_GPGPU_WALKER
:
687 size
+= gen7
->estimate_command_size(p
->dev
,
696 gen7_pipeline_estimate_states(const struct ilo_3d_pipeline
*p
,
697 const struct ilo_gpe_gen7
*gen7
,
698 const struct ilo_context
*ilo
)
700 static int static_size
;
701 int shader_type
, count
, size
;
705 enum ilo_gpe_gen7_state state
;
707 } static_states
[] = {
709 { ILO_GPE_GEN7_SF_CLIP_VIEWPORT
, 1 },
710 { ILO_GPE_GEN7_CC_VIEWPORT
, 1 },
712 { ILO_GPE_GEN7_COLOR_CALC_STATE
, 1 },
713 { ILO_GPE_GEN7_BLEND_STATE
, ILO_MAX_DRAW_BUFFERS
},
714 { ILO_GPE_GEN7_DEPTH_STENCIL_STATE
, 1 },
716 { ILO_GPE_GEN7_SCISSOR_RECT
, 1 },
717 /* binding table (vs, gs, fs) */
718 { ILO_GPE_GEN7_BINDING_TABLE_STATE
, ILO_MAX_VS_SURFACES
},
719 { ILO_GPE_GEN7_BINDING_TABLE_STATE
, ILO_MAX_GS_SURFACES
},
720 { ILO_GPE_GEN7_BINDING_TABLE_STATE
, ILO_MAX_WM_SURFACES
},
724 for (i
= 0; i
< Elements(static_states
); i
++) {
725 static_size
+= gen7
->estimate_state_size(p
->dev
,
726 static_states
[i
].state
,
727 static_states
[i
].count
);
734 * render targets (fs)
735 * sampler views (vs, fs)
736 * constant buffers (vs, fs)
738 count
= ilo
->framebuffer
.nr_cbufs
;
739 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
740 count
+= ilo
->sampler_views
[shader_type
].num_views
;
741 count
+= ilo
->constant_buffers
[shader_type
].num_buffers
;
745 size
+= gen7
->estimate_state_size(p
->dev
,
746 ILO_GPE_GEN7_SURFACE_STATE
, count
);
749 /* samplers (vs, fs) */
750 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
751 count
= ilo
->samplers
[shader_type
].num_samplers
;
753 size
+= gen7
->estimate_state_size(p
->dev
,
754 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE
, count
);
755 size
+= gen7
->estimate_state_size(p
->dev
,
756 ILO_GPE_GEN7_SAMPLER_STATE
, count
);
761 if (ilo
->vs
&& ilo
->vs
->shader
->pcb
.clip_state_size
) {
762 const int pcb_size
= ilo
->vs
->shader
->pcb
.clip_state_size
;
764 size
+= gen7
->estimate_state_size(p
->dev
,
765 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER
, pcb_size
);
772 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline
*p
,
773 enum ilo_3d_pipeline_action action
,
776 const struct ilo_gpe_gen7
*gen7
= ilo_gpe_gen7_get();
780 case ILO_3D_PIPELINE_DRAW
:
782 const struct ilo_context
*ilo
= arg
;
784 size
= gen7_pipeline_estimate_commands(p
, gen7
, ilo
) +
785 gen7_pipeline_estimate_states(p
, gen7
, ilo
);
788 case ILO_3D_PIPELINE_FLUSH
:
789 case ILO_3D_PIPELINE_WRITE_TIMESTAMP
:
790 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT
:
791 size
= gen7
->estimate_command_size(p
->dev
,
792 ILO_GPE_GEN7_PIPE_CONTROL
, 1);
795 assert(!"unknown 3D pipeline action");
804 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline
*p
)
806 const struct ilo_gpe_gen7
*gen7
= ilo_gpe_gen7_get();
808 p
->estimate_size
= ilo_3d_pipeline_estimate_size_gen7
;
809 p
->emit_draw
= ilo_3d_pipeline_emit_draw_gen7
;
810 p
->emit_flush
= ilo_3d_pipeline_emit_flush_gen6
;
811 p
->emit_write_timestamp
= ilo_3d_pipeline_emit_write_timestamp_gen6
;
812 p
->emit_write_depth_count
= ilo_3d_pipeline_emit_write_depth_count_gen6
;
814 #define GEN6_USE(p, name, from) \
815 p->gen6_ ## name = from->emit_ ## name
816 GEN6_USE(p
, STATE_BASE_ADDRESS
, gen7
);
817 GEN6_USE(p
, STATE_SIP
, gen7
);
818 GEN6_USE(p
, PIPELINE_SELECT
, gen7
);
819 GEN6_USE(p
, 3DSTATE_VERTEX_BUFFERS
, gen7
);
820 GEN6_USE(p
, 3DSTATE_VERTEX_ELEMENTS
, gen7
);
821 GEN6_USE(p
, 3DSTATE_INDEX_BUFFER
, gen7
);
822 GEN6_USE(p
, 3DSTATE_VF_STATISTICS
, gen7
);
823 GEN6_USE(p
, 3DSTATE_SCISSOR_STATE_POINTERS
, gen7
);
824 GEN6_USE(p
, 3DSTATE_VS
, gen7
);
825 GEN6_USE(p
, 3DSTATE_CLIP
, gen7
);
826 GEN6_USE(p
, 3DSTATE_CONSTANT_VS
, gen7
);
827 GEN6_USE(p
, 3DSTATE_CONSTANT_GS
, gen7
);
828 GEN6_USE(p
, 3DSTATE_CONSTANT_PS
, gen7
);
829 GEN6_USE(p
, 3DSTATE_DRAWING_RECTANGLE
, gen7
);
830 GEN6_USE(p
, 3DSTATE_POLY_STIPPLE_OFFSET
, gen7
);
831 GEN6_USE(p
, 3DSTATE_POLY_STIPPLE_PATTERN
, gen7
);
832 GEN6_USE(p
, 3DSTATE_LINE_STIPPLE
, gen7
);
833 GEN6_USE(p
, 3DSTATE_AA_LINE_PARAMETERS
, gen7
);
834 GEN6_USE(p
, 3DSTATE_MULTISAMPLE
, gen7
);
835 GEN6_USE(p
, 3DSTATE_STENCIL_BUFFER
, gen7
);
836 GEN6_USE(p
, 3DSTATE_HIER_DEPTH_BUFFER
, gen7
);
837 GEN6_USE(p
, 3DSTATE_CLEAR_PARAMS
, gen7
);
838 GEN6_USE(p
, PIPE_CONTROL
, gen7
);
839 GEN6_USE(p
, 3DPRIMITIVE
, gen7
);
840 GEN6_USE(p
, INTERFACE_DESCRIPTOR_DATA
, gen7
);
841 GEN6_USE(p
, CC_VIEWPORT
, gen7
);
842 GEN6_USE(p
, COLOR_CALC_STATE
, gen7
);
843 GEN6_USE(p
, BLEND_STATE
, gen7
);
844 GEN6_USE(p
, DEPTH_STENCIL_STATE
, gen7
);
845 GEN6_USE(p
, SCISSOR_RECT
, gen7
);
846 GEN6_USE(p
, BINDING_TABLE_STATE
, gen7
);
847 GEN6_USE(p
, surf_SURFACE_STATE
, gen7
);
848 GEN6_USE(p
, view_SURFACE_STATE
, gen7
);
849 GEN6_USE(p
, cbuf_SURFACE_STATE
, gen7
);
850 GEN6_USE(p
, SAMPLER_STATE
, gen7
);
851 GEN6_USE(p
, SAMPLER_BORDER_COLOR_STATE
, gen7
);
852 GEN6_USE(p
, push_constant_buffer
, gen7
);
855 #define GEN7_USE(p, name, from) \
856 p->gen7_ ## name = from->emit_ ## name
857 GEN7_USE(p
, 3DSTATE_DEPTH_BUFFER
, gen7
);
858 GEN7_USE(p
, 3DSTATE_CC_STATE_POINTERS
, gen7
);
859 GEN7_USE(p
, 3DSTATE_GS
, gen7
);
860 GEN7_USE(p
, 3DSTATE_SF
, gen7
);
861 GEN7_USE(p
, 3DSTATE_WM
, gen7
);
862 GEN7_USE(p
, 3DSTATE_SAMPLE_MASK
, gen7
);
863 GEN7_USE(p
, 3DSTATE_CONSTANT_HS
, gen7
);
864 GEN7_USE(p
, 3DSTATE_CONSTANT_DS
, gen7
);
865 GEN7_USE(p
, 3DSTATE_HS
, gen7
);
866 GEN7_USE(p
, 3DSTATE_TE
, gen7
);
867 GEN7_USE(p
, 3DSTATE_DS
, gen7
);
868 GEN7_USE(p
, 3DSTATE_STREAMOUT
, gen7
);
869 GEN7_USE(p
, 3DSTATE_SBE
, gen7
);
870 GEN7_USE(p
, 3DSTATE_PS
, gen7
);
871 GEN7_USE(p
, 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
, gen7
);
872 GEN7_USE(p
, 3DSTATE_VIEWPORT_STATE_POINTERS_CC
, gen7
);
873 GEN7_USE(p
, 3DSTATE_BLEND_STATE_POINTERS
, gen7
);
874 GEN7_USE(p
, 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
, gen7
);
875 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_VS
, gen7
);
876 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_HS
, gen7
);
877 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_DS
, gen7
);
878 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_GS
, gen7
);
879 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_PS
, gen7
);
880 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_VS
, gen7
);
881 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_HS
, gen7
);
882 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_DS
, gen7
);
883 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_GS
, gen7
);
884 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_PS
, gen7
);
885 GEN7_USE(p
, 3DSTATE_URB_VS
, gen7
);
886 GEN7_USE(p
, 3DSTATE_URB_HS
, gen7
);
887 GEN7_USE(p
, 3DSTATE_URB_DS
, gen7
);
888 GEN7_USE(p
, 3DSTATE_URB_GS
, gen7
);
889 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_VS
, gen7
);
890 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_HS
, gen7
);
891 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_DS
, gen7
);
892 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_GS
, gen7
);
893 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_PS
, gen7
);
894 GEN7_USE(p
, 3DSTATE_SO_DECL_LIST
, gen7
);
895 GEN7_USE(p
, 3DSTATE_SO_BUFFER
, gen7
);
896 GEN7_USE(p
, SF_CLIP_VIEWPORT
, gen7
);