2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "util/u_dual_blend.h"
29 #include "intel_reg.h"
31 #include "shader/ilo_shader_internal.h"
32 #include "ilo_common.h"
33 #include "ilo_context.h"
35 #include "ilo_gpe_gen7.h"
36 #include "ilo_shader.h"
37 #include "ilo_state.h"
38 #include "ilo_3d_pipeline.h"
39 #include "ilo_3d_pipeline_gen6.h"
40 #include "ilo_3d_pipeline_gen7.h"
43 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline
*p
,
44 bool change_multisample_state
,
45 bool change_depth_state
)
47 struct intel_bo
*bo
= NULL
;
48 uint32_t dw1
= PIPE_CONTROL_CS_STALL
;
50 assert(p
->dev
->gen
== ILO_GEN(7));
53 if (p
->state
.has_gen6_wa_pipe_control
)
55 p
->state
.has_gen6_wa_pipe_control
= true;
58 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
60 * "Due to an HW issue driver needs to send a pipe control with stall
61 * when ever there is state change in depth bias related state"
63 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
65 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
66 * in the ring after this instruction
67 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
69 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
71 * "Driver must ierarchi that all the caches in the depth pipe are
72 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
73 * requires driver to send a PIPE_CONTROL with a CS stall along with a
74 * Depth Flush prior to this command.
76 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
78 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
79 * a post sync operation prior to the group of depth
80 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
81 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
84 if (change_multisample_state
)
85 dw1
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
87 if (change_depth_state
) {
88 dw1
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
89 bo
= p
->workaround_bo
;
92 p
->gen6_PIPE_CONTROL(p
->dev
, dw1
, bo
, 0, false, p
->cp
);
96 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline
*p
)
98 assert(p
->dev
->gen
== ILO_GEN(7));
101 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
103 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
104 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
105 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
106 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
107 * needs to be sent before any combination of VS associated 3DSTATE."
109 p
->gen6_PIPE_CONTROL(p
->dev
,
110 PIPE_CONTROL_DEPTH_STALL
|
111 PIPE_CONTROL_WRITE_IMMEDIATE
,
112 p
->workaround_bo
, 0, false, p
->cp
);
116 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline
*p
,
117 bool change_depth_buffer
)
119 assert(p
->dev
->gen
== ILO_GEN(7));
122 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
124 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
125 * Enable bit set after all the following states are programmed:
128 * * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
129 * * 3DSTATE_CONSTANT_PS
130 * * 3DSTATE_BINDING_TABLE_POINTERS_PS
131 * * 3DSTATE_SAMPLER_STATE_POINTERS_PS
132 * * 3DSTATE_CC_STATE_POINTERS
133 * * 3DSTATE_BLEND_STATE_POINTERS
134 * * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
136 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
138 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
139 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
140 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
141 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
142 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
143 * Depth Flush Bit set, followed by another pipelined depth stall
144 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
145 * guarantee that the pipeline from WM onwards is already flushed
146 * (e.g., via a preceding MI_FLUSH)."
148 p
->gen6_PIPE_CONTROL(p
->dev
,
149 PIPE_CONTROL_DEPTH_STALL
,
150 NULL
, 0, false, p
->cp
);
152 if (!change_depth_buffer
)
155 p
->gen6_PIPE_CONTROL(p
->dev
,
156 PIPE_CONTROL_DEPTH_CACHE_FLUSH
,
157 NULL
, 0, false, p
->cp
);
159 p
->gen6_PIPE_CONTROL(p
->dev
,
160 PIPE_CONTROL_DEPTH_STALL
,
161 NULL
, 0, false, p
->cp
);
165 gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline
*p
)
167 assert(p
->dev
->gen
== ILO_GEN(7));
170 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
172 * "If this field (Maximum Number of Threads in 3DSTATE_WM) is changed
173 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
174 * Pixel Scoreboard set is required to be issued."
176 p
->gen6_PIPE_CONTROL(p
->dev
,
177 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
178 NULL
, 0, false, p
->cp
);
182 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
185 gen7_pipeline_common_urb(struct ilo_3d_pipeline
*p
,
186 const struct ilo_context
*ilo
,
187 struct gen6_pipeline_session
*session
)
189 /* 3DSTATE_URB_{VS,GS,HS,DS} */
190 if (DIRTY(VERTEX_ELEMENTS
) || DIRTY(VS
)) {
191 const struct ilo_shader
*vs
= (ilo
->vs
) ? ilo
->vs
->shader
: NULL
;
192 /* the first 16KB are reserved for VS and PS PCBs */
193 const int offset
= 16 * 1024;
194 int vs_entry_size
, vs_total_size
;
196 vs_entry_size
= (vs
) ? vs
->out
.count
: 0;
199 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
201 * "Programming Restriction: As the VS URB entry serves as both the
202 * per-vertex input and output of the VS shader, the VS URB
203 * Allocation Size must be sized to the maximum of the vertex input
204 * and output structures."
206 if (vs_entry_size
< ilo
->ve
->count
)
207 vs_entry_size
= ilo
->ve
->count
;
209 vs_entry_size
*= sizeof(float) * 4;
210 vs_total_size
= ilo
->dev
->urb_size
- offset
;
212 gen7_wa_pipe_control_vs_depth_stall(p
);
214 p
->gen7_3DSTATE_URB_VS(p
->dev
,
215 offset
, vs_total_size
, vs_entry_size
, p
->cp
);
217 p
->gen7_3DSTATE_URB_GS(p
->dev
, offset
, 0, 0, p
->cp
);
218 p
->gen7_3DSTATE_URB_HS(p
->dev
, offset
, 0, 0, p
->cp
);
219 p
->gen7_3DSTATE_URB_DS(p
->dev
, offset
, 0, 0, p
->cp
);
224 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline
*p
,
225 const struct ilo_context
*ilo
,
226 struct gen6_pipeline_session
*session
)
228 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
229 if (session
->hw_ctx_changed
) {
231 * push constant buffers are only allowed to take up at most the first
234 p
->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p
->dev
,
237 p
->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p
->dev
,
240 gen7_wa_pipe_control_cs_stall(p
, true, true);
245 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline
*p
,
246 const struct ilo_context
*ilo
,
247 struct gen6_pipeline_session
*session
)
249 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
250 if (session
->viewport_state_changed
) {
251 p
->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p
->dev
,
252 p
->state
.CC_VIEWPORT
, p
->cp
);
254 p
->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p
->dev
,
255 p
->state
.SF_CLIP_VIEWPORT
, p
->cp
);
260 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline
*p
,
261 const struct ilo_context
*ilo
,
262 struct gen6_pipeline_session
*session
)
264 /* 3DSTATE_BLEND_STATE_POINTERS */
265 if (session
->cc_state_blend_changed
) {
266 p
->gen7_3DSTATE_BLEND_STATE_POINTERS(p
->dev
,
267 p
->state
.BLEND_STATE
, p
->cp
);
270 /* 3DSTATE_CC_STATE_POINTERS */
271 if (session
->cc_state_cc_changed
) {
272 p
->gen7_3DSTATE_CC_STATE_POINTERS(p
->dev
,
273 p
->state
.COLOR_CALC_STATE
, p
->cp
);
276 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
277 if (session
->cc_state_dsa_changed
) {
278 p
->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p
->dev
,
279 p
->state
.DEPTH_STENCIL_STATE
, p
->cp
);
284 gen7_pipeline_vs(struct ilo_3d_pipeline
*p
,
285 const struct ilo_context
*ilo
,
286 struct gen6_pipeline_session
*session
)
288 const bool emit_3dstate_binding_table
= session
->binding_table_vs_changed
;
289 const bool emit_3dstate_sampler_state
= session
->sampler_state_vs_changed
;
290 /* see gen6_pipeline_vs() */
291 const bool emit_3dstate_constant_vs
= session
->pcb_state_vs_changed
;
292 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(VERTEX_SAMPLERS
));
294 /* emit depth stall before any of the VS commands */
295 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
296 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
297 gen7_wa_pipe_control_vs_depth_stall(p
);
299 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
300 if (emit_3dstate_binding_table
) {
301 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p
->dev
,
302 p
->state
.vs
.BINDING_TABLE_STATE
, p
->cp
);
305 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
306 if (emit_3dstate_sampler_state
) {
307 p
->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p
->dev
,
308 p
->state
.vs
.SAMPLER_STATE
, p
->cp
);
311 gen6_pipeline_vs(p
, ilo
, session
);
315 gen7_pipeline_hs(struct ilo_3d_pipeline
*p
,
316 const struct ilo_context
*ilo
,
317 struct gen6_pipeline_session
*session
)
319 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
320 if (session
->hw_ctx_changed
) {
321 p
->gen7_3DSTATE_CONSTANT_HS(p
->dev
, 0, 0, 0, p
->cp
);
322 p
->gen7_3DSTATE_HS(p
->dev
, NULL
, 0, 0, p
->cp
);
325 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
326 if (session
->hw_ctx_changed
)
327 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p
->dev
, 0, p
->cp
);
331 gen7_pipeline_te(struct ilo_3d_pipeline
*p
,
332 const struct ilo_context
*ilo
,
333 struct gen6_pipeline_session
*session
)
336 if (session
->hw_ctx_changed
)
337 p
->gen7_3DSTATE_TE(p
->dev
, p
->cp
);
341 gen7_pipeline_ds(struct ilo_3d_pipeline
*p
,
342 const struct ilo_context
*ilo
,
343 struct gen6_pipeline_session
*session
)
345 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
346 if (session
->hw_ctx_changed
) {
347 p
->gen7_3DSTATE_CONSTANT_DS(p
->dev
, 0, 0, 0, p
->cp
);
348 p
->gen7_3DSTATE_DS(p
->dev
, NULL
, 0, 0, p
->cp
);
351 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
352 if (session
->hw_ctx_changed
)
353 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p
->dev
, 0, p
->cp
);
358 gen7_pipeline_gs(struct ilo_3d_pipeline
*p
,
359 const struct ilo_context
*ilo
,
360 struct gen6_pipeline_session
*session
)
362 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
363 if (session
->hw_ctx_changed
) {
364 p
->gen6_3DSTATE_CONSTANT_GS(p
->dev
, 0, 0, 0, p
->cp
);
365 p
->gen7_3DSTATE_GS(p
->dev
, NULL
, 0, p
->cp
);
368 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
369 if (session
->binding_table_gs_changed
) {
370 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p
->dev
,
371 p
->state
.gs
.BINDING_TABLE_STATE
, p
->cp
);
376 gen7_pipeline_sol(struct ilo_3d_pipeline
*p
,
377 const struct ilo_context
*ilo
,
378 struct gen6_pipeline_session
*session
)
380 const struct pipe_stream_output_info
*so_info
;
381 const struct ilo_shader_state
*shader
;
382 bool dirty_sh
= false;
386 dirty_sh
= DIRTY(GS
);
390 dirty_sh
= DIRTY(VS
);
393 so_info
= ilo_shader_get_kernel_so_info(shader
);
395 gen6_pipeline_update_max_svbi(p
, ilo
, session
);
397 /* 3DSTATE_SO_BUFFER */
398 if ((DIRTY(STREAM_OUTPUT_TARGETS
) || dirty_sh
||
399 session
->batch_bo_changed
) && ilo
->so
.enabled
) {
402 for (i
= 0; i
< ilo
->so
.count
; i
++) {
403 const int stride
= so_info
->stride
[i
] * 4; /* in bytes */
406 /* reset HW write offsets and offset buffer base */
407 if (!p
->cp
->render_ctx
) {
408 ilo_cp_set_one_off_flags(p
->cp
, INTEL_EXEC_GEN7_SOL_RESET
);
409 base
+= p
->state
.so_num_vertices
* stride
;
412 p
->gen7_3DSTATE_SO_BUFFER(p
->dev
, i
, base
, stride
,
413 ilo
->so
.states
[i
], p
->cp
);
417 p
->gen7_3DSTATE_SO_BUFFER(p
->dev
, i
, 0, 0, NULL
, p
->cp
);
420 /* 3DSTATE_SO_DECL_LIST */
421 if (dirty_sh
&& ilo
->so
.enabled
)
422 p
->gen7_3DSTATE_SO_DECL_LIST(p
->dev
, so_info
, p
->cp
);
424 /* 3DSTATE_STREAMOUT */
425 if (DIRTY(STREAM_OUTPUT_TARGETS
) || DIRTY(RASTERIZER
) || dirty_sh
) {
426 const unsigned buffer_mask
= (1 << ilo
->so
.count
) - 1;
427 const int output_count
= ilo_shader_get_kernel_param(shader
,
428 ILO_KERNEL_OUTPUT_COUNT
);
430 p
->gen7_3DSTATE_STREAMOUT(p
->dev
, buffer_mask
, output_count
,
431 ilo
->rasterizer
->state
.rasterizer_discard
, p
->cp
);
436 gen7_pipeline_sf(struct ilo_3d_pipeline
*p
,
437 const struct ilo_context
*ilo
,
438 struct gen6_pipeline_session
*session
)
441 if (DIRTY(RASTERIZER
) || DIRTY(VS
) || DIRTY(GS
) || DIRTY(FS
)) {
442 const struct ilo_shader
*fs
= (ilo
->fs
)? ilo
->fs
->shader
: NULL
;
443 const struct ilo_shader
*last_sh
=
444 (ilo
->gs
)? ilo
->gs
->shader
:
445 (ilo
->vs
)? ilo
->vs
->shader
: NULL
;
447 p
->gen7_3DSTATE_SBE(p
->dev
, ilo
->rasterizer
, fs
, last_sh
, p
->cp
);
451 if (DIRTY(RASTERIZER
) || DIRTY(FRAMEBUFFER
)) {
452 gen7_wa_pipe_control_cs_stall(p
, true, true);
453 p
->gen7_3DSTATE_SF(p
->dev
, ilo
->rasterizer
, ilo
->fb
.state
.zsbuf
, p
->cp
);
458 gen7_pipeline_wm(struct ilo_3d_pipeline
*p
,
459 const struct ilo_context
*ilo
,
460 struct gen6_pipeline_session
*session
)
463 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DEPTH_STENCIL_ALPHA
) ||
465 const bool cc_may_kill
= (ilo
->dsa
->alpha
.enabled
||
466 ilo
->blend
->alpha_to_coverage
);
469 assert(!ilo
->fs
->shader
->pcb
.clip_state_size
);
471 if (p
->dev
->gen
== ILO_GEN(7) && session
->hw_ctx_changed
)
472 gen7_wa_pipe_control_wm_max_threads_stall(p
);
474 p
->gen7_3DSTATE_WM(p
->dev
, ilo
->fs
,
475 ilo
->rasterizer
, cc_may_kill
, p
->cp
);
478 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
479 if (session
->binding_table_fs_changed
) {
480 p
->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p
->dev
,
481 p
->state
.wm
.BINDING_TABLE_STATE
, p
->cp
);
484 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
485 if (session
->sampler_state_fs_changed
) {
486 p
->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p
->dev
,
487 p
->state
.wm
.SAMPLER_STATE
, p
->cp
);
490 /* 3DSTATE_CONSTANT_PS */
491 if (session
->pcb_state_fs_changed
)
492 p
->gen6_3DSTATE_CONSTANT_PS(p
->dev
, NULL
, NULL
, 0, p
->cp
);
495 if (DIRTY(FS
) || DIRTY(FRAGMENT_SAMPLERS
) ||
496 DIRTY(BLEND
) || session
->kernel_bo_changed
) {
497 const int num_samplers
= ilo
->sampler
[PIPE_SHADER_FRAGMENT
].count
;
498 const bool dual_blend
= ilo
->blend
->dual_blend
;
501 assert(!ilo
->fs
->shader
->pcb
.clip_state_size
);
503 p
->gen7_3DSTATE_PS(p
->dev
, ilo
->fs
, num_samplers
, dual_blend
, p
->cp
);
506 /* 3DSTATE_SCISSOR_STATE_POINTERS */
507 if (session
->scissor_state_changed
) {
508 p
->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p
->dev
,
509 p
->state
.SCISSOR_RECT
, p
->cp
);
512 /* XXX what is the best way to know if this workaround is needed? */
514 const bool emit_3dstate_ps
= (DIRTY(FS
) ||
515 DIRTY(FRAGMENT_SAMPLERS
) ||
517 const bool emit_3dstate_depth_buffer
=
518 (DIRTY(FRAMEBUFFER
) || DIRTY(DEPTH_STENCIL_ALPHA
) ||
519 session
->state_bo_changed
);
521 if (emit_3dstate_ps
||
522 emit_3dstate_depth_buffer
||
523 session
->pcb_state_fs_changed
||
524 session
->viewport_state_changed
||
525 session
->binding_table_fs_changed
||
526 session
->sampler_state_fs_changed
||
527 session
->cc_state_cc_changed
||
528 session
->cc_state_blend_changed
||
529 session
->cc_state_dsa_changed
)
530 gen7_wa_pipe_control_wm_depth_stall(p
, emit_3dstate_depth_buffer
);
533 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
534 if (DIRTY(FRAMEBUFFER
) || session
->batch_bo_changed
) {
535 const struct ilo_zs_surface
*zs
;
537 if (ilo
->fb
.state
.zsbuf
) {
538 const struct ilo_surface_cso
*surface
=
539 (const struct ilo_surface_cso
*) ilo
->fb
.state
.zsbuf
;
541 assert(!surface
->is_rt
);
545 zs
= &ilo
->fb
.null_zs
;
548 p
->gen7_3DSTATE_DEPTH_BUFFER(p
->dev
, zs
, p
->cp
);
549 p
->gen6_3DSTATE_HIER_DEPTH_BUFFER(p
->dev
, zs
, p
->cp
);
550 p
->gen6_3DSTATE_STENCIL_BUFFER(p
->dev
, zs
, p
->cp
);
553 p
->gen6_3DSTATE_CLEAR_PARAMS(p
->dev
, 0, p
->cp
);
558 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline
*p
,
559 const struct ilo_context
*ilo
,
560 struct gen6_pipeline_session
*session
)
562 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
563 if (DIRTY(SAMPLE_MASK
) || DIRTY(FRAMEBUFFER
)) {
564 const uint32_t *packed_sample_pos
;
566 gen7_wa_pipe_control_cs_stall(p
, true, true);
569 (ilo
->fb
.num_samples
> 4) ? p
->packed_sample_position_8x
:
570 (ilo
->fb
.num_samples
> 1) ? &p
->packed_sample_position_4x
:
571 &p
->packed_sample_position_1x
;
573 p
->gen6_3DSTATE_MULTISAMPLE(p
->dev
,
574 ilo
->fb
.num_samples
, packed_sample_pos
,
575 ilo
->rasterizer
->state
.half_pixel_center
, p
->cp
);
577 p
->gen7_3DSTATE_SAMPLE_MASK(p
->dev
,
578 (ilo
->fb
.num_samples
> 1) ? ilo
->sample_mask
: 0x1,
579 ilo
->fb
.num_samples
, p
->cp
);
584 gen7_pipeline_commands(struct ilo_3d_pipeline
*p
,
585 const struct ilo_context
*ilo
,
586 struct gen6_pipeline_session
*session
)
589 * We try to keep the order of the commands match, as closely as possible,
590 * that of the classic i965 driver. It allows us to compare the command
593 gen6_pipeline_common_select(p
, ilo
, session
);
594 gen6_pipeline_common_sip(p
, ilo
, session
);
595 gen6_pipeline_vf_statistics(p
, ilo
, session
);
596 gen7_pipeline_common_pcb_alloc(p
, ilo
, session
);
597 gen6_pipeline_common_base_address(p
, ilo
, session
);
598 gen7_pipeline_common_pointers_1(p
, ilo
, session
);
599 gen7_pipeline_common_urb(p
, ilo
, session
);
600 gen7_pipeline_common_pointers_2(p
, ilo
, session
);
601 gen7_pipeline_wm_multisample(p
, ilo
, session
);
602 gen7_pipeline_gs(p
, ilo
, session
);
603 gen7_pipeline_hs(p
, ilo
, session
);
604 gen7_pipeline_te(p
, ilo
, session
);
605 gen7_pipeline_ds(p
, ilo
, session
);
606 gen7_pipeline_vs(p
, ilo
, session
);
607 gen7_pipeline_sol(p
, ilo
, session
);
608 gen6_pipeline_clip(p
, ilo
, session
);
609 gen7_pipeline_sf(p
, ilo
, session
);
610 gen7_pipeline_wm(p
, ilo
, session
);
611 gen6_pipeline_wm_raster(p
, ilo
, session
);
612 gen6_pipeline_sf_rect(p
, ilo
, session
);
613 gen6_pipeline_vf(p
, ilo
, session
);
614 gen6_pipeline_vf_draw(p
, ilo
, session
);
618 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline
*p
,
619 const struct ilo_context
*ilo
,
620 const struct pipe_draw_info
*info
)
622 struct gen6_pipeline_session session
;
624 gen6_pipeline_prepare(p
, ilo
, info
, &session
);
626 session
.emit_draw_states
= gen6_pipeline_states
;
627 session
.emit_draw_commands
= gen7_pipeline_commands
;
629 gen6_pipeline_draw(p
, ilo
, &session
);
630 gen6_pipeline_end(p
, ilo
, &session
);
634 gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline
*p
,
635 const struct ilo_gpe_gen7
*gen7
,
636 const struct ilo_context
*ilo
)
639 enum ilo_gpe_gen7_command cmd
;
644 for (cmd
= 0; cmd
< ILO_GPE_GEN7_COMMAND_COUNT
; cmd
++) {
648 case ILO_GPE_GEN7_PIPE_CONTROL
:
649 /* for the workaround */
651 /* another one after 3DSTATE_URB */
653 /* and another one after 3DSTATE_CONSTANT_VS */
656 case ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS
:
659 case ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS
:
662 case ILO_GPE_GEN7_MEDIA_VFE_STATE
:
663 case ILO_GPE_GEN7_MEDIA_CURBE_LOAD
:
664 case ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD
:
665 case ILO_GPE_GEN7_MEDIA_STATE_FLUSH
:
666 case ILO_GPE_GEN7_GPGPU_WALKER
:
676 size
+= gen7
->estimate_command_size(p
->dev
,
685 gen7_pipeline_estimate_states(const struct ilo_3d_pipeline
*p
,
686 const struct ilo_gpe_gen7
*gen7
,
687 const struct ilo_context
*ilo
)
689 static int static_size
;
690 int shader_type
, count
, size
;
694 enum ilo_gpe_gen7_state state
;
696 } static_states
[] = {
698 { ILO_GPE_GEN7_SF_CLIP_VIEWPORT
, 1 },
699 { ILO_GPE_GEN7_CC_VIEWPORT
, 1 },
701 { ILO_GPE_GEN7_COLOR_CALC_STATE
, 1 },
702 { ILO_GPE_GEN7_BLEND_STATE
, ILO_MAX_DRAW_BUFFERS
},
703 { ILO_GPE_GEN7_DEPTH_STENCIL_STATE
, 1 },
705 { ILO_GPE_GEN7_SCISSOR_RECT
, 1 },
706 /* binding table (vs, gs, fs) */
707 { ILO_GPE_GEN7_BINDING_TABLE_STATE
, ILO_MAX_VS_SURFACES
},
708 { ILO_GPE_GEN7_BINDING_TABLE_STATE
, ILO_MAX_GS_SURFACES
},
709 { ILO_GPE_GEN7_BINDING_TABLE_STATE
, ILO_MAX_WM_SURFACES
},
713 for (i
= 0; i
< Elements(static_states
); i
++) {
714 static_size
+= gen7
->estimate_state_size(p
->dev
,
715 static_states
[i
].state
,
716 static_states
[i
].count
);
723 * render targets (fs)
724 * sampler views (vs, fs)
725 * constant buffers (vs, fs)
727 count
= ilo
->fb
.state
.nr_cbufs
;
728 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
729 count
+= ilo
->view
[shader_type
].count
;
730 count
+= ilo
->cbuf
[shader_type
].count
;
734 size
+= gen7
->estimate_state_size(p
->dev
,
735 ILO_GPE_GEN7_SURFACE_STATE
, count
);
738 /* samplers (vs, fs) */
739 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
740 count
= ilo
->sampler
[shader_type
].count
;
742 size
+= gen7
->estimate_state_size(p
->dev
,
743 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE
, count
);
744 size
+= gen7
->estimate_state_size(p
->dev
,
745 ILO_GPE_GEN7_SAMPLER_STATE
, count
);
750 if (ilo
->vs
&& ilo
->vs
->shader
->pcb
.clip_state_size
) {
751 const int pcb_size
= ilo
->vs
->shader
->pcb
.clip_state_size
;
753 size
+= gen7
->estimate_state_size(p
->dev
,
754 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER
, pcb_size
);
761 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline
*p
,
762 enum ilo_3d_pipeline_action action
,
765 const struct ilo_gpe_gen7
*gen7
= ilo_gpe_gen7_get();
769 case ILO_3D_PIPELINE_DRAW
:
771 const struct ilo_context
*ilo
= arg
;
773 size
= gen7_pipeline_estimate_commands(p
, gen7
, ilo
) +
774 gen7_pipeline_estimate_states(p
, gen7
, ilo
);
777 case ILO_3D_PIPELINE_FLUSH
:
778 case ILO_3D_PIPELINE_WRITE_TIMESTAMP
:
779 case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT
:
780 size
= gen7
->estimate_command_size(p
->dev
,
781 ILO_GPE_GEN7_PIPE_CONTROL
, 1);
784 assert(!"unknown 3D pipeline action");
793 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline
*p
)
795 const struct ilo_gpe_gen7
*gen7
= ilo_gpe_gen7_get();
797 p
->estimate_size
= ilo_3d_pipeline_estimate_size_gen7
;
798 p
->emit_draw
= ilo_3d_pipeline_emit_draw_gen7
;
799 p
->emit_flush
= ilo_3d_pipeline_emit_flush_gen6
;
800 p
->emit_write_timestamp
= ilo_3d_pipeline_emit_write_timestamp_gen6
;
801 p
->emit_write_depth_count
= ilo_3d_pipeline_emit_write_depth_count_gen6
;
803 #define GEN6_USE(p, name, from) \
804 p->gen6_ ## name = from->emit_ ## name
805 GEN6_USE(p
, STATE_BASE_ADDRESS
, gen7
);
806 GEN6_USE(p
, STATE_SIP
, gen7
);
807 GEN6_USE(p
, PIPELINE_SELECT
, gen7
);
808 GEN6_USE(p
, 3DSTATE_VERTEX_BUFFERS
, gen7
);
809 GEN6_USE(p
, 3DSTATE_VERTEX_ELEMENTS
, gen7
);
810 GEN6_USE(p
, 3DSTATE_INDEX_BUFFER
, gen7
);
811 GEN6_USE(p
, 3DSTATE_VF_STATISTICS
, gen7
);
812 GEN6_USE(p
, 3DSTATE_SCISSOR_STATE_POINTERS
, gen7
);
813 GEN6_USE(p
, 3DSTATE_VS
, gen7
);
814 GEN6_USE(p
, 3DSTATE_CLIP
, gen7
);
815 GEN6_USE(p
, 3DSTATE_CONSTANT_VS
, gen7
);
816 GEN6_USE(p
, 3DSTATE_CONSTANT_GS
, gen7
);
817 GEN6_USE(p
, 3DSTATE_CONSTANT_PS
, gen7
);
818 GEN6_USE(p
, 3DSTATE_DRAWING_RECTANGLE
, gen7
);
819 GEN6_USE(p
, 3DSTATE_POLY_STIPPLE_OFFSET
, gen7
);
820 GEN6_USE(p
, 3DSTATE_POLY_STIPPLE_PATTERN
, gen7
);
821 GEN6_USE(p
, 3DSTATE_LINE_STIPPLE
, gen7
);
822 GEN6_USE(p
, 3DSTATE_AA_LINE_PARAMETERS
, gen7
);
823 GEN6_USE(p
, 3DSTATE_MULTISAMPLE
, gen7
);
824 GEN6_USE(p
, 3DSTATE_STENCIL_BUFFER
, gen7
);
825 GEN6_USE(p
, 3DSTATE_HIER_DEPTH_BUFFER
, gen7
);
826 GEN6_USE(p
, 3DSTATE_CLEAR_PARAMS
, gen7
);
827 GEN6_USE(p
, PIPE_CONTROL
, gen7
);
828 GEN6_USE(p
, 3DPRIMITIVE
, gen7
);
829 GEN6_USE(p
, INTERFACE_DESCRIPTOR_DATA
, gen7
);
830 GEN6_USE(p
, CC_VIEWPORT
, gen7
);
831 GEN6_USE(p
, COLOR_CALC_STATE
, gen7
);
832 GEN6_USE(p
, BLEND_STATE
, gen7
);
833 GEN6_USE(p
, DEPTH_STENCIL_STATE
, gen7
);
834 GEN6_USE(p
, SCISSOR_RECT
, gen7
);
835 GEN6_USE(p
, BINDING_TABLE_STATE
, gen7
);
836 GEN6_USE(p
, SURFACE_STATE
, gen7
);
837 GEN6_USE(p
, SAMPLER_STATE
, gen7
);
838 GEN6_USE(p
, SAMPLER_BORDER_COLOR_STATE
, gen7
);
839 GEN6_USE(p
, push_constant_buffer
, gen7
);
842 #define GEN7_USE(p, name, from) \
843 p->gen7_ ## name = from->emit_ ## name
844 GEN7_USE(p
, 3DSTATE_DEPTH_BUFFER
, gen7
);
845 GEN7_USE(p
, 3DSTATE_CC_STATE_POINTERS
, gen7
);
846 GEN7_USE(p
, 3DSTATE_GS
, gen7
);
847 GEN7_USE(p
, 3DSTATE_SF
, gen7
);
848 GEN7_USE(p
, 3DSTATE_WM
, gen7
);
849 GEN7_USE(p
, 3DSTATE_SAMPLE_MASK
, gen7
);
850 GEN7_USE(p
, 3DSTATE_CONSTANT_HS
, gen7
);
851 GEN7_USE(p
, 3DSTATE_CONSTANT_DS
, gen7
);
852 GEN7_USE(p
, 3DSTATE_HS
, gen7
);
853 GEN7_USE(p
, 3DSTATE_TE
, gen7
);
854 GEN7_USE(p
, 3DSTATE_DS
, gen7
);
855 GEN7_USE(p
, 3DSTATE_STREAMOUT
, gen7
);
856 GEN7_USE(p
, 3DSTATE_SBE
, gen7
);
857 GEN7_USE(p
, 3DSTATE_PS
, gen7
);
858 GEN7_USE(p
, 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
, gen7
);
859 GEN7_USE(p
, 3DSTATE_VIEWPORT_STATE_POINTERS_CC
, gen7
);
860 GEN7_USE(p
, 3DSTATE_BLEND_STATE_POINTERS
, gen7
);
861 GEN7_USE(p
, 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
, gen7
);
862 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_VS
, gen7
);
863 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_HS
, gen7
);
864 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_DS
, gen7
);
865 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_GS
, gen7
);
866 GEN7_USE(p
, 3DSTATE_BINDING_TABLE_POINTERS_PS
, gen7
);
867 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_VS
, gen7
);
868 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_HS
, gen7
);
869 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_DS
, gen7
);
870 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_GS
, gen7
);
871 GEN7_USE(p
, 3DSTATE_SAMPLER_STATE_POINTERS_PS
, gen7
);
872 GEN7_USE(p
, 3DSTATE_URB_VS
, gen7
);
873 GEN7_USE(p
, 3DSTATE_URB_HS
, gen7
);
874 GEN7_USE(p
, 3DSTATE_URB_DS
, gen7
);
875 GEN7_USE(p
, 3DSTATE_URB_GS
, gen7
);
876 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_VS
, gen7
);
877 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_HS
, gen7
);
878 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_DS
, gen7
);
879 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_GS
, gen7
);
880 GEN7_USE(p
, 3DSTATE_PUSH_CONSTANT_ALLOC_PS
, gen7
);
881 GEN7_USE(p
, 3DSTATE_SO_DECL_LIST
, gen7
);
882 GEN7_USE(p
, 3DSTATE_SO_BUFFER
, gen7
);
883 GEN7_USE(p
, SF_CLIP_VIEWPORT
, gen7
);