src/gallium/drivers/ilo/ilo_blitter_blt.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "genhw/genhw.h"
  29 #include "util/u_pack_color.h"
  30
  31 #include "ilo_3d.h"
  32 #include "ilo_context.h"
  33 #include "ilo_cp.h"
  34 #include "ilo_blit.h"
  35 #include "ilo_resource.h"
  36 #include "ilo_blitter.h"
  37
  38 #define MI_FLUSH_DW           GEN_MI_CMD(MI_FLUSH_DW)
  39 #define MI_LOAD_REGISTER_IMM  GEN_MI_CMD(MI_LOAD_REGISTER_IMM)
  40 #define COLOR_BLT             GEN_BLITTER_CMD(COLOR_BLT)
  41 #define XY_COLOR_BLT          GEN_BLITTER_CMD(XY_COLOR_BLT)
  42 #define SRC_COPY_BLT          GEN_BLITTER_CMD(SRC_COPY_BLT)
  43 #define XY_SRC_COPY_BLT       GEN_BLITTER_CMD(XY_SRC_COPY_BLT)
  44
  45 enum gen6_blt_mask {
  46    GEN6_BLT_MASK_8,
  47    GEN6_BLT_MASK_16,
  48    GEN6_BLT_MASK_32,
  49    GEN6_BLT_MASK_32_LO,
  50    GEN6_BLT_MASK_32_HI,
  51 };
  52
  53 /*
  54  * From the Sandy Bridge PRM, volume 1 part 5, page 7:
  55  *
  56  *     "The BLT engine is capable of transferring very large quantities of
  57  *      graphics data. Any graphics data read from and written to the
  58  *      destination is permitted to represent a number of pixels that occupies
  59  *      up to 65,536 scan lines and up to 32,768 bytes per scan line at the
  60  *      destination. The maximum number of pixels that may be represented per
  61  *      scan line's worth of graphics data depends on the color depth."
  62  */
  63 static const int gen6_max_bytes_per_scanline = 32768;
  64 static const int gen6_max_scanlines = 65536;
  65
  66 static void
  67 gen6_emit_MI_FLUSH_DW(struct ilo_dev_info *dev, struct ilo_cp *cp)
  68 {
  69    const uint8_t cmd_len = 4;
  70
  71    ilo_cp_begin(cp, cmd_len);
  72    ilo_cp_write(cp, MI_FLUSH_DW | (cmd_len - 2));
  73    ilo_cp_write(cp, 0);
  74    ilo_cp_write(cp, 0);
  75    ilo_cp_write(cp, 0);
  76    ilo_cp_end(cp);
  77 }
  78
  79 static void
  80 gen6_emit_MI_LOAD_REGISTER_IMM(struct ilo_dev_info *dev,
  81                                uint32_t reg, uint32_t val,
  82                                struct ilo_cp *cp)
  83 {
  84    const uint8_t cmd_len = 3;
  85
  86    ilo_cp_begin(cp, cmd_len);
  87    ilo_cp_write(cp, MI_LOAD_REGISTER_IMM | (cmd_len - 2));
  88    ilo_cp_write(cp, reg);
  89    ilo_cp_write(cp, val);
  90    ilo_cp_end(cp);
  91 }
  92
  93 static uint32_t
  94 gen6_translate_blt_value_mask(enum gen6_blt_mask value_mask)
  95 {
  96    switch (value_mask) {
  97    case GEN6_BLT_MASK_8:  return GEN6_BLITTER_BR13_FORMAT_8;
  98    case GEN6_BLT_MASK_16: return GEN6_BLITTER_BR13_FORMAT_565;
  99    default:               return GEN6_BLITTER_BR13_FORMAT_8888;
 100    }
 101 }
 102
 103 static uint32_t
 104 gen6_translate_blt_write_mask(enum gen6_blt_mask write_mask)
 105 {
 106    switch (write_mask) {
 107    case GEN6_BLT_MASK_32:    return GEN6_BLITTER_BR00_WRITE_RGB |
 108                                     GEN6_BLITTER_BR00_WRITE_A;
 109    case GEN6_BLT_MASK_32_LO: return GEN6_BLITTER_BR00_WRITE_RGB;
 110    case GEN6_BLT_MASK_32_HI: return GEN6_BLITTER_BR00_WRITE_A;
 111    default:                  return 0;
 112    }
 113 }
 114
 115 static uint32_t
 116 gen6_translate_blt_cpp(enum gen6_blt_mask mask)
 117 {
 118    switch (mask) {
 119    case GEN6_BLT_MASK_8:  return 1;
 120    case GEN6_BLT_MASK_16: return 2;
 121    default:               return 4;
 122    }
 123 }
 124
 125 static void
 126 gen6_emit_COLOR_BLT(struct ilo_dev_info *dev,
 127                     struct intel_bo *dst_bo,
 128                     int16_t dst_pitch, uint32_t dst_offset,
 129                     uint16_t width, uint16_t height,
 130                     uint32_t pattern, uint8_t rop,
 131                     enum gen6_blt_mask value_mask,
 132                     enum gen6_blt_mask write_mask,
 133                     struct ilo_cp *cp)
 134 {
 135    const uint8_t cmd_len = 5;
 136    const int cpp = gen6_translate_blt_cpp(value_mask);
 137    uint32_t dw0, dw1;
 138
 139    dw0 = COLOR_BLT |
 140          gen6_translate_blt_write_mask(write_mask) |
 141          (cmd_len - 2);
 142
 143    assert(width < gen6_max_bytes_per_scanline);
 144    assert(height < gen6_max_scanlines);
 145    /* offsets are naturally aligned and pitches are dword-aligned */
 146    assert(dst_offset % cpp == 0 && dst_pitch % 4 == 0);
 147
 148    dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
 149          gen6_translate_blt_value_mask(value_mask) |
 150          dst_pitch;
 151
 152    ilo_cp_begin(cp, cmd_len);
 153    ilo_cp_write(cp, dw0);
 154    ilo_cp_write(cp, dw1);
 155    ilo_cp_write(cp, height << 16 | width);
 156    ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
 157                                            INTEL_DOMAIN_RENDER);
 158    ilo_cp_write(cp, pattern);
 159    ilo_cp_end(cp);
 160 }
 161
 162 static void
 163 gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev,
 164                        struct intel_bo *dst_bo,
 165                        enum intel_tiling_mode dst_tiling,
 166                        int16_t dst_pitch, uint32_t dst_offset,
 167                        int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 168                        uint32_t pattern, uint8_t rop,
 169                        enum gen6_blt_mask value_mask,
 170                        enum gen6_blt_mask write_mask,
 171                        struct ilo_cp *cp)
 172 {
 173    const uint8_t cmd_len = 6;
 174    const int cpp = gen6_translate_blt_cpp(value_mask);
 175    int dst_align, dst_pitch_shift;
 176    uint32_t dw0, dw1;
 177
 178    dw0 = XY_COLOR_BLT |
 179          gen6_translate_blt_write_mask(write_mask) |
 180          (cmd_len - 2);
 181
 182    if (dst_tiling == INTEL_TILING_NONE) {
 183       dst_align = 4;
 184       dst_pitch_shift = 0;
 185    }
 186    else {
 187       dw0 |= GEN6_BLITTER_BR00_DST_TILED;
 188
 189       dst_align = (dst_tiling == INTEL_TILING_Y) ? 128 : 512;
 190       /* in dwords when tiled */
 191       dst_pitch_shift = 2;
 192    }
 193
 194    assert((x2 - x1) * cpp < gen6_max_bytes_per_scanline);
 195    assert(y2 - y1 < gen6_max_scanlines);
 196    assert(dst_offset % dst_align == 0 && dst_pitch % dst_align == 0);
 197
 198    dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
 199          gen6_translate_blt_value_mask(value_mask) |
 200          dst_pitch >> dst_pitch_shift;
 201
 202    ilo_cp_begin(cp, cmd_len);
 203    ilo_cp_write(cp, dw0);
 204    ilo_cp_write(cp, dw1);
 205    ilo_cp_write(cp, y1 << 16 | x1);
 206    ilo_cp_write(cp, y2 << 16 | x2);
 207    ilo_cp_write_bo(cp, dst_offset, dst_bo,
 208                    INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
 209    ilo_cp_write(cp, pattern);
 210    ilo_cp_end(cp);
 211 }
 212
 213 static void
 214 gen6_emit_SRC_COPY_BLT(struct ilo_dev_info *dev,
 215                        struct intel_bo *dst_bo,
 216                        int16_t dst_pitch, uint32_t dst_offset,
 217                        uint16_t width, uint16_t height,
 218                        struct intel_bo *src_bo,
 219                        int16_t src_pitch, uint32_t src_offset,
 220                        bool dir_rtl, uint8_t rop,
 221                        enum gen6_blt_mask value_mask,
 222                        enum gen6_blt_mask write_mask,
 223                        struct ilo_cp *cp)
 224 {
 225    const uint8_t cmd_len = 6;
 226    const int cpp = gen6_translate_blt_cpp(value_mask);
 227    uint32_t dw0, dw1;
 228
 229    dw0 = SRC_COPY_BLT |
 230          gen6_translate_blt_write_mask(write_mask) |
 231          (cmd_len - 2);
 232
 233    assert(width < gen6_max_bytes_per_scanline);
 234    assert(height < gen6_max_scanlines);
 235    /* offsets are naturally aligned and pitches are dword-aligned */
 236    assert(dst_offset % cpp == 0 && dst_pitch % 4 == 0);
 237    assert(src_offset % cpp == 0 && src_pitch % 4 == 0);
 238
 239    dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
 240          gen6_translate_blt_value_mask(value_mask) |
 241          dst_pitch;
 242
 243    if (dir_rtl)
 244       dw1 |= GEN6_BLITTER_BR13_DIR_RTL;
 245
 246    ilo_cp_begin(cp, cmd_len);
 247    ilo_cp_write(cp, dw0);
 248    ilo_cp_write(cp, dw1);
 249    ilo_cp_write(cp, height << 16 | width);
 250    ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
 251                                            INTEL_DOMAIN_RENDER);
 252    ilo_cp_write(cp, src_pitch);
 253    ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
 254    ilo_cp_end(cp);
 255 }
 256
 257 static void
 258 gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev,
 259                           struct intel_bo *dst_bo,
 260                           enum intel_tiling_mode dst_tiling,
 261                           int16_t dst_pitch, uint32_t dst_offset,
 262                           int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 263                           struct intel_bo *src_bo,
 264                           enum intel_tiling_mode src_tiling,
 265                           int16_t src_pitch, uint32_t src_offset,
 266                           int16_t src_x, int16_t src_y, uint8_t rop,
 267                           enum gen6_blt_mask value_mask,
 268                           enum gen6_blt_mask write_mask,
 269                           struct ilo_cp *cp)
 270 {
 271    const uint8_t cmd_len = 8;
 272    const int cpp = gen6_translate_blt_cpp(value_mask);
 273    int dst_align, dst_pitch_shift;
 274    int src_align, src_pitch_shift;
 275    uint32_t dw0, dw1;
 276
 277    dw0 = XY_SRC_COPY_BLT |
 278          gen6_translate_blt_write_mask(write_mask) |
 279          (cmd_len - 2);
 280
 281    if (dst_tiling == INTEL_TILING_NONE) {
 282       dst_align = 4;
 283       dst_pitch_shift = 0;
 284    }
 285    else {
 286       dw0 |= GEN6_BLITTER_BR00_DST_TILED;
 287
 288       dst_align = (dst_tiling == INTEL_TILING_Y) ? 128 : 512;
 289       /* in dwords when tiled */
 290       dst_pitch_shift = 2;
 291    }
 292
 293    if (src_tiling == INTEL_TILING_NONE) {
 294       src_align = 4;
 295       src_pitch_shift = 0;
 296    }
 297    else {
 298       dw0 |= GEN6_BLITTER_BR00_SRC_TILED;
 299
 300       src_align = (src_tiling == INTEL_TILING_Y) ? 128 : 512;
 301       /* in dwords when tiled */
 302       src_pitch_shift = 2;
 303    }
 304
 305    assert((x2 - x1) * cpp < gen6_max_bytes_per_scanline);
 306    assert(y2 - y1 < gen6_max_scanlines);
 307    assert(dst_offset % dst_align == 0 && dst_pitch % dst_align == 0);
 308    assert(src_offset % src_align == 0 && src_pitch % src_align == 0);
 309
 310    dw1 = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
 311          gen6_translate_blt_value_mask(value_mask) |
 312          dst_pitch >> dst_pitch_shift;
 313
 314    ilo_cp_begin(cp, cmd_len);
 315    ilo_cp_write(cp, dw0);
 316    ilo_cp_write(cp, dw1);
 317    ilo_cp_write(cp, y1 << 16 | x1);
 318    ilo_cp_write(cp, y2 << 16 | x2);
 319    ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
 320                                            INTEL_DOMAIN_RENDER);
 321    ilo_cp_write(cp, src_y << 16 | src_x);
 322    ilo_cp_write(cp, src_pitch >> src_pitch_shift);
 323    ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
 324    ilo_cp_end(cp);
 325 }
 326
 327 static uint32_t
 328 ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size,
 329                       struct intel_bo *dst, enum intel_tiling_mode dst_tiling,
 330                       struct intel_bo *src, enum intel_tiling_mode src_tiling)
 331 {
 332    struct ilo_context *ilo = blitter->ilo;
 333    struct intel_bo *aper_check[3];
 334    int count;
 335    uint32_t swctrl;
 336
 337    /* change ring */
 338    ilo_cp_set_ring(ilo->cp, INTEL_RING_BLT);
 339    ilo_cp_set_owner(ilo->cp, NULL, 0);
 340
 341    /* check aperture space */
 342    aper_check[0] = ilo->cp->bo;
 343    aper_check[1] = dst;
 344    count = 2;
 345
 346    if (src) {
 347       aper_check[2] = src;
 348       count++;
 349    }
 350
 351    if (!intel_winsys_can_submit_bo(ilo->winsys, aper_check, count))
 352       ilo_cp_flush(ilo->cp, "out of aperture");
 353
 354    /* set BCS_SWCTRL */
 355    swctrl = 0x0;
 356
 357    if (dst_tiling == INTEL_TILING_Y) {
 358       swctrl |= GEN6_REG_BCS_SWCTRL_DST_TILING_Y << 16 |
 359                 GEN6_REG_BCS_SWCTRL_DST_TILING_Y;
 360    }
 361
 362    if (src && src_tiling == INTEL_TILING_Y) {
 363       swctrl |= GEN6_REG_BCS_SWCTRL_SRC_TILING_Y << 16 |
 364                 GEN6_REG_BCS_SWCTRL_SRC_TILING_Y;
 365    }
 366
 367    if (swctrl) {
 368       /*
 369        * Most clients expect BLT engine to be stateless.  If we have to set
 370        * BCS_SWCTRL to a non-default value, we have to set it back in the same
 371        * batch buffer.
 372        */
 373       if (ilo_cp_space(ilo->cp) < (4 + 3) * 2 + max_cmd_size)
 374          ilo_cp_flush(ilo->cp, "out of space");
 375
 376       ilo_cp_assert_no_implicit_flush(ilo->cp, true);
 377
 378       /*
 379        * From the Ivy Bridge PRM, volume 1 part 4, page 133:
 380        *
 381        *     "SW is required to flush the HW before changing the polarity of
 382        *      this bit (Tile Y Destination/Source)."
 383        */
 384       gen6_emit_MI_FLUSH_DW(ilo->dev, ilo->cp);
 385       gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev,
 386             GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp);
 387
 388       swctrl &= ~(GEN6_REG_BCS_SWCTRL_DST_TILING_Y |
 389                   GEN6_REG_BCS_SWCTRL_SRC_TILING_Y);
 390    }
 391
 392    return swctrl;
 393 }
 394
 395 static void
 396 ilo_blitter_blt_end(struct ilo_blitter *blitter, uint32_t swctrl)
 397 {
 398    struct ilo_context *ilo = blitter->ilo;
 399
 400    /* set BCS_SWCTRL back */
 401    if (swctrl) {
 402       gen6_emit_MI_FLUSH_DW(ilo->dev, ilo->cp);
 403       gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp);
 404
 405       ilo_cp_assert_no_implicit_flush(ilo->cp, false);
 406    }
 407 }
 408
 409 static bool
 410 buf_clear_region(struct ilo_blitter *blitter,
 411                  struct ilo_buffer *dst,
 412                  unsigned dst_offset, unsigned dst_size,
 413                  uint32_t val,
 414                  enum gen6_blt_mask value_mask,
 415                  enum gen6_blt_mask write_mask)
 416 {
 417    const uint8_t rop = 0xf0; /* PATCOPY */
 418    const int cpp = gen6_translate_blt_cpp(value_mask);
 419    struct ilo_context *ilo = blitter->ilo;
 420    unsigned offset = 0;
 421
 422    if (dst_offset % cpp || dst_size % cpp)
 423       return false;
 424
 425    ilo_blitter_blt_begin(blitter, 0,
 426          dst->bo, INTEL_TILING_NONE, NULL, INTEL_TILING_NONE);
 427
 428    while (dst_size) {
 429       unsigned width, height;
 430       int16_t pitch;
 431
 432       width = dst_size;
 433       height = 1;
 434       pitch = 0;
 435
 436       if (width > gen6_max_bytes_per_scanline) {
 437          /* less than INT16_MAX and dword-aligned */
 438          pitch = 32764;
 439
 440          width = pitch;
 441          height = dst_size / width;
 442          if (height > gen6_max_scanlines)
 443             height = gen6_max_scanlines;
 444       }
 445
 446       gen6_emit_COLOR_BLT(ilo->dev, dst->bo, pitch, dst_offset + offset,
 447             width, height, val, rop, value_mask, write_mask, ilo->cp);
 448
 449       offset += pitch * height;
 450       dst_size -= width * height;
 451    }
 452
 453    ilo_blitter_blt_end(blitter, 0);
 454
 455    return true;
 456 }
 457
 458 static bool
 459 buf_copy_region(struct ilo_blitter *blitter,
 460                 struct ilo_buffer *dst, unsigned dst_offset,
 461                 struct ilo_buffer *src, unsigned src_offset,
 462                 unsigned size)
 463 {
 464    const uint8_t rop = 0xcc; /* SRCCOPY */
 465    struct ilo_context *ilo = blitter->ilo;
 466    unsigned offset = 0;
 467
 468    ilo_blitter_blt_begin(blitter, 0,
 469          dst->bo, INTEL_TILING_NONE, src->bo, INTEL_TILING_NONE);
 470
 471    while (size) {
 472       unsigned width, height;
 473       int16_t pitch;
 474
 475       width = size;
 476       height = 1;
 477       pitch = 0;
 478
 479       if (width > gen6_max_bytes_per_scanline) {
 480          /* less than INT16_MAX and dword-aligned */
 481          pitch = 32764;
 482
 483          width = pitch;
 484          height = size / width;
 485          if (height > gen6_max_scanlines)
 486             height = gen6_max_scanlines;
 487       }
 488
 489       gen6_emit_SRC_COPY_BLT(ilo->dev,
 490             dst->bo, pitch, dst_offset + offset,
 491             width, height,
 492             src->bo, pitch, src_offset + offset,
 493             false, rop, GEN6_BLT_MASK_8, GEN6_BLT_MASK_8,
 494             ilo->cp);
 495
 496       offset += pitch * height;
 497       size -= width * height;
 498    }
 499
 500    ilo_blitter_blt_end(blitter, 0);
 501
 502    return true;
 503 }
 504
 505 static bool
 506 tex_clear_region(struct ilo_blitter *blitter,
 507                  struct ilo_texture *dst, unsigned dst_level,
 508                  const struct pipe_box *dst_box,
 509                  uint32_t val,
 510                  enum gen6_blt_mask value_mask,
 511                  enum gen6_blt_mask write_mask)
 512 {
 513    const int cpp = gen6_translate_blt_cpp(value_mask);
 514    const unsigned max_extent = 32767; /* INT16_MAX */
 515    const uint8_t rop = 0xf0; /* PATCOPY */
 516    struct ilo_context *ilo = blitter->ilo;
 517    uint32_t swctrl;
 518    int slice;
 519
 520    /* no W-tiling support */
 521    if (dst->separate_s8)
 522       return false;
 523
 524    if (dst->bo_stride > max_extent)
 525       return false;
 526
 527    swctrl = ilo_blitter_blt_begin(blitter, dst_box->depth * 6,
 528          dst->bo, dst->tiling, NULL, INTEL_TILING_NONE);
 529
 530    for (slice = 0; slice < dst_box->depth; slice++) {
 531       const struct ilo_texture_slice *dst_slice =
 532          ilo_texture_get_slice(dst, dst_level, dst_box->z + slice);
 533       unsigned x1, y1, x2, y2;
 534
 535       x1 = dst_slice->x + dst_box->x;
 536       y1 = dst_slice->y + dst_box->y;
 537       x2 = x1 + dst_box->width;
 538       y2 = y1 + dst_box->height;
 539
 540       if (x2 > max_extent || y2 > max_extent ||
 541           (x2 - x1) * cpp > gen6_max_bytes_per_scanline)
 542          break;
 543
 544       gen6_emit_XY_COLOR_BLT(ilo->dev,
 545             dst->bo, dst->tiling, dst->bo_stride, 0,
 546             x1, y1, x2, y2, val, rop, value_mask, write_mask,
 547             ilo->cp);
 548    }
 549
 550    ilo_blitter_blt_end(blitter, swctrl);
 551
 552    return (slice == dst_box->depth);
 553 }
 554
 555 static bool
 556 tex_copy_region(struct ilo_blitter *blitter,
 557                 struct ilo_texture *dst,
 558                 unsigned dst_level,
 559                 unsigned dst_x, unsigned dst_y, unsigned dst_z,
 560                 struct ilo_texture *src,
 561                 unsigned src_level,
 562                 const struct pipe_box *src_box)
 563 {
 564    const struct util_format_description *desc =
 565       util_format_description(dst->bo_format);
 566    const unsigned max_extent = 32767; /* INT16_MAX */
 567    const uint8_t rop = 0xcc; /* SRCCOPY */
 568    struct ilo_context *ilo = blitter->ilo;
 569    enum gen6_blt_mask mask;
 570    uint32_t swctrl;
 571    int cpp, xscale, slice;
 572
 573    /* no W-tiling support */
 574    if (dst->separate_s8 || src->separate_s8)
 575       return false;
 576
 577    if (dst->bo_stride > max_extent || src->bo_stride > max_extent)
 578       return false;
 579
 580    cpp = desc->block.bits / 8;
 581    xscale = 1;
 582
 583    /* accommodate for larger cpp */
 584    if (cpp > 4) {
 585       if (cpp % 2 == 1)
 586          return false;
 587
 588       cpp = (cpp % 4 == 0) ? 4 : 2;
 589       xscale = (desc->block.bits / 8) / cpp;
 590    }
 591
 592    switch (cpp) {
 593    case 1:
 594       mask = GEN6_BLT_MASK_8;
 595       break;
 596    case 2:
 597       mask = GEN6_BLT_MASK_16;
 598       break;
 599    case 4:
 600       mask = GEN6_BLT_MASK_32;
 601       break;
 602    default:
 603       return false;
 604       break;
 605    }
 606
 607    swctrl = ilo_blitter_blt_begin(blitter, src_box->depth * 8,
 608          dst->bo, dst->tiling, src->bo, src->tiling);
 609
 610    for (slice = 0; slice < src_box->depth; slice++) {
 611       const struct ilo_texture_slice *dst_slice =
 612          ilo_texture_get_slice(dst, dst_level, dst_z + slice);
 613       const struct ilo_texture_slice *src_slice =
 614          ilo_texture_get_slice(src, src_level, src_box->z + slice);
 615       unsigned x1, y1, x2, y2, src_x, src_y;
 616
 617       x1 = (dst_slice->x + dst_x) * xscale;
 618       y1 = dst_slice->y + dst_y;
 619       x2 = (x1 + src_box->width) * xscale;
 620       y2 = y1 + src_box->height;
 621       src_x = (src_slice->x + src_box->x) * xscale;
 622       src_y = src_slice->y + src_box->y;
 623
 624       /* in blocks */
 625       x1 /= desc->block.width;
 626       y1 /= desc->block.height;
 627       x2 = (x2 + desc->block.width - 1) / desc->block.width;
 628       y2 = (y2 + desc->block.height - 1) / desc->block.height;
 629       src_x /= desc->block.width;
 630       src_y /= desc->block.height;
 631
 632       if (x2 > max_extent || y2 > max_extent ||
 633           src_x > max_extent || src_y > max_extent ||
 634           (x2 - x1) * cpp > gen6_max_bytes_per_scanline)
 635          break;
 636
 637       gen6_emit_XY_SRC_COPY_BLT(ilo->dev,
 638             dst->bo, dst->tiling, dst->bo_stride, 0,
 639             x1, y1, x2, y2,
 640             src->bo, src->tiling, src->bo_stride, 0,
 641             src_x, src_y, rop, mask, mask,
 642             ilo->cp);
 643    }
 644
 645    ilo_blitter_blt_end(blitter, swctrl);
 646
 647    return (slice == src_box->depth);
 648 }
 649
 650 bool
 651 ilo_blitter_blt_copy_resource(struct ilo_blitter *blitter,
 652                               struct pipe_resource *dst, unsigned dst_level,
 653                               unsigned dst_x, unsigned dst_y, unsigned dst_z,
 654                               struct pipe_resource *src, unsigned src_level,
 655                               const struct pipe_box *src_box)
 656 {
 657    bool success;
 658
 659    ilo_blit_resolve_slices(blitter->ilo, src, src_level,
 660          src_box->z, src_box->depth, ILO_TEXTURE_BLT_READ);
 661    ilo_blit_resolve_slices(blitter->ilo, dst, dst_level,
 662          dst_z, src_box->depth, ILO_TEXTURE_BLT_WRITE);
 663
 664    if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 665       const unsigned dst_offset = dst_x;
 666       const unsigned src_offset = src_box->x;
 667       const unsigned size = src_box->width;
 668
 669       assert(dst_level == 0 && dst_y == 0 && dst_z == 0);
 670       assert(src_level == 0 &&
 671              src_box->y == 0 &&
 672              src_box->z == 0 &&
 673              src_box->height == 1 &&
 674              src_box->depth == 1);
 675
 676       success = buf_copy_region(blitter,
 677             ilo_buffer(dst), dst_offset, ilo_buffer(src), src_offset, size);
 678    }
 679    else if (dst->target != PIPE_BUFFER && src->target != PIPE_BUFFER) {
 680       success = tex_copy_region(blitter,
 681             ilo_texture(dst), dst_level, dst_x, dst_y, dst_z,
 682             ilo_texture(src), src_level, src_box);
 683    }
 684    else {
 685       success = false;
 686    }
 687
 688    return success;
 689 }
 690
 691 bool
 692 ilo_blitter_blt_clear_rt(struct ilo_blitter *blitter,
 693                          struct pipe_surface *rt,
 694                          const union pipe_color_union *color,
 695                          unsigned x, unsigned y,
 696                          unsigned width, unsigned height)
 697 {
 698    const int cpp = util_format_get_blocksize(rt->format);
 699    enum gen6_blt_mask mask;
 700    union util_color packed;
 701    bool success;
 702
 703    if (!ilo_3d_pass_render_condition(blitter->ilo))
 704       return true;
 705
 706    switch (cpp) {
 707    case 1:
 708       mask = GEN6_BLT_MASK_8;
 709       break;
 710    case 2:
 711       mask = GEN6_BLT_MASK_16;
 712       break;
 713    case 4:
 714       mask = GEN6_BLT_MASK_32;
 715       break;
 716    default:
 717       return false;
 718       break;
 719    }
 720
 721    if (util_format_is_pure_integer(rt->format) ||
 722        util_format_is_compressed(rt->format))
 723       return false;
 724
 725    ilo_blit_resolve_surface(blitter->ilo, rt, ILO_TEXTURE_BLT_WRITE);
 726
 727    util_pack_color(color->f, rt->format, &packed);
 728
 729    if (rt->texture->target == PIPE_BUFFER) {
 730       unsigned offset, end, size;
 731
 732       assert(y == 0 && height == 1);
 733
 734       offset = (rt->u.buf.first_element + x) * cpp;
 735       end = (rt->u.buf.last_element + 1) * cpp;
 736
 737       size = width * cpp;
 738       if (offset + size > end)
 739          size = end - offset;
 740
 741       success = buf_clear_region(blitter, ilo_buffer(rt->texture),
 742             offset, size, packed.ui, mask, mask);
 743    }
 744    else {
 745       struct pipe_box box;
 746
 747       u_box_3d(x, y, rt->u.tex.first_layer, width, height,
 748             rt->u.tex.last_layer - rt->u.tex.first_layer + 1, &box);
 749
 750       success = tex_clear_region(blitter, ilo_texture(rt->texture),
 751             rt->u.tex.level, &box, packed.ui, mask, mask);
 752    }
 753
 754    return success;
 755 }
 756
 757 bool
 758 ilo_blitter_blt_clear_zs(struct ilo_blitter *blitter,
 759                          struct pipe_surface *zs,
 760                          unsigned clear_flags,
 761                          double depth, unsigned stencil,
 762                          unsigned x, unsigned y,
 763                          unsigned width, unsigned height)
 764 {
 765    enum gen6_blt_mask value_mask, write_mask;
 766    struct pipe_box box;
 767    uint32_t val;
 768
 769    if (!ilo_3d_pass_render_condition(blitter->ilo))
 770       return true;
 771
 772    switch (zs->format) {
 773    case PIPE_FORMAT_Z16_UNORM:
 774       if (!(clear_flags & PIPE_CLEAR_DEPTH))
 775          return true;
 776
 777       value_mask = GEN6_BLT_MASK_16;
 778       write_mask = GEN6_BLT_MASK_16;
 779       break;
 780    case PIPE_FORMAT_Z32_FLOAT:
 781       if (!(clear_flags & PIPE_CLEAR_DEPTH))
 782          return true;
 783
 784       value_mask = GEN6_BLT_MASK_32;
 785       write_mask = GEN6_BLT_MASK_32;
 786       break;
 787    case PIPE_FORMAT_Z24X8_UNORM:
 788       if (!(clear_flags & PIPE_CLEAR_DEPTH))
 789          return true;
 790
 791       value_mask = GEN6_BLT_MASK_32;
 792       write_mask = GEN6_BLT_MASK_32_LO;
 793       break;
 794    case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 795       if (!(clear_flags & PIPE_CLEAR_DEPTHSTENCIL))
 796          return true;
 797
 798       value_mask = GEN6_BLT_MASK_32;
 799
 800       if ((clear_flags & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL)
 801          write_mask = GEN6_BLT_MASK_32;
 802       else if (clear_flags & PIPE_CLEAR_DEPTH)
 803          write_mask = GEN6_BLT_MASK_32_LO;
 804       else
 805          write_mask = GEN6_BLT_MASK_32_HI;
 806       break;
 807    default:
 808       return false;
 809       break;
 810    }
 811
 812    ilo_blit_resolve_surface(blitter->ilo, zs, ILO_TEXTURE_BLT_WRITE);
 813
 814    val = util_pack_z_stencil(zs->format, depth, stencil);
 815
 816    u_box_3d(x, y, zs->u.tex.first_layer, width, height,
 817          zs->u.tex.last_layer - zs->u.tex.first_layer + 1, &box);
 818
 819    assert(zs->texture->target != PIPE_BUFFER);
 820
 821    return tex_clear_region(blitter, ilo_texture(zs->texture),
 822          zs->u.tex.level, &box, val, value_mask, write_mask);
 823 }