projects / mesa.git / blob
? search:


3207843cbcd331be5c70d8c5ef1713ef0722170f
[mesa.git] / src / gallium / drivers / ilo / ilo_builder_3d_bottom.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_BUILDER_3D_BOTTOM_H
29 #define ILO_BUILDER_3D_BOTTOM_H
30
31 #include "genhw/genhw.h"
32 #include "intel_winsys.h"
33
34 #include "ilo_common.h"
35 #include "ilo_format.h"
36 #include "ilo_shader.h"
37 #include "ilo_builder.h"
38 #include "ilo_builder_3d_top.h"
39
40 static inline void
41 gen6_3DSTATE_CLIP(struct ilo_builder *builder,
42 const struct ilo_rasterizer_state *rasterizer,
43 const struct ilo_shader_state *fs,
44 bool enable_guardband,
45 int num_viewports)
46 {
47 const uint8_t cmd_len = 4;
48 uint32_t dw1, dw2, dw3, *dw;
49 int interps;
50
51 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
52
53 dw1 = rasterizer->clip.payload[0];
54 dw2 = rasterizer->clip.payload[1];
55 dw3 = rasterizer->clip.payload[2];
56
57 if (enable_guardband && rasterizer->clip.can_enable_guardband)
58 dw2 |= GEN6_CLIP_DW2_GB_TEST_ENABLE;
59
60 interps = (fs) ? ilo_shader_get_kernel_param(fs,
61 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) : 0;
62
63 if (interps & (GEN6_INTERP_NONPERSPECTIVE_PIXEL |
64 GEN6_INTERP_NONPERSPECTIVE_CENTROID |
65 GEN6_INTERP_NONPERSPECTIVE_SAMPLE))
66 dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE;
67
68 dw3 |= GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO |
69 (num_viewports - 1);
70
71 ilo_builder_batch_pointer(builder, cmd_len, &dw);
72
73 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (cmd_len - 2);
74 dw[1] = dw1;
75 dw[2] = dw2;
76 dw[3] = dw3;
77 }
78
79 static inline void
80 gen6_disable_3DSTATE_CLIP(struct ilo_builder *builder)
81 {
82 const uint8_t cmd_len = 4;
83 uint32_t *dw;
84
85 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
86
87 ilo_builder_batch_pointer(builder, cmd_len, &dw);
88
89 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (cmd_len - 2);
90 dw[1] = 0;
91 dw[2] = 0;
92 dw[3] = 0;
93 }
94
95 /**
96 * Fill in DW2 to DW7 of 3DSTATE_SF.
97 */
98 static inline void
99 ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev,
100 const struct ilo_rasterizer_state *rasterizer,
101 int num_samples,
102 enum pipe_format depth_format,
103 uint32_t *payload, unsigned payload_len)
104 {
105 assert(payload_len == Elements(rasterizer->sf.payload));
106
107 if (rasterizer) {
108 const struct ilo_rasterizer_sf *sf = &rasterizer->sf;
109
110 memcpy(payload, sf->payload, sizeof(sf->payload));
111 if (num_samples > 1)
112 payload[1] |= sf->dw_msaa;
113 }
114 else {
115 payload[0] = 0;
116 payload[1] = (num_samples > 1) ? GEN7_SF_DW2_MSRASTMODE_ON_PATTERN : 0;
117 payload[2] = 0;
118 payload[3] = 0;
119 payload[4] = 0;
120 payload[5] = 0;
121 }
122
123 if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
124 int format;
125
126 /* separate stencil */
127 switch (depth_format) {
128 case PIPE_FORMAT_Z16_UNORM:
129 format = GEN6_ZFORMAT_D16_UNORM;
130 break;
131 case PIPE_FORMAT_Z32_FLOAT:
132 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
133 format = GEN6_ZFORMAT_D32_FLOAT;
134 break;
135 case PIPE_FORMAT_Z24X8_UNORM:
136 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
137 format = GEN6_ZFORMAT_D24_UNORM_X8_UINT;
138 break;
139 default:
140 /* FLOAT surface is assumed when there is no depth buffer */
141 format = GEN6_ZFORMAT_D32_FLOAT;
142 break;
143 }
144
145 payload[0] |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT;
146 }
147 }
148
149 /**
150 * Fill in DW1 and DW8 to DW19 of 3DSTATE_SF.
151 */
152 static inline void
153 ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
154 const struct ilo_rasterizer_state *rasterizer,
155 const struct ilo_shader_state *fs,
156 uint32_t *dw, int num_dwords)
157 {
158 int output_count, vue_offset, vue_len;
159 const struct ilo_kernel_routing *routing;
160
161 ILO_DEV_ASSERT(dev, 6, 7.5);
162 assert(num_dwords == 13);
163
164 if (!fs) {
165 memset(dw, 0, sizeof(dw[0]) * num_dwords);
166 dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
167 return;
168 }
169
170 output_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT);
171 assert(output_count <= 32);
172
173 routing = ilo_shader_get_kernel_routing(fs);
174
175 vue_offset = routing->source_skip;
176 assert(vue_offset % 2 == 0);
177 vue_offset /= 2;
178
179 vue_len = (routing->source_len + 1) / 2;
180 if (!vue_len)
181 vue_len = 1;
182
183 dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
184 vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT |
185 vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
186 if (routing->swizzle_enable)
187 dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
188
189 switch (rasterizer->state.sprite_coord_mode) {
190 case PIPE_SPRITE_COORD_UPPER_LEFT:
191 dw[0] |= GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT;
192 break;
193 case PIPE_SPRITE_COORD_LOWER_LEFT:
194 dw[0] |= GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT;
195 break;
196 }
197
198 STATIC_ASSERT(Elements(routing->swizzles) >= 16);
199 memcpy(&dw[1], routing->swizzles, 2 * 16);
200
201 /*
202 * From the Ivy Bridge PRM, volume 2 part 1, page 268:
203 *
204 * "This field (Point Sprite Texture Coordinate Enable) must be
205 * programmed to 0 when non-point primitives are rendered."
206 *
207 * TODO We do not check that yet.
208 */
209 dw[9] = routing->point_sprite_enable;
210
211 dw[10] = routing->const_interp_enable;
212
213 /* WrapShortest enables */
214 dw[11] = 0;
215 dw[12] = 0;
216 }
217
218 static inline void
219 gen6_3DSTATE_SF(struct ilo_builder *builder,
220 const struct ilo_rasterizer_state *rasterizer,
221 const struct ilo_shader_state *fs)
222 {
223 const uint8_t cmd_len = 20;
224 uint32_t payload_raster[6], payload_sbe[13], *dw;
225
226 ILO_DEV_ASSERT(builder->dev, 6, 6);
227
228 ilo_gpe_gen6_fill_3dstate_sf_raster(builder->dev, rasterizer,
229 1, PIPE_FORMAT_NONE, payload_raster, Elements(payload_raster));
230 ilo_gpe_gen6_fill_3dstate_sf_sbe(builder->dev, rasterizer,
231 fs, payload_sbe, Elements(payload_sbe));
232
233 ilo_builder_batch_pointer(builder, cmd_len, &dw);
234
235 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
236 dw[1] = payload_sbe[0];
237 memcpy(&dw[2], payload_raster, sizeof(payload_raster));
238 memcpy(&dw[8], &payload_sbe[1], sizeof(payload_sbe) - 4);
239 }
240
241 static inline void
242 gen7_3DSTATE_SF(struct ilo_builder *builder,
243 const struct ilo_rasterizer_state *rasterizer,
244 enum pipe_format zs_format)
245 {
246 const uint8_t cmd_len = 7;
247 const int num_samples = 1;
248 uint32_t payload[6], *dw;
249
250 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
251
252 ilo_gpe_gen6_fill_3dstate_sf_raster(builder->dev,
253 rasterizer, num_samples, zs_format,
254 payload, Elements(payload));
255
256 ilo_builder_batch_pointer(builder, cmd_len, &dw);
257
258 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
259 memcpy(&dw[1], payload, sizeof(payload));
260 }
261
262 static inline void
263 gen7_3DSTATE_SBE(struct ilo_builder *builder,
264 const struct ilo_rasterizer_state *rasterizer,
265 const struct ilo_shader_state *fs)
266 {
267 const uint8_t cmd_len = 14;
268 uint32_t payload[13], *dw;
269
270 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
271
272 ilo_gpe_gen6_fill_3dstate_sf_sbe(builder->dev,
273 rasterizer, fs, payload, Elements(payload));
274
275 ilo_builder_batch_pointer(builder, cmd_len, &dw);
276
277 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
278 memcpy(&dw[1], payload, sizeof(payload));
279 }
280
281 static inline void
282 gen6_3DSTATE_WM(struct ilo_builder *builder,
283 const struct ilo_shader_state *fs,
284 const struct ilo_rasterizer_state *rasterizer,
285 bool dual_blend, bool cc_may_kill,
286 uint32_t hiz_op)
287 {
288 const uint8_t cmd_len = 9;
289 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
290 const int num_samples = 1;
291 const struct ilo_shader_cso *fs_cso;
292 uint32_t dw2, dw4, dw5, dw6, *dw;
293
294 ILO_DEV_ASSERT(builder->dev, 6, 6);
295
296 if (!fs) {
297 /* see brwCreateContext() */
298 const int max_threads = (builder->dev->gt == 2) ? 80 : 40;
299
300 ilo_builder_batch_pointer(builder, cmd_len, &dw);
301 dw[0] = dw0;
302 dw[1] = 0;
303 dw[2] = 0;
304 dw[3] = 0;
305 dw[4] = hiz_op;
306 /* honor the valid range even if dispatching is disabled */
307 dw[5] = (max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT;
308 dw[6] = 0;
309 dw[7] = 0;
310 dw[8] = 0;
311
312 return;
313 }
314
315 fs_cso = ilo_shader_get_kernel_cso(fs);
316 dw2 = fs_cso->payload[0];
317 dw4 = fs_cso->payload[1];
318 dw5 = fs_cso->payload[2];
319 dw6 = fs_cso->payload[3];
320
321 /*
322 * From the Sandy Bridge PRM, volume 2 part 1, page 248:
323 *
324 * "This bit (Statistics Enable) must be disabled if either of these
325 * bits is set: Depth Buffer Clear , Hierarchical Depth Buffer Resolve
326 * Enable or Depth Buffer Resolve Enable."
327 */
328 assert(!hiz_op);
329 dw4 |= GEN6_WM_DW4_STATISTICS;
330
331 if (cc_may_kill)
332 dw5 |= GEN6_WM_DW5_PS_KILL | GEN6_WM_DW5_PS_ENABLE;
333
334 if (dual_blend)
335 dw5 |= GEN6_WM_DW5_DUAL_SOURCE_BLEND;
336
337 dw5 |= rasterizer->wm.payload[0];
338
339 dw6 |= rasterizer->wm.payload[1];
340
341 if (num_samples > 1) {
342 dw6 |= rasterizer->wm.dw_msaa_rast |
343 rasterizer->wm.dw_msaa_disp;
344 }
345
346 ilo_builder_batch_pointer(builder, cmd_len, &dw);
347 dw[0] = dw0;
348 dw[1] = ilo_shader_get_kernel_offset(fs);
349 dw[2] = dw2;
350 dw[3] = 0; /* scratch */
351 dw[4] = dw4;
352 dw[5] = dw5;
353 dw[6] = dw6;
354 dw[7] = 0; /* kernel 1 */
355 dw[8] = 0; /* kernel 2 */
356 }
357
358 static inline void
359 gen7_3DSTATE_WM(struct ilo_builder *builder,
360 const struct ilo_shader_state *fs,
361 const struct ilo_rasterizer_state *rasterizer,
362 bool cc_may_kill, uint32_t hiz_op)
363 {
364 const uint8_t cmd_len = 3;
365 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
366 const int num_samples = 1;
367 uint32_t dw1, dw2, *dw;
368
369 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
370
371 /* see ilo_gpe_init_rasterizer_wm() */
372 if (rasterizer) {
373 dw1 = rasterizer->wm.payload[0];
374 dw2 = rasterizer->wm.payload[1];
375
376 assert(!hiz_op);
377 dw1 |= GEN7_WM_DW1_STATISTICS;
378 }
379 else {
380 dw1 = hiz_op;
381 dw2 = 0;
382 }
383
384 if (fs) {
385 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
386
387 dw1 |= fs_cso->payload[3];
388 }
389
390 if (cc_may_kill)
391 dw1 |= GEN7_WM_DW1_PS_ENABLE | GEN7_WM_DW1_PS_KILL;
392
393 if (num_samples > 1) {
394 dw1 |= rasterizer->wm.dw_msaa_rast;
395 dw2 |= rasterizer->wm.dw_msaa_disp;
396 }
397
398 ilo_builder_batch_pointer(builder, cmd_len, &dw);
399 dw[0] = dw0;
400 dw[1] = dw1;
401 dw[2] = dw2;
402 }
403
404 static inline void
405 gen7_3DSTATE_PS(struct ilo_builder *builder,
406 const struct ilo_shader_state *fs,
407 bool dual_blend)
408 {
409 const uint8_t cmd_len = 8;
410 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
411 const struct ilo_shader_cso *cso;
412 uint32_t dw2, dw4, dw5, *dw;
413
414 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
415
416 if (!fs) {
417 int max_threads;
418
419 /* GPU hangs if none of the dispatch enable bits is set */
420 dw4 = GEN7_PS_DW4_8_PIXEL_DISPATCH;
421
422 /* see brwCreateContext() */
423 switch (ilo_dev_gen(builder->dev)) {
424 case ILO_GEN(7.5):
425 max_threads = (builder->dev->gt == 3) ? 408 :
426 (builder->dev->gt == 2) ? 204 : 102;
427 dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
428 break;
429 case ILO_GEN(7):
430 default:
431 max_threads = (builder->dev->gt == 2) ? 172 : 48;
432 dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
433 break;
434 }
435
436 ilo_builder_batch_pointer(builder, cmd_len, &dw);
437 dw[0] = dw0;
438 dw[1] = 0;
439 dw[2] = 0;
440 dw[3] = 0;
441 dw[4] = dw4;
442 dw[5] = 0;
443 dw[6] = 0;
444 dw[7] = 0;
445
446 return;
447 }
448
449 cso = ilo_shader_get_kernel_cso(fs);
450 dw2 = cso->payload[0];
451 dw4 = cso->payload[1];
452 dw5 = cso->payload[2];
453
454 if (dual_blend)
455 dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
456
457 ilo_builder_batch_pointer(builder, cmd_len, &dw);
458 dw[0] = dw0;
459 dw[1] = ilo_shader_get_kernel_offset(fs);
460 dw[2] = dw2;
461 dw[3] = 0; /* scratch */
462 dw[4] = dw4;
463 dw[5] = dw5;
464 dw[6] = 0; /* kernel 1 */
465 dw[7] = 0; /* kernel 2 */
466 }
467
468 static inline void
469 gen6_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
470 const uint32_t *bufs, const int *sizes,
471 int num_bufs)
472 {
473 const uint8_t cmd_len = 5;
474 uint32_t buf_dw[4], buf_enabled;
475 uint32_t *dw;
476
477 ILO_DEV_ASSERT(builder->dev, 6, 6);
478 assert(num_bufs <= 4);
479
480 /*
481 * From the Sandy Bridge PRM, volume 2 part 1, page 287:
482 *
483 * "The sum of all four read length fields (each incremented to
484 * represent the actual read length) must be less than or equal to 64"
485 */
486 buf_enabled = gen6_fill_3dstate_constant(builder->dev,
487 bufs, sizes, num_bufs, 64, buf_dw, Elements(buf_dw));
488
489 ilo_builder_batch_pointer(builder, cmd_len, &dw);
490
491 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) |
492 buf_enabled << 12 |
493 (cmd_len - 2);
494 memcpy(&dw[1], buf_dw, sizeof(buf_dw));
495 }
496
497 static inline void
498 gen7_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
499 const uint32_t *bufs, const int *sizes,
500 int num_bufs)
501 {
502 gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
503 bufs, sizes, num_bufs);
504 }
505
506 static inline void
507 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(struct ilo_builder *builder,
508 uint32_t binding_table)
509 {
510 gen7_3dstate_pointer(builder,
511 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
512 binding_table);
513 }
514
515 static inline void
516 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(struct ilo_builder *builder,
517 uint32_t sampler_state)
518 {
519 gen7_3dstate_pointer(builder,
520 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
521 sampler_state);
522 }
523
524 static inline void
525 gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
526 int num_samples,
527 const uint32_t *packed_sample_pos,
528 bool pixel_location_center)
529 {
530 const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 3;
531 uint32_t dw1, dw2, dw3, *dw;
532
533 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
534
535 dw1 = (pixel_location_center) ? GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER :
536 GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER;
537
538 switch (num_samples) {
539 case 0:
540 case 1:
541 dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
542 dw2 = 0;
543 dw3 = 0;
544 break;
545 case 4:
546 dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
547 dw2 = packed_sample_pos[0];
548 dw3 = 0;
549 break;
550 case 8:
551 assert(ilo_dev_gen(builder->dev) >= ILO_GEN(7));
552 dw1 |= GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
553 dw2 = packed_sample_pos[0];
554 dw3 = packed_sample_pos[1];
555 break;
556 default:
557 assert(!"unsupported sample count");
558 dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
559 dw2 = 0;
560 dw3 = 0;
561 break;
562 }
563
564 ilo_builder_batch_pointer(builder, cmd_len, &dw);
565
566 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (cmd_len - 2);
567 dw[1] = dw1;
568 dw[2] = dw2;
569 if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
570 dw[3] = dw3;
571 }
572
573 static inline void
574 gen6_3DSTATE_SAMPLE_MASK(struct ilo_builder *builder,
575 unsigned sample_mask)
576 {
577 const uint8_t cmd_len = 2;
578 const unsigned valid_mask = 0xf;
579 uint32_t *dw;
580
581 ILO_DEV_ASSERT(builder->dev, 6, 6);
582
583 sample_mask &= valid_mask;
584
585 ilo_builder_batch_pointer(builder, cmd_len, &dw);
586
587 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) | (cmd_len - 2);
588 dw[1] = sample_mask;
589 }
590
591 static inline void
592 gen7_3DSTATE_SAMPLE_MASK(struct ilo_builder *builder,
593 unsigned sample_mask,
594 int num_samples)
595 {
596 const uint8_t cmd_len = 2;
597 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
598 uint32_t *dw;
599
600 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
601
602 /*
603 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
604 *
605 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
606 * (Sample Mask) must be zero.
607 *
608 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
609 * must be zero."
610 */
611 sample_mask &= valid_mask;
612
613 ilo_builder_batch_pointer(builder, cmd_len, &dw);
614
615 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) | (cmd_len - 2);
616 dw[1] = sample_mask;
617 }
618
619 static inline void
620 gen6_3DSTATE_DRAWING_RECTANGLE(struct ilo_builder *builder,
621 unsigned x, unsigned y,
622 unsigned width, unsigned height)
623 {
624 const uint8_t cmd_len = 4;
625 unsigned xmax = x + width - 1;
626 unsigned ymax = y + height - 1;
627 unsigned rect_limit;
628 uint32_t *dw;
629
630 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
631
632 if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
633 rect_limit = 16383;
634 }
635 else {
636 /*
637 * From the Sandy Bridge PRM, volume 2 part 1, page 230:
638 *
639 * "[DevSNB] Errata: This field (Clipped Drawing Rectangle Y Min)
640 * must be an even number"
641 */
642 assert(y % 2 == 0);
643
644 rect_limit = 8191;
645 }
646
647 if (x > rect_limit) x = rect_limit;
648 if (y > rect_limit) y = rect_limit;
649 if (xmax > rect_limit) xmax = rect_limit;
650 if (ymax > rect_limit) ymax = rect_limit;
651
652 ilo_builder_batch_pointer(builder, cmd_len, &dw);
653
654 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) | (cmd_len - 2);
655 dw[1] = y << 16 | x;
656 dw[2] = ymax << 16 | xmax;
657 /*
658 * There is no need to set the origin. It is intended to support front
659 * buffer rendering.
660 */
661 dw[3] = 0;
662 }
663
664 static inline void
665 gen6_3DSTATE_POLY_STIPPLE_OFFSET(struct ilo_builder *builder,
666 int x_offset, int y_offset)
667 {
668 const uint8_t cmd_len = 2;
669 uint32_t *dw;
670
671 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
672
673 assert(x_offset >= 0 && x_offset <= 31);
674 assert(y_offset >= 0 && y_offset <= 31);
675
676 ilo_builder_batch_pointer(builder, cmd_len, &dw);
677
678 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET) | (cmd_len - 2);
679 dw[1] = x_offset << 8 | y_offset;
680 }
681
682 static inline void
683 gen6_3DSTATE_POLY_STIPPLE_PATTERN(struct ilo_builder *builder,
684 const struct pipe_poly_stipple *pattern)
685 {
686 const uint8_t cmd_len = 33;
687 uint32_t *dw;
688 int i;
689
690 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
691
692 ilo_builder_batch_pointer(builder, cmd_len, &dw);
693
694 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN) | (cmd_len - 2);
695 dw++;
696
697 STATIC_ASSERT(Elements(pattern->stipple) == 32);
698 for (i = 0; i < 32; i++)
699 dw[i] = pattern->stipple[i];
700 }
701
702 static inline void
703 gen6_3DSTATE_LINE_STIPPLE(struct ilo_builder *builder,
704 unsigned pattern, unsigned factor)
705 {
706 const uint8_t cmd_len = 3;
707 unsigned inverse;
708 uint32_t *dw;
709
710 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
711
712 assert((pattern & 0xffff) == pattern);
713 assert(factor >= 1 && factor <= 256);
714
715 ilo_builder_batch_pointer(builder, cmd_len, &dw);
716
717 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE) | (cmd_len - 2);
718 dw[1] = pattern;
719
720 if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
721 /* in U1.16 */
722 inverse = 65536 / factor;
723
724 dw[2] = inverse << GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT |
725 factor;
726 }
727 else {
728 /* in U1.13 */
729 inverse = 8192 / factor;
730
731 dw[2] = inverse << GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT |
732 factor;
733 }
734 }
735
736 static inline void
737 gen6_3DSTATE_AA_LINE_PARAMETERS(struct ilo_builder *builder)
738 {
739 const uint8_t cmd_len = 3;
740 const uint32_t dw[3] = {
741 GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) | (cmd_len - 2),
742 0 << GEN6_AA_LINE_DW1_BIAS__SHIFT | 0,
743 0 << GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT | 0,
744 };
745
746 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
747
748 ilo_builder_batch_write(builder, cmd_len, dw);
749 }
750
751 static inline void
752 gen6_3DSTATE_DEPTH_BUFFER(struct ilo_builder *builder,
753 const struct ilo_zs_surface *zs,
754 bool aligned_8x4)
755 {
756 const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
757 GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
758 GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
759 const uint8_t cmd_len = 7;
760 uint32_t *dw;
761 unsigned pos;
762
763 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
764
765 pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
766
767 dw[0] = cmd | (cmd_len - 2);
768 dw[1] = zs->payload[0];
769 dw[3] = (aligned_8x4) ? zs->dw_aligned_8x4 : zs->payload[2];
770 dw[4] = zs->payload[3];
771 dw[5] = zs->payload[4];
772 dw[6] = zs->payload[5];
773
774 if (zs->bo) {
775 ilo_builder_batch_reloc(builder, pos + 2,
776 zs->bo, zs->payload[1], INTEL_RELOC_WRITE);
777 } else {
778 dw[2] = 0;
779 }
780 }
781
782 static inline void
783 gen6_3DSTATE_STENCIL_BUFFER(struct ilo_builder *builder,
784 const struct ilo_zs_surface *zs)
785 {
786 const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
787 GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
788 GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
789 const uint8_t cmd_len = 3;
790 uint32_t *dw;
791 unsigned pos;
792
793 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
794
795 pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
796
797 dw[0] = cmd | (cmd_len - 2);
798 /* see ilo_gpe_init_zs_surface() */
799 dw[1] = zs->payload[6];
800
801 if (zs->separate_s8_bo) {
802 ilo_builder_batch_reloc(builder, pos + 2,
803 zs->separate_s8_bo, zs->payload[7], INTEL_RELOC_WRITE);
804 } else {
805 dw[2] = 0;
806 }
807 }
808
809 static inline void
810 gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_builder *builder,
811 const struct ilo_zs_surface *zs)
812 {
813 const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
814 GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
815 GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
816 const uint8_t cmd_len = 3;
817 uint32_t *dw;
818 unsigned pos;
819
820 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
821
822 pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
823
824 dw[0] = cmd | (cmd_len - 2);
825 /* see ilo_gpe_init_zs_surface() */
826 dw[1] = zs->payload[8];
827
828 if (zs->hiz_bo) {
829 ilo_builder_batch_reloc(builder, pos + 2,
830 zs->hiz_bo, zs->payload[9], INTEL_RELOC_WRITE);
831 } else {
832 dw[2] = 0;
833 }
834 }
835
836 static inline void
837 gen6_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
838 uint32_t clear_val)
839 {
840 const uint8_t cmd_len = 2;
841 uint32_t *dw;
842
843 ILO_DEV_ASSERT(builder->dev, 6, 6);
844
845 ilo_builder_batch_pointer(builder, cmd_len, &dw);
846
847 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
848 GEN6_CLEAR_PARAMS_DW0_VALID |
849 (cmd_len - 2);
850 dw[1] = clear_val;
851 }
852
853 static inline void
854 gen7_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
855 uint32_t clear_val)
856 {
857 const uint8_t cmd_len = 3;
858 uint32_t *dw;
859
860 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
861
862 ilo_builder_batch_pointer(builder, cmd_len, &dw);
863
864 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) | (cmd_len - 2);
865 dw[1] = clear_val;
866 dw[2] = GEN7_CLEAR_PARAMS_DW2_VALID;
867 }
868
869 static inline void
870 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct ilo_builder *builder,
871 uint32_t clip_viewport,
872 uint32_t sf_viewport,
873 uint32_t cc_viewport)
874 {
875 const uint8_t cmd_len = 4;
876 uint32_t *dw;
877
878 ILO_DEV_ASSERT(builder->dev, 6, 6);
879
880 ilo_builder_batch_pointer(builder, cmd_len, &dw);
881
882 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) |
883 GEN6_PTR_VP_DW0_CLIP_CHANGED |
884 GEN6_PTR_VP_DW0_SF_CHANGED |
885 GEN6_PTR_VP_DW0_CC_CHANGED |
886 (cmd_len - 2);
887 dw[1] = clip_viewport;
888 dw[2] = sf_viewport;
889 dw[3] = cc_viewport;
890 }
891
892 static inline void
893 gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct ilo_builder *builder,
894 uint32_t scissor_rect)
895 {
896 const uint8_t cmd_len = 2;
897 uint32_t *dw;
898
899 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
900
901 ilo_builder_batch_pointer(builder, cmd_len, &dw);
902
903 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS) |
904 (cmd_len - 2);
905 dw[1] = scissor_rect;
906 }
907
908 static inline void
909 gen6_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
910 uint32_t blend_state,
911 uint32_t depth_stencil_state,
912 uint32_t color_calc_state)
913 {
914 const uint8_t cmd_len = 4;
915 uint32_t *dw;
916
917 ILO_DEV_ASSERT(builder->dev, 6, 6);
918
919 ilo_builder_batch_pointer(builder, cmd_len, &dw);
920
921 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS) | (cmd_len - 2);
922 dw[1] = blend_state | GEN6_PTR_CC_DW1_BLEND_CHANGED;
923 dw[2] = depth_stencil_state | GEN6_PTR_CC_DW2_ZS_CHANGED;
924 dw[3] = color_calc_state | GEN6_PTR_CC_DW3_CC_CHANGED;
925 }
926
927 static inline void
928 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(struct ilo_builder *builder,
929 uint32_t sf_clip_viewport)
930 {
931 gen7_3dstate_pointer(builder,
932 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
933 sf_clip_viewport);
934 }
935
936 static inline void
937 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(struct ilo_builder *builder,
938 uint32_t cc_viewport)
939 {
940 gen7_3dstate_pointer(builder,
941 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
942 cc_viewport);
943 }
944
945 static inline void
946 gen7_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
947 uint32_t color_calc_state)
948 {
949 gen7_3dstate_pointer(builder,
950 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, color_calc_state);
951 }
952
953 static inline void
954 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(struct ilo_builder *builder,
955 uint32_t depth_stencil_state)
956 {
957 gen7_3dstate_pointer(builder,
958 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
959 depth_stencil_state);
960 }
961
962 static inline void
963 gen7_3DSTATE_BLEND_STATE_POINTERS(struct ilo_builder *builder,
964 uint32_t blend_state)
965 {
966 gen7_3dstate_pointer(builder,
967 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
968 blend_state);
969 }
970
971 static inline uint32_t
972 gen6_CLIP_VIEWPORT(struct ilo_builder *builder,
973 const struct ilo_viewport_cso *viewports,
974 unsigned num_viewports)
975 {
976 const int state_align = 32;
977 const int state_len = 4 * num_viewports;
978 uint32_t state_offset, *dw;
979 unsigned i;
980
981 ILO_DEV_ASSERT(builder->dev, 6, 6);
982
983 /*
984 * From the Sandy Bridge PRM, volume 2 part 1, page 193:
985 *
986 * "The viewport-related state is stored as an array of up to 16
987 * elements..."
988 */
989 assert(num_viewports && num_viewports <= 16);
990
991 state_offset = ilo_builder_dynamic_pointer(builder,
992 ILO_BUILDER_ITEM_CLIP_VIEWPORT, state_align, state_len, &dw);
993
994 for (i = 0; i < num_viewports; i++) {
995 const struct ilo_viewport_cso *vp = &viewports[i];
996
997 dw[0] = fui(vp->min_gbx);
998 dw[1] = fui(vp->max_gbx);
999 dw[2] = fui(vp->min_gby);
1000 dw[3] = fui(vp->max_gby);
1001
1002 dw += 4;
1003 }
1004
1005 return state_offset;
1006 }
1007
1008 static inline uint32_t
1009 gen6_SF_VIEWPORT(struct ilo_builder *builder,
1010 const struct ilo_viewport_cso *viewports,
1011 unsigned num_viewports)
1012 {
1013 const int state_align = 32;
1014 const int state_len = 8 * num_viewports;
1015 uint32_t state_offset, *dw;
1016 unsigned i;
1017
1018 ILO_DEV_ASSERT(builder->dev, 6, 6);
1019
1020 /*
1021 * From the Sandy Bridge PRM, volume 2 part 1, page 262:
1022 *
1023 * "The viewport-specific state used by the SF unit (SF_VIEWPORT) is
1024 * stored as an array of up to 16 elements..."
1025 */
1026 assert(num_viewports && num_viewports <= 16);
1027
1028 state_offset = ilo_builder_dynamic_pointer(builder,
1029 ILO_BUILDER_ITEM_SF_VIEWPORT, state_align, state_len, &dw);
1030
1031 for (i = 0; i < num_viewports; i++) {
1032 const struct ilo_viewport_cso *vp = &viewports[i];
1033
1034 dw[0] = fui(vp->m00);
1035 dw[1] = fui(vp->m11);
1036 dw[2] = fui(vp->m22);
1037 dw[3] = fui(vp->m30);
1038 dw[4] = fui(vp->m31);
1039 dw[5] = fui(vp->m32);
1040 dw[6] = 0;
1041 dw[7] = 0;
1042
1043 dw += 8;
1044 }
1045
1046 return state_offset;
1047 }
1048
1049 static inline uint32_t
1050 gen7_SF_CLIP_VIEWPORT(struct ilo_builder *builder,
1051 const struct ilo_viewport_cso *viewports,
1052 unsigned num_viewports)
1053 {
1054 const int state_align = 64;
1055 const int state_len = 16 * num_viewports;
1056 uint32_t state_offset, *dw;
1057 unsigned i;
1058
1059 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
1060
1061 /*
1062 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1063 *
1064 * "The viewport-specific state used by both the SF and CL units
1065 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1066 * of which contains the DWords described below. The start of each
1067 * element is spaced 16 DWords apart. The location of first element of
1068 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1069 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1070 */
1071 assert(num_viewports && num_viewports <= 16);
1072
1073 state_offset = ilo_builder_dynamic_pointer(builder,
1074 ILO_BUILDER_ITEM_SF_VIEWPORT, state_align, state_len, &dw);
1075
1076 for (i = 0; i < num_viewports; i++) {
1077 const struct ilo_viewport_cso *vp = &viewports[i];
1078
1079 dw[0] = fui(vp->m00);
1080 dw[1] = fui(vp->m11);
1081 dw[2] = fui(vp->m22);
1082 dw[3] = fui(vp->m30);
1083 dw[4] = fui(vp->m31);
1084 dw[5] = fui(vp->m32);
1085 dw[6] = 0;
1086 dw[7] = 0;
1087 dw[8] = fui(vp->min_gbx);
1088 dw[9] = fui(vp->max_gbx);
1089 dw[10] = fui(vp->min_gby);
1090 dw[11] = fui(vp->max_gby);
1091 dw[12] = 0;
1092 dw[13] = 0;
1093 dw[14] = 0;
1094 dw[15] = 0;
1095
1096 dw += 16;
1097 }
1098
1099 return state_offset;
1100 }
1101
1102 static inline uint32_t
1103 gen6_CC_VIEWPORT(struct ilo_builder *builder,
1104 const struct ilo_viewport_cso *viewports,
1105 unsigned num_viewports)
1106 {
1107 const int state_align = 32;
1108 const int state_len = 2 * num_viewports;
1109 uint32_t state_offset, *dw;
1110 unsigned i;
1111
1112 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1113
1114 /*
1115 * From the Sandy Bridge PRM, volume 2 part 1, page 385:
1116 *
1117 * "The viewport state is stored as an array of up to 16 elements..."
1118 */
1119 assert(num_viewports && num_viewports <= 16);
1120
1121 state_offset = ilo_builder_dynamic_pointer(builder,
1122 ILO_BUILDER_ITEM_CC_VIEWPORT, state_align, state_len, &dw);
1123
1124 for (i = 0; i < num_viewports; i++) {
1125 const struct ilo_viewport_cso *vp = &viewports[i];
1126
1127 dw[0] = fui(vp->min_z);
1128 dw[1] = fui(vp->max_z);
1129
1130 dw += 2;
1131 }
1132
1133 return state_offset;
1134 }
1135
1136 static inline uint32_t
1137 gen6_SCISSOR_RECT(struct ilo_builder *builder,
1138 const struct ilo_scissor_state *scissor,
1139 unsigned num_viewports)
1140 {
1141 const int state_align = 32;
1142 const int state_len = 2 * num_viewports;
1143
1144 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1145
1146 /*
1147 * From the Sandy Bridge PRM, volume 2 part 1, page 263:
1148 *
1149 * "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
1150 * stored as an array of up to 16 elements..."
1151 */
1152 assert(num_viewports && num_viewports <= 16);
1153 assert(Elements(scissor->payload) >= state_len);
1154
1155 return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_SCISSOR_RECT,
1156 state_align, state_len, scissor->payload);
1157 }
1158
1159 static inline uint32_t
1160 gen6_COLOR_CALC_STATE(struct ilo_builder *builder,
1161 const struct pipe_stencil_ref *stencil_ref,
1162 ubyte alpha_ref,
1163 const struct pipe_blend_color *blend_color)
1164 {
1165 const int state_align = 64;
1166 const int state_len = 6;
1167 uint32_t state_offset, *dw;
1168
1169 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1170
1171 state_offset = ilo_builder_dynamic_pointer(builder,
1172 ILO_BUILDER_ITEM_COLOR_CALC, state_align, state_len, &dw);
1173
1174 dw[0] = stencil_ref->ref_value[0] << 24 |
1175 stencil_ref->ref_value[1] << 16 |
1176 GEN6_CC_DW0_ALPHATEST_UNORM8;
1177 dw[1] = alpha_ref;
1178 dw[2] = fui(blend_color->color[0]);
1179 dw[3] = fui(blend_color->color[1]);
1180 dw[4] = fui(blend_color->color[2]);
1181 dw[5] = fui(blend_color->color[3]);
1182
1183 return state_offset;
1184 }
1185
1186 static inline uint32_t
1187 gen6_DEPTH_STENCIL_STATE(struct ilo_builder *builder,
1188 const struct ilo_dsa_state *dsa)
1189 {
1190 const int state_align = 64;
1191 const int state_len = 3;
1192
1193 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1194
1195 STATIC_ASSERT(Elements(dsa->payload) >= state_len);
1196
1197 return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_DEPTH_STENCIL,
1198 state_align, state_len, dsa->payload);
1199 }
1200
1201 static inline uint32_t
1202 gen6_BLEND_STATE(struct ilo_builder *builder,
1203 const struct ilo_blend_state *blend,
1204 const struct ilo_fb_state *fb,
1205 const struct ilo_dsa_state *dsa)
1206 {
1207 const int state_align = 64;
1208 int state_len;
1209 uint32_t state_offset, *dw;
1210 unsigned num_targets, i;
1211
1212 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1213
1214 /*
1215 * From the Sandy Bridge PRM, volume 2 part 1, page 376:
1216 *
1217 * "The blend state is stored as an array of up to 8 elements..."
1218 */
1219 num_targets = fb->state.nr_cbufs;
1220 assert(num_targets <= 8);
1221
1222 if (!num_targets) {
1223 if (!dsa->dw_alpha)
1224 return 0;
1225 /* to be able to reference alpha func */
1226 num_targets = 1;
1227 }
1228
1229 state_len = 2 * num_targets;
1230
1231 state_offset = ilo_builder_dynamic_pointer(builder,
1232 ILO_BUILDER_ITEM_BLEND, state_align, state_len, &dw);
1233
1234 for (i = 0; i < num_targets; i++) {
1235 const struct ilo_blend_cso *cso =
1236 &blend->cso[(blend->independent_blend_enable) ? i : 0];
1237
1238 dw[0] = cso->payload[0];
1239 dw[1] = cso->payload[1];
1240
1241 if (i < fb->state.nr_cbufs && fb->state.cbufs[i]) {
1242 const struct ilo_fb_blend_caps *caps = &fb->blend_caps[i];
1243
1244 if (caps->can_blend) {
1245 if (caps->dst_alpha_forced_one)
1246 dw[0] |= cso->dw_blend_dst_alpha_forced_one;
1247 else
1248 dw[0] |= cso->dw_blend;
1249 }
1250
1251 if (caps->can_logicop)
1252 dw[1] |= cso->dw_logicop;
1253
1254 if (caps->can_alpha_test)
1255 dw[1] |= dsa->dw_alpha;
1256 } else {
1257 dw[1] |= GEN6_BLEND_DW1_WRITE_DISABLE_A |
1258 GEN6_BLEND_DW1_WRITE_DISABLE_R |
1259 GEN6_BLEND_DW1_WRITE_DISABLE_G |
1260 GEN6_BLEND_DW1_WRITE_DISABLE_B |
1261 dsa->dw_alpha;
1262 }
1263
1264 /*
1265 * From the Sandy Bridge PRM, volume 2 part 1, page 356:
1266 *
1267 * "When NumSamples = 1, AlphaToCoverage and AlphaToCoverage
1268 * Dither both must be disabled."
1269 *
1270 * There is no such limitation on GEN7, or for AlphaToOne. But GL
1271 * requires that anyway.
1272 */
1273 if (fb->num_samples > 1)
1274 dw[1] |= cso->dw_alpha_mod;
1275
1276 dw += 2;
1277 }
1278
1279 return state_offset;
1280 }
1281
1282 #endif /* ILO_BUILDER_3D_BOTTOM_H */