projects / mesa.git / blob
? search:


6427228a64cd085baacd344cb91c7aef74a24fc1
[mesa.git] / src / gallium / drivers / ilo / ilo_builder_3d_bottom.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_BUILDER_3D_BOTTOM_H
29 #define ILO_BUILDER_3D_BOTTOM_H
30
31 #include "genhw/genhw.h"
32 #include "intel_winsys.h"
33
34 #include "ilo_common.h"
35 #include "ilo_format.h"
36 #include "ilo_shader.h"
37 #include "ilo_builder.h"
38 #include "ilo_builder_3d_top.h"
39
40 static inline void
41 gen6_3DSTATE_CLIP(struct ilo_builder *builder,
42 const struct ilo_rasterizer_state *rasterizer,
43 const struct ilo_shader_state *fs,
44 bool enable_guardband,
45 int num_viewports)
46 {
47 const uint8_t cmd_len = 4;
48 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (cmd_len - 2);
49 uint32_t dw1, dw2, dw3, *dw;
50
51 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
52
53 if (rasterizer) {
54 int interps;
55
56 dw1 = rasterizer->clip.payload[0];
57 dw2 = rasterizer->clip.payload[1];
58 dw3 = rasterizer->clip.payload[2];
59
60 if (enable_guardband && rasterizer->clip.can_enable_guardband)
61 dw2 |= GEN6_CLIP_DW2_GB_TEST_ENABLE;
62
63 interps = (fs) ? ilo_shader_get_kernel_param(fs,
64 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) : 0;
65
66 if (interps & (GEN6_INTERP_NONPERSPECTIVE_PIXEL |
67 GEN6_INTERP_NONPERSPECTIVE_CENTROID |
68 GEN6_INTERP_NONPERSPECTIVE_SAMPLE))
69 dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE;
70
71 dw3 |= GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO |
72 (num_viewports - 1);
73 }
74 else {
75 dw1 = 0;
76 dw2 = 0;
77 dw3 = 0;
78 }
79
80 ilo_builder_batch_pointer(builder, cmd_len, &dw);
81 dw[0] = dw0;
82 dw[1] = dw1;
83 dw[2] = dw2;
84 dw[3] = dw3;
85 }
86
87 /**
88 * Fill in DW2 to DW7 of 3DSTATE_SF.
89 */
90 static inline void
91 ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev,
92 const struct ilo_rasterizer_state *rasterizer,
93 int num_samples,
94 enum pipe_format depth_format,
95 uint32_t *payload, unsigned payload_len)
96 {
97 assert(payload_len == Elements(rasterizer->sf.payload));
98
99 if (rasterizer) {
100 const struct ilo_rasterizer_sf *sf = &rasterizer->sf;
101
102 memcpy(payload, sf->payload, sizeof(sf->payload));
103 if (num_samples > 1)
104 payload[1] |= sf->dw_msaa;
105 }
106 else {
107 payload[0] = 0;
108 payload[1] = (num_samples > 1) ? GEN7_SF_DW2_MSRASTMODE_ON_PATTERN : 0;
109 payload[2] = 0;
110 payload[3] = 0;
111 payload[4] = 0;
112 payload[5] = 0;
113 }
114
115 if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
116 int format;
117
118 /* separate stencil */
119 switch (depth_format) {
120 case PIPE_FORMAT_Z16_UNORM:
121 format = GEN6_ZFORMAT_D16_UNORM;
122 break;
123 case PIPE_FORMAT_Z32_FLOAT:
124 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
125 format = GEN6_ZFORMAT_D32_FLOAT;
126 break;
127 case PIPE_FORMAT_Z24X8_UNORM:
128 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
129 format = GEN6_ZFORMAT_D24_UNORM_X8_UINT;
130 break;
131 default:
132 /* FLOAT surface is assumed when there is no depth buffer */
133 format = GEN6_ZFORMAT_D32_FLOAT;
134 break;
135 }
136
137 payload[0] |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT;
138 }
139 }
140
141 /**
142 * Fill in DW1 and DW8 to DW19 of 3DSTATE_SF.
143 */
144 static inline void
145 ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
146 const struct ilo_rasterizer_state *rasterizer,
147 const struct ilo_shader_state *fs,
148 uint32_t *dw, int num_dwords)
149 {
150 int output_count, vue_offset, vue_len;
151 const struct ilo_kernel_routing *routing;
152
153 ILO_DEV_ASSERT(dev, 6, 7.5);
154 assert(num_dwords == 13);
155
156 if (!fs) {
157 memset(dw, 0, sizeof(dw[0]) * num_dwords);
158 dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
159 return;
160 }
161
162 output_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT);
163 assert(output_count <= 32);
164
165 routing = ilo_shader_get_kernel_routing(fs);
166
167 vue_offset = routing->source_skip;
168 assert(vue_offset % 2 == 0);
169 vue_offset /= 2;
170
171 vue_len = (routing->source_len + 1) / 2;
172 if (!vue_len)
173 vue_len = 1;
174
175 dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
176 vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT |
177 vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
178 if (routing->swizzle_enable)
179 dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
180
181 switch (rasterizer->state.sprite_coord_mode) {
182 case PIPE_SPRITE_COORD_UPPER_LEFT:
183 dw[0] |= GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT;
184 break;
185 case PIPE_SPRITE_COORD_LOWER_LEFT:
186 dw[0] |= GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT;
187 break;
188 }
189
190 STATIC_ASSERT(Elements(routing->swizzles) >= 16);
191 memcpy(&dw[1], routing->swizzles, 2 * 16);
192
193 /*
194 * From the Ivy Bridge PRM, volume 2 part 1, page 268:
195 *
196 * "This field (Point Sprite Texture Coordinate Enable) must be
197 * programmed to 0 when non-point primitives are rendered."
198 *
199 * TODO We do not check that yet.
200 */
201 dw[9] = routing->point_sprite_enable;
202
203 dw[10] = routing->const_interp_enable;
204
205 /* WrapShortest enables */
206 dw[11] = 0;
207 dw[12] = 0;
208 }
209
210 static inline void
211 gen6_3DSTATE_SF(struct ilo_builder *builder,
212 const struct ilo_rasterizer_state *rasterizer,
213 const struct ilo_shader_state *fs)
214 {
215 const uint8_t cmd_len = 20;
216 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
217 uint32_t payload_raster[6], payload_sbe[13], *dw;
218
219 ILO_DEV_ASSERT(builder->dev, 6, 6);
220
221 ilo_gpe_gen6_fill_3dstate_sf_raster(builder->dev, rasterizer,
222 1, PIPE_FORMAT_NONE, payload_raster, Elements(payload_raster));
223 ilo_gpe_gen6_fill_3dstate_sf_sbe(builder->dev, rasterizer,
224 fs, payload_sbe, Elements(payload_sbe));
225
226 ilo_builder_batch_pointer(builder, cmd_len, &dw);
227 dw[0] = dw0;
228 dw[1] = payload_sbe[0];
229 memcpy(&dw[2], payload_raster, sizeof(payload_raster));
230 memcpy(&dw[8], &payload_sbe[1], sizeof(payload_sbe) - 4);
231 }
232
233 static inline void
234 gen7_3DSTATE_SF(struct ilo_builder *builder,
235 const struct ilo_rasterizer_state *rasterizer,
236 enum pipe_format zs_format)
237 {
238 const uint8_t cmd_len = 7;
239 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
240 const int num_samples = 1;
241 uint32_t payload[6], *dw;
242
243 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
244
245 ilo_gpe_gen6_fill_3dstate_sf_raster(builder->dev,
246 rasterizer, num_samples, zs_format,
247 payload, Elements(payload));
248
249 ilo_builder_batch_pointer(builder, cmd_len, &dw);
250 dw[0] = dw0;
251 memcpy(&dw[1], payload, sizeof(payload));
252 }
253
254 static inline void
255 gen7_3DSTATE_SBE(struct ilo_builder *builder,
256 const struct ilo_rasterizer_state *rasterizer,
257 const struct ilo_shader_state *fs)
258 {
259 const uint8_t cmd_len = 14;
260 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
261 uint32_t payload[13], *dw;
262
263 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
264
265 ilo_gpe_gen6_fill_3dstate_sf_sbe(builder->dev,
266 rasterizer, fs, payload, Elements(payload));
267
268 ilo_builder_batch_pointer(builder, cmd_len, &dw);
269 dw[0] = dw0;
270 memcpy(&dw[1], payload, sizeof(payload));
271 }
272
273 static inline void
274 gen6_3DSTATE_WM(struct ilo_builder *builder,
275 const struct ilo_shader_state *fs,
276 int num_samplers,
277 const struct ilo_rasterizer_state *rasterizer,
278 bool dual_blend, bool cc_may_kill,
279 uint32_t hiz_op)
280 {
281 const uint8_t cmd_len = 9;
282 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
283 const int num_samples = 1;
284 const struct ilo_shader_cso *fs_cso;
285 uint32_t dw2, dw4, dw5, dw6, *dw;
286
287 ILO_DEV_ASSERT(builder->dev, 6, 6);
288
289 if (!fs) {
290 /* see brwCreateContext() */
291 const int max_threads = (builder->dev->gt == 2) ? 80 : 40;
292
293 ilo_builder_batch_pointer(builder, cmd_len, &dw);
294 dw[0] = dw0;
295 dw[1] = 0;
296 dw[2] = 0;
297 dw[3] = 0;
298 dw[4] = hiz_op;
299 /* honor the valid range even if dispatching is disabled */
300 dw[5] = (max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT;
301 dw[6] = 0;
302 dw[7] = 0;
303 dw[8] = 0;
304
305 return;
306 }
307
308 fs_cso = ilo_shader_get_kernel_cso(fs);
309 dw2 = fs_cso->payload[0];
310 dw4 = fs_cso->payload[1];
311 dw5 = fs_cso->payload[2];
312 dw6 = fs_cso->payload[3];
313
314 dw2 |= (num_samplers + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
315
316 /*
317 * From the Sandy Bridge PRM, volume 2 part 1, page 248:
318 *
319 * "This bit (Statistics Enable) must be disabled if either of these
320 * bits is set: Depth Buffer Clear , Hierarchical Depth Buffer Resolve
321 * Enable or Depth Buffer Resolve Enable."
322 */
323 assert(!hiz_op);
324 dw4 |= GEN6_WM_DW4_STATISTICS;
325
326 if (cc_may_kill)
327 dw5 |= GEN6_WM_DW5_PS_KILL | GEN6_WM_DW5_PS_ENABLE;
328
329 if (dual_blend)
330 dw5 |= GEN6_WM_DW5_DUAL_SOURCE_BLEND;
331
332 dw5 |= rasterizer->wm.payload[0];
333
334 dw6 |= rasterizer->wm.payload[1];
335
336 if (num_samples > 1) {
337 dw6 |= rasterizer->wm.dw_msaa_rast |
338 rasterizer->wm.dw_msaa_disp;
339 }
340
341 ilo_builder_batch_pointer(builder, cmd_len, &dw);
342 dw[0] = dw0;
343 dw[1] = ilo_shader_get_kernel_offset(fs);
344 dw[2] = dw2;
345 dw[3] = 0; /* scratch */
346 dw[4] = dw4;
347 dw[5] = dw5;
348 dw[6] = dw6;
349 dw[7] = 0; /* kernel 1 */
350 dw[8] = 0; /* kernel 2 */
351 }
352
353 static inline void
354 gen7_3DSTATE_WM(struct ilo_builder *builder,
355 const struct ilo_shader_state *fs,
356 const struct ilo_rasterizer_state *rasterizer,
357 bool cc_may_kill, uint32_t hiz_op)
358 {
359 const uint8_t cmd_len = 3;
360 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
361 const int num_samples = 1;
362 uint32_t dw1, dw2, *dw;
363
364 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
365
366 /* see ilo_gpe_init_rasterizer_wm() */
367 if (rasterizer) {
368 dw1 = rasterizer->wm.payload[0];
369 dw2 = rasterizer->wm.payload[1];
370
371 assert(!hiz_op);
372 dw1 |= GEN7_WM_DW1_STATISTICS;
373 }
374 else {
375 dw1 = hiz_op;
376 dw2 = 0;
377 }
378
379 if (fs) {
380 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
381
382 dw1 |= fs_cso->payload[3];
383 }
384
385 if (cc_may_kill)
386 dw1 |= GEN7_WM_DW1_PS_ENABLE | GEN7_WM_DW1_PS_KILL;
387
388 if (num_samples > 1) {
389 dw1 |= rasterizer->wm.dw_msaa_rast;
390 dw2 |= rasterizer->wm.dw_msaa_disp;
391 }
392
393 ilo_builder_batch_pointer(builder, cmd_len, &dw);
394 dw[0] = dw0;
395 dw[1] = dw1;
396 dw[2] = dw2;
397 }
398
399 static inline void
400 gen7_3DSTATE_PS(struct ilo_builder *builder,
401 const struct ilo_shader_state *fs,
402 int num_samplers, bool dual_blend)
403 {
404 const uint8_t cmd_len = 8;
405 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
406 const struct ilo_shader_cso *cso;
407 uint32_t dw2, dw4, dw5, *dw;
408
409 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
410
411 if (!fs) {
412 int max_threads;
413
414 /* GPU hangs if none of the dispatch enable bits is set */
415 dw4 = GEN7_PS_DW4_8_PIXEL_DISPATCH;
416
417 /* see brwCreateContext() */
418 switch (ilo_dev_gen(builder->dev)) {
419 case ILO_GEN(7.5):
420 max_threads = (builder->dev->gt == 3) ? 408 :
421 (builder->dev->gt == 2) ? 204 : 102;
422 dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
423 break;
424 case ILO_GEN(7):
425 default:
426 max_threads = (builder->dev->gt == 2) ? 172 : 48;
427 dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
428 break;
429 }
430
431 ilo_builder_batch_pointer(builder, cmd_len, &dw);
432 dw[0] = dw0;
433 dw[1] = 0;
434 dw[2] = 0;
435 dw[3] = 0;
436 dw[4] = dw4;
437 dw[5] = 0;
438 dw[6] = 0;
439 dw[7] = 0;
440
441 return;
442 }
443
444 cso = ilo_shader_get_kernel_cso(fs);
445 dw2 = cso->payload[0];
446 dw4 = cso->payload[1];
447 dw5 = cso->payload[2];
448
449 dw2 |= (num_samplers + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
450
451 if (dual_blend)
452 dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
453
454 ilo_builder_batch_pointer(builder, cmd_len, &dw);
455 dw[0] = dw0;
456 dw[1] = ilo_shader_get_kernel_offset(fs);
457 dw[2] = dw2;
458 dw[3] = 0; /* scratch */
459 dw[4] = dw4;
460 dw[5] = dw5;
461 dw[6] = 0; /* kernel 1 */
462 dw[7] = 0; /* kernel 2 */
463 }
464
465 static inline void
466 gen6_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
467 const uint32_t *bufs, const int *sizes,
468 int num_bufs)
469 {
470 const uint8_t cmd_len = 5;
471 uint32_t buf_dw[4], buf_enabled;
472 uint32_t dw0, *dw;
473
474 ILO_DEV_ASSERT(builder->dev, 6, 6);
475 assert(num_bufs <= 4);
476
477 /*
478 * From the Sandy Bridge PRM, volume 2 part 1, page 287:
479 *
480 * "The sum of all four read length fields (each incremented to
481 * represent the actual read length) must be less than or equal to 64"
482 */
483 buf_enabled = gen6_fill_3dstate_constant(builder->dev,
484 bufs, sizes, num_bufs, 64, buf_dw, Elements(buf_dw));
485
486 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) |
487 buf_enabled << 12 |
488 (cmd_len - 2);
489
490 ilo_builder_batch_pointer(builder, cmd_len, &dw);
491 dw[0] = dw0;
492 memcpy(&dw[1], buf_dw, sizeof(buf_dw));
493 }
494
495 static inline void
496 gen7_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
497 const uint32_t *bufs, const int *sizes,
498 int num_bufs)
499 {
500 gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
501 bufs, sizes, num_bufs);
502 }
503
504 static inline void
505 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(struct ilo_builder *builder,
506 uint32_t binding_table)
507 {
508 gen7_3dstate_pointer(builder,
509 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
510 binding_table);
511 }
512
513 static inline void
514 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(struct ilo_builder *builder,
515 uint32_t sampler_state)
516 {
517 gen7_3dstate_pointer(builder,
518 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
519 sampler_state);
520 }
521
522 static inline void
523 gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
524 int num_samples,
525 const uint32_t *packed_sample_pos,
526 bool pixel_location_center)
527 {
528 const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 3;
529 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) |
530 (cmd_len - 2);
531 uint32_t dw1, dw2, dw3, *dw;
532
533 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
534
535 dw1 = (pixel_location_center) ?
536 GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER : GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER;
537
538 switch (num_samples) {
539 case 0:
540 case 1:
541 dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
542 dw2 = 0;
543 dw3 = 0;
544 break;
545 case 4:
546 dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
547 dw2 = packed_sample_pos[0];
548 dw3 = 0;
549 break;
550 case 8:
551 assert(ilo_dev_gen(builder->dev) >= ILO_GEN(7));
552 dw1 |= GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
553 dw2 = packed_sample_pos[0];
554 dw3 = packed_sample_pos[1];
555 break;
556 default:
557 assert(!"unsupported sample count");
558 dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
559 dw2 = 0;
560 dw3 = 0;
561 break;
562 }
563
564 ilo_builder_batch_pointer(builder, cmd_len, &dw);
565 dw[0] = dw0;
566 dw[1] = dw1;
567 dw[2] = dw2;
568 if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
569 dw[2] = dw3;
570 }
571
572 static inline void
573 gen6_3DSTATE_SAMPLE_MASK(struct ilo_builder *builder,
574 unsigned sample_mask)
575 {
576 const uint8_t cmd_len = 2;
577 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) |
578 (cmd_len - 2);
579 const unsigned valid_mask = 0xf;
580 uint32_t *dw;
581
582 ILO_DEV_ASSERT(builder->dev, 6, 6);
583
584 sample_mask &= valid_mask;
585
586 ilo_builder_batch_pointer(builder, cmd_len, &dw);
587 dw[0] = dw0;
588 dw[1] = sample_mask;
589 }
590
591 static inline void
592 gen7_3DSTATE_SAMPLE_MASK(struct ilo_builder *builder,
593 unsigned sample_mask,
594 int num_samples)
595 {
596 const uint8_t cmd_len = 2;
597 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
598 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) |
599 (cmd_len - 2);
600 uint32_t *dw;
601
602 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
603
604 /*
605 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
606 *
607 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
608 * (Sample Mask) must be zero.
609 *
610 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
611 * must be zero."
612 */
613 sample_mask &= valid_mask;
614
615 ilo_builder_batch_pointer(builder, cmd_len, &dw);
616 dw[0] = dw0;
617 dw[1] = sample_mask;
618 }
619
620 static inline void
621 gen6_3DSTATE_DRAWING_RECTANGLE(struct ilo_builder *builder,
622 unsigned x, unsigned y,
623 unsigned width, unsigned height)
624 {
625 const uint8_t cmd_len = 4;
626 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) |
627 (cmd_len - 2);
628 unsigned xmax = x + width - 1;
629 unsigned ymax = y + height - 1;
630 int rect_limit;
631 uint32_t *dw;
632
633 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
634
635 if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
636 rect_limit = 16383;
637 }
638 else {
639 /*
640 * From the Sandy Bridge PRM, volume 2 part 1, page 230:
641 *
642 * "[DevSNB] Errata: This field (Clipped Drawing Rectangle Y Min)
643 * must be an even number"
644 */
645 assert(y % 2 == 0);
646
647 rect_limit = 8191;
648 }
649
650 if (x > rect_limit) x = rect_limit;
651 if (y > rect_limit) y = rect_limit;
652 if (xmax > rect_limit) xmax = rect_limit;
653 if (ymax > rect_limit) ymax = rect_limit;
654
655 ilo_builder_batch_pointer(builder, cmd_len, &dw);
656
657 dw[0] = dw0;
658 dw[1] = y << 16 | x;
659 dw[2] = ymax << 16 | xmax;
660
661 /*
662 * There is no need to set the origin. It is intended to support front
663 * buffer rendering.
664 */
665 dw[3] = 0;
666 }
667
668 static inline void
669 gen6_3DSTATE_POLY_STIPPLE_OFFSET(struct ilo_builder *builder,
670 int x_offset, int y_offset)
671 {
672 const uint8_t cmd_len = 2;
673 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET) |
674 (cmd_len - 2);
675 uint32_t *dw;
676
677 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
678 assert(x_offset >= 0 && x_offset <= 31);
679 assert(y_offset >= 0 && y_offset <= 31);
680
681 ilo_builder_batch_pointer(builder, cmd_len, &dw);
682 dw[0] = dw0;
683 dw[1] = x_offset << 8 | y_offset;
684 }
685
686 static inline void
687 gen6_3DSTATE_POLY_STIPPLE_PATTERN(struct ilo_builder *builder,
688 const struct pipe_poly_stipple *pattern)
689 {
690 const uint8_t cmd_len = 33;
691 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN) |
692 (cmd_len - 2);
693 uint32_t *dw;
694 int i;
695
696 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
697 STATIC_ASSERT(Elements(pattern->stipple) == 32);
698
699 ilo_builder_batch_pointer(builder, cmd_len, &dw);
700 dw[0] = dw0;
701 dw++;
702
703 for (i = 0; i < 32; i++)
704 dw[i] = pattern->stipple[i];
705 }
706
707 static inline void
708 gen6_3DSTATE_LINE_STIPPLE(struct ilo_builder *builder,
709 unsigned pattern, unsigned factor)
710 {
711 const uint8_t cmd_len = 3;
712 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE) |
713 (cmd_len - 2);
714 uint32_t *dw;
715 unsigned inverse;
716
717 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
718 assert((pattern & 0xffff) == pattern);
719 assert(factor >= 1 && factor <= 256);
720
721 ilo_builder_batch_pointer(builder, cmd_len, &dw);
722 dw[0] = dw0;
723 dw[1] = pattern;
724
725 if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
726 /* in U1.16 */
727 inverse = (unsigned) (65536.0f / factor);
728 dw[2] = inverse << 15 | factor;
729 }
730 else {
731 /* in U1.13 */
732 inverse = (unsigned) (8192.0f / factor);
733 dw[2] = inverse << 16 | factor;
734 }
735 }
736
737 static inline void
738 gen6_3DSTATE_AA_LINE_PARAMETERS(struct ilo_builder *builder)
739 {
740 const uint8_t cmd_len = 3;
741 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) |
742 (cmd_len - 2);
743 uint32_t *dw;
744
745 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
746
747 ilo_builder_batch_pointer(builder, cmd_len, &dw);
748 dw[0] = dw0;
749 dw[1] = 0 << 16 | 0;
750 dw[2] = 0 << 16 | 0;
751 }
752
753 static inline void
754 gen6_3DSTATE_DEPTH_BUFFER(struct ilo_builder *builder,
755 const struct ilo_zs_surface *zs)
756 {
757 const uint8_t cmd_len = 7;
758 unsigned pos;
759 uint32_t dw0, *dw;
760
761 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
762
763 dw0 = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
764 GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
765 GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
766 dw0 |= (cmd_len - 2);
767
768 pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
769 dw[0] = dw0;
770 dw[1] = zs->payload[0];
771
772 if (zs->bo) {
773 ilo_builder_batch_reloc(builder, pos + 2,
774 zs->bo, zs->payload[1], INTEL_RELOC_WRITE);
775 } else {
776 dw[2] = 0;
777 }
778
779 dw[3] = zs->payload[2];
780 dw[4] = zs->payload[3];
781 dw[5] = zs->payload[4];
782 dw[6] = zs->payload[5];
783 }
784
785 static inline void
786 gen6_3DSTATE_STENCIL_BUFFER(struct ilo_builder *builder,
787 const struct ilo_zs_surface *zs)
788 {
789 const uint8_t cmd_len = 3;
790 uint32_t dw0, *dw;
791 unsigned pos;
792
793 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
794
795 dw0 = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
796 GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
797 GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
798 dw0 |= (cmd_len - 2);
799
800 pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
801 dw[0] = dw0;
802 /* see ilo_gpe_init_zs_surface() */
803 dw[1] = zs->payload[6];
804
805 if (zs->separate_s8_bo) {
806 ilo_builder_batch_reloc(builder, pos + 2,
807 zs->separate_s8_bo, zs->payload[7], INTEL_RELOC_WRITE);
808 } else {
809 dw[2] = 0;
810 }
811 }
812
813 static inline void
814 gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_builder *builder,
815 const struct ilo_zs_surface *zs)
816 {
817 const uint8_t cmd_len = 3;
818 uint32_t dw0, *dw;
819 unsigned pos;
820
821 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
822
823 dw0 = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
824 GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
825 GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
826 dw0 |= (cmd_len - 2);
827
828 pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
829 dw[0] = dw0;
830 /* see ilo_gpe_init_zs_surface() */
831 dw[1] = zs->payload[8];
832
833 if (zs->hiz_bo) {
834 ilo_builder_batch_reloc(builder, pos + 2,
835 zs->hiz_bo, zs->payload[9], INTEL_RELOC_WRITE);
836 } else {
837 dw[2] = 0;
838 }
839 }
840
841 static inline void
842 gen6_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
843 uint32_t clear_val)
844 {
845 const uint8_t cmd_len = 2;
846 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
847 GEN6_CLEAR_PARAMS_DW0_VALID |
848 (cmd_len - 2);
849 uint32_t *dw;
850
851 ILO_DEV_ASSERT(builder->dev, 6, 6);
852
853 ilo_builder_batch_pointer(builder, cmd_len, &dw);
854 dw[0] = dw0;
855 dw[1] = clear_val;
856 }
857
858 static inline void
859 gen7_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
860 uint32_t clear_val)
861 {
862 const uint8_t cmd_len = 3;
863 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
864 (cmd_len - 2);
865 uint32_t *dw;
866
867 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
868
869 ilo_builder_batch_pointer(builder, cmd_len, &dw);
870 dw[0] = dw0;
871 dw[1] = clear_val;
872 dw[2] = 1;
873 }
874
875 static inline void
876 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct ilo_builder *builder,
877 uint32_t clip_viewport,
878 uint32_t sf_viewport,
879 uint32_t cc_viewport)
880 {
881 const uint8_t cmd_len = 4;
882 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) |
883 GEN6_PTR_VP_DW0_CLIP_CHANGED |
884 GEN6_PTR_VP_DW0_SF_CHANGED |
885 GEN6_PTR_VP_DW0_CC_CHANGED |
886 (cmd_len - 2);
887 uint32_t *dw;
888
889 ILO_DEV_ASSERT(builder->dev, 6, 6);
890
891 ilo_builder_batch_pointer(builder, cmd_len, &dw);
892 dw[0] = dw0;
893 dw[1] = clip_viewport;
894 dw[2] = sf_viewport;
895 dw[3] = cc_viewport;
896 }
897
898 static inline void
899 gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct ilo_builder *builder,
900 uint32_t scissor_rect)
901 {
902 const uint8_t cmd_len = 2;
903 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS) |
904 (cmd_len - 2);
905 uint32_t *dw;
906
907 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
908
909 ilo_builder_batch_pointer(builder, cmd_len, &dw);
910 dw[0] = dw0;
911 dw[1] = scissor_rect;
912 }
913
914 static inline void
915 gen6_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
916 uint32_t blend_state,
917 uint32_t depth_stencil_state,
918 uint32_t color_calc_state)
919 {
920 const uint8_t cmd_len = 4;
921 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS) |
922 (cmd_len - 2);
923 uint32_t *dw;
924
925 ILO_DEV_ASSERT(builder->dev, 6, 6);
926
927 ilo_builder_batch_pointer(builder, cmd_len, &dw);
928 dw[0] = dw0;
929 dw[1] = blend_state | 1;
930 dw[2] = depth_stencil_state | 1;
931 dw[3] = color_calc_state | 1;
932 }
933
934 static inline void
935 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(struct ilo_builder *builder,
936 uint32_t sf_clip_viewport)
937 {
938 gen7_3dstate_pointer(builder,
939 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
940 sf_clip_viewport);
941 }
942
943 static inline void
944 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(struct ilo_builder *builder,
945 uint32_t cc_viewport)
946 {
947 gen7_3dstate_pointer(builder,
948 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
949 cc_viewport);
950 }
951
952 static inline void
953 gen7_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
954 uint32_t color_calc_state)
955 {
956 gen7_3dstate_pointer(builder,
957 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, color_calc_state);
958 }
959
960 static inline void
961 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(struct ilo_builder *builder,
962 uint32_t depth_stencil_state)
963 {
964 gen7_3dstate_pointer(builder,
965 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
966 depth_stencil_state);
967 }
968
969 static inline void
970 gen7_3DSTATE_BLEND_STATE_POINTERS(struct ilo_builder *builder,
971 uint32_t blend_state)
972 {
973 gen7_3dstate_pointer(builder,
974 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
975 blend_state);
976 }
977
978 static inline uint32_t
979 gen6_CLIP_VIEWPORT(struct ilo_builder *builder,
980 const struct ilo_viewport_cso *viewports,
981 unsigned num_viewports)
982 {
983 const int state_align = 32;
984 const int state_len = 4 * num_viewports;
985 uint32_t state_offset, *dw;
986 unsigned i;
987
988 ILO_DEV_ASSERT(builder->dev, 6, 6);
989
990 /*
991 * From the Sandy Bridge PRM, volume 2 part 1, page 193:
992 *
993 * "The viewport-related state is stored as an array of up to 16
994 * elements..."
995 */
996 assert(num_viewports && num_viewports <= 16);
997
998 state_offset = ilo_builder_state_pointer(builder,
999 ILO_BUILDER_ITEM_CLIP_VIEWPORT, state_align, state_len, &dw);
1000
1001 for (i = 0; i < num_viewports; i++) {
1002 const struct ilo_viewport_cso *vp = &viewports[i];
1003
1004 dw[0] = fui(vp->min_gbx);
1005 dw[1] = fui(vp->max_gbx);
1006 dw[2] = fui(vp->min_gby);
1007 dw[3] = fui(vp->max_gby);
1008
1009 dw += 4;
1010 }
1011
1012 return state_offset;
1013 }
1014
1015 static inline uint32_t
1016 gen6_SF_VIEWPORT(struct ilo_builder *builder,
1017 const struct ilo_viewport_cso *viewports,
1018 unsigned num_viewports)
1019 {
1020 const int state_align = 32;
1021 const int state_len = 8 * num_viewports;
1022 uint32_t state_offset, *dw;
1023 unsigned i;
1024
1025 ILO_DEV_ASSERT(builder->dev, 6, 6);
1026
1027 /*
1028 * From the Sandy Bridge PRM, volume 2 part 1, page 262:
1029 *
1030 * "The viewport-specific state used by the SF unit (SF_VIEWPORT) is
1031 * stored as an array of up to 16 elements..."
1032 */
1033 assert(num_viewports && num_viewports <= 16);
1034
1035 state_offset = ilo_builder_state_pointer(builder,
1036 ILO_BUILDER_ITEM_SF_VIEWPORT, state_align, state_len, &dw);
1037
1038 for (i = 0; i < num_viewports; i++) {
1039 const struct ilo_viewport_cso *vp = &viewports[i];
1040
1041 dw[0] = fui(vp->m00);
1042 dw[1] = fui(vp->m11);
1043 dw[2] = fui(vp->m22);
1044 dw[3] = fui(vp->m30);
1045 dw[4] = fui(vp->m31);
1046 dw[5] = fui(vp->m32);
1047 dw[6] = 0;
1048 dw[7] = 0;
1049
1050 dw += 8;
1051 }
1052
1053 return state_offset;
1054 }
1055
1056 static inline uint32_t
1057 gen7_SF_CLIP_VIEWPORT(struct ilo_builder *builder,
1058 const struct ilo_viewport_cso *viewports,
1059 unsigned num_viewports)
1060 {
1061 const int state_align = 64;
1062 const int state_len = 16 * num_viewports;
1063 uint32_t state_offset, *dw;
1064 unsigned i;
1065
1066 ILO_DEV_ASSERT(builder->dev, 7, 7.5);
1067
1068 /*
1069 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1070 *
1071 * "The viewport-specific state used by both the SF and CL units
1072 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1073 * of which contains the DWords described below. The start of each
1074 * element is spaced 16 DWords apart. The location of first element of
1075 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1076 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1077 */
1078 assert(num_viewports && num_viewports <= 16);
1079
1080 state_offset = ilo_builder_state_pointer(builder,
1081 ILO_BUILDER_ITEM_SF_VIEWPORT, state_align, state_len, &dw);
1082
1083 for (i = 0; i < num_viewports; i++) {
1084 const struct ilo_viewport_cso *vp = &viewports[i];
1085
1086 dw[0] = fui(vp->m00);
1087 dw[1] = fui(vp->m11);
1088 dw[2] = fui(vp->m22);
1089 dw[3] = fui(vp->m30);
1090 dw[4] = fui(vp->m31);
1091 dw[5] = fui(vp->m32);
1092 dw[6] = 0;
1093 dw[7] = 0;
1094 dw[8] = fui(vp->min_gbx);
1095 dw[9] = fui(vp->max_gbx);
1096 dw[10] = fui(vp->min_gby);
1097 dw[11] = fui(vp->max_gby);
1098 dw[12] = 0;
1099 dw[13] = 0;
1100 dw[14] = 0;
1101 dw[15] = 0;
1102
1103 dw += 16;
1104 }
1105
1106 return state_offset;
1107 }
1108
1109 static inline uint32_t
1110 gen6_CC_VIEWPORT(struct ilo_builder *builder,
1111 const struct ilo_viewport_cso *viewports,
1112 unsigned num_viewports)
1113 {
1114 const int state_align = 32;
1115 const int state_len = 2 * num_viewports;
1116 uint32_t state_offset, *dw;
1117 unsigned i;
1118
1119 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1120
1121 /*
1122 * From the Sandy Bridge PRM, volume 2 part 1, page 385:
1123 *
1124 * "The viewport state is stored as an array of up to 16 elements..."
1125 */
1126 assert(num_viewports && num_viewports <= 16);
1127
1128 state_offset = ilo_builder_state_pointer(builder,
1129 ILO_BUILDER_ITEM_CC_VIEWPORT, state_align, state_len, &dw);
1130
1131 for (i = 0; i < num_viewports; i++) {
1132 const struct ilo_viewport_cso *vp = &viewports[i];
1133
1134 dw[0] = fui(vp->min_z);
1135 dw[1] = fui(vp->max_z);
1136
1137 dw += 2;
1138 }
1139
1140 return state_offset;
1141 }
1142
1143 static inline uint32_t
1144 gen6_SCISSOR_RECT(struct ilo_builder *builder,
1145 const struct ilo_scissor_state *scissor,
1146 unsigned num_viewports)
1147 {
1148 const int state_align = 32;
1149 const int state_len = 2 * num_viewports;
1150
1151 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1152
1153 /*
1154 * From the Sandy Bridge PRM, volume 2 part 1, page 263:
1155 *
1156 * "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
1157 * stored as an array of up to 16 elements..."
1158 */
1159 assert(num_viewports && num_viewports <= 16);
1160 assert(Elements(scissor->payload) >= state_len);
1161
1162 return ilo_builder_state_write(builder, ILO_BUILDER_ITEM_SCISSOR_RECT,
1163 state_align, state_len, scissor->payload);
1164 }
1165
1166 static inline uint32_t
1167 gen6_COLOR_CALC_STATE(struct ilo_builder *builder,
1168 const struct pipe_stencil_ref *stencil_ref,
1169 ubyte alpha_ref,
1170 const struct pipe_blend_color *blend_color)
1171 {
1172 const int state_align = 64;
1173 const int state_len = 6;
1174 uint32_t state_offset, *dw;
1175
1176 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1177
1178 state_offset = ilo_builder_state_pointer(builder,
1179 ILO_BUILDER_ITEM_COLOR_CALC, state_align, state_len, &dw);
1180
1181 dw[0] = stencil_ref->ref_value[0] << 24 |
1182 stencil_ref->ref_value[1] << 16 |
1183 GEN6_CC_DW0_ALPHATEST_UNORM8;
1184 dw[1] = alpha_ref;
1185 dw[2] = fui(blend_color->color[0]);
1186 dw[3] = fui(blend_color->color[1]);
1187 dw[4] = fui(blend_color->color[2]);
1188 dw[5] = fui(blend_color->color[3]);
1189
1190 return state_offset;
1191 }
1192
1193 static inline uint32_t
1194 gen6_DEPTH_STENCIL_STATE(struct ilo_builder *builder,
1195 const struct ilo_dsa_state *dsa)
1196 {
1197 const int state_align = 64;
1198 const int state_len = 3;
1199
1200 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1201
1202 STATIC_ASSERT(Elements(dsa->payload) >= state_len);
1203
1204 return ilo_builder_state_write(builder, ILO_BUILDER_ITEM_DEPTH_STENCIL,
1205 state_align, state_len, dsa->payload);
1206 }
1207
1208 static inline uint32_t
1209 gen6_BLEND_STATE(struct ilo_builder *builder,
1210 const struct ilo_blend_state *blend,
1211 const struct ilo_fb_state *fb,
1212 const struct ilo_dsa_state *dsa)
1213 {
1214 const int state_align = 64;
1215 int state_len;
1216 uint32_t state_offset, *dw;
1217 unsigned num_targets, i;
1218
1219 ILO_DEV_ASSERT(builder->dev, 6, 7.5);
1220
1221 /*
1222 * From the Sandy Bridge PRM, volume 2 part 1, page 376:
1223 *
1224 * "The blend state is stored as an array of up to 8 elements..."
1225 */
1226 num_targets = fb->state.nr_cbufs;
1227 assert(num_targets <= 8);
1228
1229 if (!num_targets) {
1230 if (!dsa->dw_alpha)
1231 return 0;
1232 /* to be able to reference alpha func */
1233 num_targets = 1;
1234 }
1235
1236 state_len = 2 * num_targets;
1237
1238 state_offset = ilo_builder_state_pointer(builder,
1239 ILO_BUILDER_ITEM_BLEND, state_align, state_len, &dw);
1240
1241 for (i = 0; i < num_targets; i++) {
1242 const unsigned idx = (blend->independent_blend_enable) ? i : 0;
1243 const struct ilo_blend_cso *cso = &blend->cso[idx];
1244 const int num_samples = fb->num_samples;
1245 const struct util_format_description *format_desc =
1246 (idx < fb->state.nr_cbufs && fb->state.cbufs[idx]) ?
1247 util_format_description(fb->state.cbufs[idx]->format) : NULL;
1248 bool rt_is_unorm, rt_is_pure_integer, rt_dst_alpha_forced_one;
1249
1250 rt_is_unorm = true;
1251 rt_is_pure_integer = false;
1252 rt_dst_alpha_forced_one = false;
1253
1254 if (format_desc) {
1255 int ch;
1256
1257 switch (format_desc->format) {
1258 case PIPE_FORMAT_B8G8R8X8_UNORM:
1259 /* force alpha to one when the HW format has alpha */
1260 assert(ilo_translate_render_format(builder->dev,
1261 PIPE_FORMAT_B8G8R8X8_UNORM) ==
1262 GEN6_FORMAT_B8G8R8A8_UNORM);
1263 rt_dst_alpha_forced_one = true;
1264 break;
1265 default:
1266 break;
1267 }
1268
1269 for (ch = 0; ch < 4; ch++) {
1270 if (format_desc->channel[ch].type == UTIL_FORMAT_TYPE_VOID)
1271 continue;
1272
1273 if (format_desc->channel[ch].pure_integer) {
1274 rt_is_unorm = false;
1275 rt_is_pure_integer = true;
1276 break;
1277 }
1278
1279 if (!format_desc->channel[ch].normalized ||
1280 format_desc->channel[ch].type != UTIL_FORMAT_TYPE_UNSIGNED)
1281 rt_is_unorm = false;
1282 }
1283 }
1284
1285 dw[0] = cso->payload[0];
1286 dw[1] = cso->payload[1];
1287
1288 if (!rt_is_pure_integer) {
1289 if (rt_dst_alpha_forced_one)
1290 dw[0] |= cso->dw_blend_dst_alpha_forced_one;
1291 else
1292 dw[0] |= cso->dw_blend;
1293 }
1294
1295 /*
1296 * From the Sandy Bridge PRM, volume 2 part 1, page 365:
1297 *
1298 * "Logic Ops are only supported on *_UNORM surfaces (excluding
1299 * _SRGB variants), otherwise Logic Ops must be DISABLED."
1300 *
1301 * Since logicop is ignored for non-UNORM color buffers, no special care
1302 * is needed.
1303 */
1304 if (rt_is_unorm)
1305 dw[1] |= cso->dw_logicop;
1306
1307 /*
1308 * From the Sandy Bridge PRM, volume 2 part 1, page 356:
1309 *
1310 * "When NumSamples = 1, AlphaToCoverage and AlphaToCoverage
1311 * Dither both must be disabled."
1312 *
1313 * There is no such limitation on GEN7, or for AlphaToOne. But GL
1314 * requires that anyway.
1315 */
1316 if (num_samples > 1)
1317 dw[1] |= cso->dw_alpha_mod;
1318
1319 /*
1320 * From the Sandy Bridge PRM, volume 2 part 1, page 382:
1321 *
1322 * "Alpha Test can only be enabled if Pixel Shader outputs a float
1323 * alpha value."
1324 */
1325 if (!rt_is_pure_integer)
1326 dw[1] |= dsa->dw_alpha;
1327
1328 dw += 2;
1329 }
1330
1331 return state_offset;
1332 }
1333
1334 #endif /* ILO_BUILDER_3D_BOTTOM_H */