src/gallium/drivers/ilo/ilo_builder_mi.h

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2014 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #ifndef ILO_BUILDER_MI_H
  29 #define ILO_BUILDER_MI_H
  30
  31 #include "genhw/genhw.h"
  32 #include "intel_winsys.h"
  33
  34 #include "ilo_common.h"
  35 #include "ilo_builder.h"
  36
  37 static inline void
  38 gen6_MI_STORE_DATA_IMM(struct ilo_builder *builder,
  39                        struct intel_bo *bo, uint32_t bo_offset,
  40                        uint64_t val)
  41 {
  42    const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
  43    uint32_t reloc_flags = INTEL_RELOC_WRITE;
  44    uint32_t *dw;
  45    unsigned pos;
  46
  47    ILO_DEV_ASSERT(builder->dev, 6, 8);
  48
  49    assert(bo_offset % 8 == 0);
  50
  51    pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
  52
  53    dw[0] = GEN6_MI_CMD(MI_STORE_DATA_IMM) | (cmd_len - 2);
  54    /* must use GGTT on GEN6 as in PIPE_CONTROL */
  55    if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
  56       dw[0] |= GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT;
  57       reloc_flags |= INTEL_RELOC_GGTT;
  58    }
  59
  60    dw[1] = 0; /* MBZ */
  61
  62    if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
  63       dw[4] = (uint32_t) val;
  64       dw[5] = (uint32_t) (val >> 32);
  65
  66       ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, reloc_flags);
  67    } else {
  68       dw[3] = (uint32_t) val;
  69       dw[4] = (uint32_t) (val >> 32);
  70
  71       ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, reloc_flags);
  72    }
  73 }
  74
  75 static inline void
  76 gen6_MI_LOAD_REGISTER_IMM(struct ilo_builder *builder,
  77                           uint32_t reg, uint32_t val)
  78 {
  79    const uint8_t cmd_len = 3;
  80    uint32_t *dw;
  81
  82    ILO_DEV_ASSERT(builder->dev, 6, 8);
  83
  84    assert(reg % 4 == 0);
  85
  86    ilo_builder_batch_pointer(builder, cmd_len, &dw);
  87
  88    dw[0] = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM) | (cmd_len - 2);
  89    dw[1] = reg;
  90    dw[2] = val;
  91 }
  92
  93 static inline void
  94 gen6_MI_STORE_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg,
  95                            struct intel_bo *bo, uint32_t bo_offset)
  96 {
  97    const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 3;
  98    uint32_t reloc_flags = INTEL_RELOC_WRITE;
  99    uint32_t *dw;
 100    unsigned pos;
 101
 102    ILO_DEV_ASSERT(builder->dev, 6, 8);
 103
 104    assert(reg % 4 == 0 && bo_offset % 4 == 0);
 105
 106    pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
 107
 108    dw[0] = GEN6_MI_CMD(MI_STORE_REGISTER_MEM) | (cmd_len - 2);
 109    dw[1] = reg;
 110
 111    if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
 112       ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, reloc_flags);
 113    } else {
 114       /* must use GGTT on Gen6 as in PIPE_CONTROL */
 115       if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
 116          dw[0] |= GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT;
 117          reloc_flags |= INTEL_RELOC_GGTT;
 118       }
 119
 120       ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, reloc_flags);
 121    }
 122 }
 123
 124 static inline void
 125 gen6_MI_FLUSH_DW(struct ilo_builder *builder)
 126 {
 127    const uint8_t cmd_len = 4;
 128    uint32_t *dw;
 129
 130    ILO_DEV_ASSERT(builder->dev, 6, 8);
 131
 132    ilo_builder_batch_pointer(builder, cmd_len, &dw);
 133
 134    dw[0] = GEN6_MI_CMD(MI_FLUSH_DW) | (cmd_len - 2);
 135    dw[1] = 0;
 136    dw[2] = 0;
 137    dw[3] = 0;
 138 }
 139
 140 static inline void
 141 gen6_MI_REPORT_PERF_COUNT(struct ilo_builder *builder,
 142                           struct intel_bo *bo, uint32_t bo_offset,
 143                           uint32_t report_id)
 144 {
 145    const uint8_t cmd_len = 3;
 146    uint32_t reloc_flags = INTEL_RELOC_WRITE;
 147    uint32_t *dw;
 148    unsigned pos;
 149
 150    ILO_DEV_ASSERT(builder->dev, 6, 7.5);
 151
 152    assert(bo_offset % 64 == 0);
 153
 154    /* must use GGTT on GEN6 as in PIPE_CONTROL */
 155    if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
 156       bo_offset |= GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT;
 157       reloc_flags |= INTEL_RELOC_GGTT;
 158    }
 159
 160    pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
 161
 162    dw[0] = GEN6_MI_CMD(MI_REPORT_PERF_COUNT) | (cmd_len - 2);
 163    dw[2] = report_id;
 164
 165    ilo_builder_batch_reloc(builder, pos + 1, bo, bo_offset, reloc_flags);
 166 }
 167
 168 static inline void
 169 gen7_MI_LOAD_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg,
 170                           struct intel_bo *bo, uint32_t bo_offset)
 171 {
 172    const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 3;
 173    uint32_t *dw;
 174    unsigned pos;
 175
 176    ILO_DEV_ASSERT(builder->dev, 7, 8);
 177
 178    assert(reg % 4 == 0 && bo_offset % 4 == 0);
 179
 180    pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
 181
 182    dw[0] = GEN7_MI_CMD(MI_LOAD_REGISTER_MEM) | (cmd_len - 2);
 183    dw[1] = reg;
 184
 185    if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
 186       ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, 0);
 187    else
 188       ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, 0);
 189 }
 190
 191 /**
 192  * Add a MI_BATCH_BUFFER_END to the batch buffer.  Pad with MI_NOOP if
 193  * necessary.
 194  */
 195 static inline void
 196 gen6_mi_batch_buffer_end(struct ilo_builder *builder)
 197 {
 198    /*
 199     * From the Sandy Bridge PRM, volume 1 part 1, page 107:
 200     *
 201     *     "The batch buffer must be QWord aligned and a multiple of QWords in
 202     *      length."
 203     */
 204    const bool pad = !(builder->writers[ILO_BUILDER_WRITER_BATCH].used & 0x7);
 205    uint32_t *dw;
 206
 207    ILO_DEV_ASSERT(builder->dev, 6, 8);
 208
 209    if (pad) {
 210       ilo_builder_batch_pointer(builder, 2, &dw);
 211       dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
 212       dw[1] = GEN6_MI_CMD(MI_NOOP);
 213    } else {
 214       ilo_builder_batch_pointer(builder, 1, &dw);
 215       dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
 216    }
 217 }
 218
 219 #endif /* ILO_BUILDER_MI_H */