2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_resource.h"
31 #include "ilo_format.h"
32 #include "ilo_resource.h"
33 #include "ilo_shader.h"
34 #include "ilo_gpe_gen7.h"
37 ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info
*dev
,
38 const struct ilo_shader_state
*gs
,
39 struct ilo_shader_cso
*cso
)
41 int start_grf
, vue_read_len
, max_threads
;
42 uint32_t dw2
, dw4
, dw5
;
44 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
46 start_grf
= ilo_shader_get_kernel_param(gs
, ILO_KERNEL_URB_DATA_START_REG
);
47 vue_read_len
= ilo_shader_get_kernel_param(gs
, ILO_KERNEL_INPUT_COUNT
);
50 vue_read_len
= (vue_read_len
+ 1) / 2;
54 max_threads
= (dev
->gt
>= 2) ? 256 : 70;
57 max_threads
= (dev
->gt
== 2) ? 128 : 36;
64 dw2
= (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT
;
66 dw4
= vue_read_len
<< GEN6_GS_DW4_URB_READ_LEN__SHIFT
|
67 GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES
|
68 0 << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT
|
69 start_grf
<< GEN6_GS_DW4_URB_GRF_START__SHIFT
;
71 dw5
= (max_threads
- 1) << GEN6_GS_DW5_MAX_THREADS__SHIFT
|
72 GEN6_GS_DW5_STATISTICS
|
73 GEN6_GS_DW6_GS_ENABLE
;
75 STATIC_ASSERT(Elements(cso
->payload
) >= 3);
76 cso
->payload
[0] = dw2
;
77 cso
->payload
[1] = dw4
;
78 cso
->payload
[2] = dw5
;
82 ilo_gpe_init_rasterizer_wm_gen7(const struct ilo_dev_info
*dev
,
83 const struct pipe_rasterizer_state
*state
,
84 struct ilo_rasterizer_wm
*wm
)
88 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
90 dw1
= GEN7_WM_DW1_ZW_INTERP_PIXEL
|
91 GEN7_WM_DW1_AA_LINE_WIDTH_2_0
|
92 GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL
;
94 /* same value as in 3DSTATE_SF */
95 if (state
->line_smooth
)
96 dw1
|= GEN7_WM_DW1_AA_LINE_CAP_1_0
;
98 if (state
->poly_stipple_enable
)
99 dw1
|= GEN7_WM_DW1_POLY_STIPPLE_ENABLE
;
100 if (state
->line_stipple_enable
)
101 dw1
|= GEN7_WM_DW1_LINE_STIPPLE_ENABLE
;
103 if (state
->bottom_edge_rule
)
104 dw1
|= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT
;
106 dw2
= GEN7_WM_DW2_MSDISPMODE_PERSAMPLE
;
109 * assertion that makes sure
111 * dw1 |= wm->dw_msaa_rast;
112 * dw2 |= wm->dw_msaa_disp;
116 STATIC_ASSERT(GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL
== 0 &&
117 GEN7_WM_DW2_MSDISPMODE_PERSAMPLE
== 0);
120 (state
->multisample
) ? GEN7_WM_DW1_MSRASTMODE_ON_PATTERN
: 0;
121 wm
->dw_msaa_disp
= GEN7_WM_DW2_MSDISPMODE_PERPIXEL
;
123 STATIC_ASSERT(Elements(wm
->payload
) >= 2);
124 wm
->payload
[0] = dw1
;
125 wm
->payload
[1] = dw2
;
129 ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info
*dev
,
130 const struct ilo_shader_state
*fs
,
131 struct ilo_shader_cso
*cso
)
133 int start_grf
, max_threads
;
134 uint32_t dw2
, dw4
, dw5
;
135 uint32_t wm_interps
, wm_dw1
;
137 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
139 start_grf
= ilo_shader_get_kernel_param(fs
, ILO_KERNEL_URB_DATA_START_REG
);
141 dw2
= (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT
;
143 dw4
= GEN7_PS_DW4_POSOFFSET_NONE
;
145 /* see brwCreateContext() */
148 max_threads
= (dev
->gt
== 3) ? 408 : (dev
->gt
== 2) ? 204 : 102;
149 dw4
|= (max_threads
- 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT
;
150 dw4
|= 1 << GEN75_PS_DW4_SAMPLE_MASK__SHIFT
;
154 max_threads
= (dev
->gt
== 2) ? 172 : 48;
155 dw4
|= (max_threads
- 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT
;
159 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_PCB_CBUF0_SIZE
))
160 dw4
|= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE
;
162 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_INPUT_COUNT
))
163 dw4
|= GEN7_PS_DW4_ATTR_ENABLE
;
165 assert(!ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_DISPATCH_16_OFFSET
));
166 dw4
|= GEN7_PS_DW4_8_PIXEL_DISPATCH
;
168 dw5
= start_grf
<< GEN7_PS_DW5_URB_GRF_START0__SHIFT
|
169 0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT
|
170 0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT
;
172 /* FS affects 3DSTATE_WM too */
176 * TODO set this bit only when
178 * a) fs writes colors and color is not masked, or
179 * b) fs writes depth, or
182 wm_dw1
|= GEN7_WM_DW1_PS_ENABLE
;
185 * From the Ivy Bridge PRM, volume 2 part 1, page 278:
187 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that
188 * the PS kernel or color calculator has the ability to kill
189 * (discard) pixels or samples, other than due to depth or stencil
190 * testing. This bit is required to be ENABLED in the following
193 * - The API pixel shader program contains "killpix" or "discard"
194 * instructions, or other code in the pixel shader kernel that
195 * can cause the final pixel mask to differ from the pixel mask
196 * received on dispatch.
198 * - A sampler with chroma key enabled with kill pixel mode is used
199 * by the pixel shader.
201 * - Any render target has Alpha Test Enable or AlphaToCoverage
204 * - The pixel shader kernel generates and outputs oMask.
206 * Note: As ClipDistance clipping is fully supported in hardware
207 * and therefore not via PS instructions, there should be no need
208 * to ENABLE this bit due to ClipDistance clipping."
210 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_USE_KILL
))
211 wm_dw1
|= GEN7_WM_DW1_PS_KILL
;
213 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_OUTPUT_Z
))
214 wm_dw1
|= GEN7_WM_DW1_PSCDEPTH_ON
;
216 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_INPUT_Z
))
217 wm_dw1
|= GEN7_WM_DW1_PS_USE_DEPTH
;
219 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_INPUT_W
))
220 wm_dw1
|= GEN7_WM_DW1_PS_USE_W
;
222 wm_interps
= ilo_shader_get_kernel_param(fs
,
223 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS
);
225 wm_dw1
|= wm_interps
<< GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT
;
227 STATIC_ASSERT(Elements(cso
->payload
) >= 4);
228 cso
->payload
[0] = dw2
;
229 cso
->payload
[1] = dw4
;
230 cso
->payload
[2] = dw5
;
231 cso
->payload
[3] = wm_dw1
;
235 ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info
*dev
,
236 unsigned width
, unsigned height
,
237 unsigned depth
, unsigned level
,
238 struct ilo_view_surface
*surf
)
242 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
245 * From the Ivy Bridge PRM, volume 4 part 1, page 62:
247 * "A null surface is used in instances where an actual surface is not
248 * bound. When a write message is generated to a null surface, no
249 * actual surface is written to. When a read message (including any
250 * sampling engine message) is generated to a null surface, the result
251 * is all zeros. Note that a null surface type is allowed to be used
252 * with all messages, even if it is not specificially indicated as
253 * supported. All of the remaining fields in surface state are ignored
254 * for null surfaces, with the following exceptions:
256 * * Width, Height, Depth, LOD, and Render Target View Extent fields
257 * must match the depth buffer's corresponding state for all render
258 * target surfaces, including null.
259 * * All sampling engine and data port messages support null surfaces
260 * with the above behavior, even if not mentioned as specifically
261 * supported, except for the following:
262 * * Data Port Media Block Read/Write messages.
263 * * The Surface Type of a surface used as a render target (accessed
264 * via the Data Port's Render Target Write message) must be the same
265 * as the Surface Type of all other render targets and of the depth
266 * buffer (defined in 3DSTATE_DEPTH_BUFFER), unless either the depth
267 * buffer or render targets are SURFTYPE_NULL."
269 * From the Ivy Bridge PRM, volume 4 part 1, page 65:
271 * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must be
275 STATIC_ASSERT(Elements(surf
->payload
) >= 8);
278 dw
[0] = GEN6_SURFTYPE_NULL
<< GEN6_SURFACE_DW0_TYPE__SHIFT
|
279 GEN6_FORMAT_B8G8R8A8_UNORM
<< GEN6_SURFACE_DW0_FORMAT__SHIFT
|
284 dw
[2] = SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
) |
285 SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
);
287 dw
[3] = SET_FIELD(depth
- 1, BRW_SURFACE_DEPTH
);
299 ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info
*dev
,
300 const struct ilo_buffer
*buf
,
301 unsigned offset
, unsigned size
,
302 unsigned struct_size
,
303 enum pipe_format elem_format
,
304 bool is_rt
, bool render_cache_rw
,
305 struct ilo_view_surface
*surf
)
307 const bool typed
= (elem_format
!= PIPE_FORMAT_NONE
);
308 const bool structured
= (!typed
&& struct_size
> 1);
309 const int elem_size
= (typed
) ?
310 util_format_get_blocksize(elem_format
) : 1;
311 int width
, height
, depth
, pitch
;
312 int surface_type
, surface_format
, num_entries
;
315 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
317 surface_type
= (structured
) ? 5 : GEN6_SURFTYPE_BUFFER
;
319 surface_format
= (typed
) ?
320 ilo_translate_color_format(elem_format
) : GEN6_FORMAT_RAW
;
322 num_entries
= size
/ struct_size
;
323 /* see if there is enough space to fit another element */
324 if (size
% struct_size
>= elem_size
&& !structured
)
328 * From the Ivy Bridge PRM, volume 4 part 1, page 67:
330 * "For SURFTYPE_BUFFER render targets, this field (Surface Base
331 * Address) specifies the base address of first element of the
332 * surface. The surface is interpreted as a simple array of that
333 * single element type. The address must be naturally-aligned to the
334 * element size (e.g., a buffer containing R32G32B32A32_FLOAT elements
335 * must be 16-byte aligned)
337 * For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
338 * the base address of the first element of the surface, computed in
339 * software by adding the surface base address to the byte offset of
340 * the element in the buffer."
343 assert(offset
% elem_size
== 0);
346 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
348 * "For typed buffer and structured buffer surfaces, the number of
349 * entries in the buffer ranges from 1 to 2^27. For raw buffer
350 * surfaces, the number of entries in the buffer is the number of
351 * bytes which can range from 1 to 2^30."
353 assert(num_entries
>= 1 &&
354 num_entries
<= 1 << ((typed
|| structured
) ? 27 : 30));
357 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
359 * "For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
360 * 11 if the Surface Format is RAW (the size of the buffer must be a
361 * multiple of 4 bytes)."
363 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
365 * "For surfaces of type SURFTYPE_BUFFER and SURFTYPE_STRBUF, this
366 * field (Surface Pitch) indicates the size of the structure."
368 * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the pitch
369 * must be a multiple of 4 bytes."
372 assert(struct_size
% 4 == 0);
374 assert(num_entries
% 4 == 0);
381 width
= (num_entries
& 0x0000007f);
383 height
= (num_entries
& 0x001fff80) >> 7;
385 depth
= (num_entries
& 0x7fe00000) >> 21;
386 /* limit to [26:21] */
387 if (typed
|| structured
)
390 STATIC_ASSERT(Elements(surf
->payload
) >= 8);
393 dw
[0] = surface_type
<< GEN6_SURFACE_DW0_TYPE__SHIFT
|
394 surface_format
<< GEN6_SURFACE_DW0_FORMAT__SHIFT
;
396 dw
[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW
;
400 dw
[2] = SET_FIELD(height
, GEN7_SURFACE_HEIGHT
) |
401 SET_FIELD(width
, GEN7_SURFACE_WIDTH
);
403 dw
[3] = SET_FIELD(depth
, BRW_SURFACE_DEPTH
) |
412 if (dev
->gen
>= ILO_GEN(7.5)) {
413 dw
[7] |= SET_FIELD(GEN75_SCS_RED
, GEN7_SURFACE_SCS_R
) |
414 SET_FIELD(GEN75_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
415 SET_FIELD(GEN75_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
416 SET_FIELD(GEN75_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
419 /* do not increment reference count */
424 ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info
*dev
,
425 const struct ilo_texture
*tex
,
426 enum pipe_format format
,
427 unsigned first_level
,
429 unsigned first_layer
,
431 bool is_rt
, bool offset_to_layer
,
432 struct ilo_view_surface
*surf
)
434 int surface_type
, surface_format
;
435 int width
, height
, depth
, pitch
, lod
;
436 unsigned layer_offset
, x_offset
, y_offset
;
439 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
441 surface_type
= ilo_gpe_gen6_translate_texture(tex
->base
.target
);
442 assert(surface_type
!= GEN6_SURFTYPE_BUFFER
);
444 if (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
&& tex
->separate_s8
)
445 format
= PIPE_FORMAT_Z32_FLOAT
;
448 surface_format
= ilo_translate_render_format(format
);
450 surface_format
= ilo_translate_texture_format(format
);
451 assert(surface_format
>= 0);
453 width
= tex
->base
.width0
;
454 height
= tex
->base
.height0
;
455 depth
= (tex
->base
.target
== PIPE_TEXTURE_3D
) ?
456 tex
->base
.depth0
: num_layers
;
457 pitch
= tex
->bo_stride
;
459 if (surface_type
== GEN6_SURFTYPE_CUBE
) {
461 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
463 * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of
464 * this field is [0,340], indicating the number of cube array
465 * elements (equal to the number of underlying 2D array elements
466 * divided by 6). For other surfaces, this field must be zero."
468 * When is_rt is true, we treat the texture as a 2D one to avoid the
472 surface_type
= GEN6_SURFTYPE_2D
;
475 assert(num_layers
% 6 == 0);
476 depth
= num_layers
/ 6;
480 /* sanity check the size */
481 assert(width
>= 1 && height
>= 1 && depth
>= 1 && pitch
>= 1);
482 assert(first_layer
< 2048 && num_layers
<= 2048);
483 switch (surface_type
) {
484 case GEN6_SURFTYPE_1D
:
485 assert(width
<= 16384 && height
== 1 && depth
<= 2048);
487 case GEN6_SURFTYPE_2D
:
488 assert(width
<= 16384 && height
<= 16384 && depth
<= 2048);
490 case GEN6_SURFTYPE_3D
:
491 assert(width
<= 2048 && height
<= 2048 && depth
<= 2048);
493 assert(first_layer
== 0);
495 case GEN6_SURFTYPE_CUBE
:
496 assert(width
<= 16384 && height
<= 16384 && depth
<= 86);
497 assert(width
== height
);
499 assert(first_layer
== 0);
502 assert(!"unexpected surface type");
507 assert(num_levels
== 1);
511 lod
= num_levels
- 1;
515 * Offset to the layer. When rendering, the hardware requires LOD and
516 * Depth to be the same for all render targets and the depth buffer. We
517 * need to offset to the layer manually and always set LOD and Depth to 0.
519 if (offset_to_layer
) {
520 /* we lose the capability for layered rendering */
521 assert(is_rt
&& num_layers
== 1);
523 layer_offset
= ilo_texture_get_slice_offset(tex
,
524 first_level
, first_layer
, &x_offset
, &y_offset
);
526 assert(x_offset
% 4 == 0);
527 assert(y_offset
% 2 == 0);
531 /* derive the size for the LOD */
532 width
= u_minify(width
, first_level
);
533 height
= u_minify(height
, first_level
);
548 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
550 * "The Base Address for linear render target surfaces and surfaces
551 * accessed with the typed surface read/write data port messages must
552 * be element-size aligned, for non-YUV surface formats, or a multiple
553 * of 2 element-sizes for YUV surface formats. Other linear surfaces
554 * have no alignment requirements (byte alignment is sufficient)."
556 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
558 * "For linear render target surfaces and surfaces accessed with the
559 * typed data port messages, the pitch must be a multiple of the
560 * element size for non-YUV surface formats. Pitch must be a multiple
561 * of 2 * element size for YUV surface formats. For linear surfaces
562 * with Surface Type of SURFTYPE_STRBUF, the pitch must be a multiple
563 * of 4 bytes.For other linear surfaces, the pitch can be any multiple
566 * From the Ivy Bridge PRM, volume 4 part 1, page 74:
568 * "For linear surfaces, this field (X Offset) must be zero."
570 if (tex
->tiling
== INTEL_TILING_NONE
) {
572 const int elem_size
= util_format_get_blocksize(format
);
573 assert(layer_offset
% elem_size
== 0);
574 assert(pitch
% elem_size
== 0);
580 STATIC_ASSERT(Elements(surf
->payload
) >= 8);
583 dw
[0] = surface_type
<< GEN6_SURFACE_DW0_TYPE__SHIFT
|
584 surface_format
<< GEN6_SURFACE_DW0_FORMAT__SHIFT
|
585 ilo_gpe_gen6_translate_winsys_tiling(tex
->tiling
) << 13;
588 * From the Ivy Bridge PRM, volume 4 part 1, page 63:
590 * "If this field (Surface Array) is enabled, the Surface Type must be
591 * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
592 * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
593 * SURFTYPE_CUBE, the Depth field must be set to zero."
595 * For non-3D sampler surfaces, resinfo (the sampler message) always
596 * returns zero for the number of layers when this field is not set.
598 if (surface_type
!= GEN6_SURFTYPE_3D
) {
599 if (util_resource_is_array_texture(&tex
->base
))
600 dw
[0] |= GEN7_SURFACE_DW0_IS_ARRAY
;
606 dw
[0] |= GEN7_SURFACE_DW0_VALIGN_4
;
609 dw
[0] |= GEN7_SURFACE_DW0_HALIGN_8
;
611 if (tex
->array_spacing_full
)
612 dw
[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL
;
614 dw
[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0
;
617 dw
[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW
;
619 if (surface_type
== GEN6_SURFTYPE_CUBE
&& !is_rt
)
620 dw
[0] |= GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK
;
622 dw
[1] = layer_offset
;
624 dw
[2] = SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
) |
625 SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
);
627 dw
[3] = SET_FIELD(depth
- 1, BRW_SURFACE_DEPTH
) |
630 dw
[4] = first_layer
<< 18 |
631 (num_layers
- 1) << 7;
634 * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
635 * means the samples are interleaved. The layouts are the same when the
636 * number of samples is 1.
638 if (tex
->interleaved
&& tex
->base
.nr_samples
> 1) {
640 dw
[4] |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL
;
643 dw
[4] |= GEN7_SURFACE_DW4_MSFMT_MSS
;
646 if (tex
->base
.nr_samples
> 4)
647 dw
[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8
;
648 else if (tex
->base
.nr_samples
> 2)
649 dw
[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4
;
651 dw
[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1
;
653 dw
[5] = x_offset
<< GEN6_SURFACE_DW5_X_OFFSET__SHIFT
|
654 y_offset
<< GEN6_SURFACE_DW5_Y_OFFSET__SHIFT
|
655 SET_FIELD(first_level
, GEN7_SURFACE_MIN_LOD
) |
661 if (dev
->gen
>= ILO_GEN(7.5)) {
662 dw
[7] |= SET_FIELD(GEN75_SCS_RED
, GEN7_SURFACE_SCS_R
) |
663 SET_FIELD(GEN75_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
664 SET_FIELD(GEN75_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
665 SET_FIELD(GEN75_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
668 /* do not increment reference count */
673 ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info
*dev
,
674 enum ilo_gpe_gen7_command cmd
,
677 static const struct {
680 } gen7_command_size_table
[ILO_GPE_GEN7_COMMAND_COUNT
] = {
681 [ILO_GPE_GEN7_MI_STORE_DATA_IMM
] = { 0, 5 },
682 [ILO_GPE_GEN7_MI_LOAD_REGISTER_IMM
] = { 0, 3 },
683 [ILO_GPE_GEN7_MI_STORE_REGISTER_MEM
] = { 0, 3 },
684 [ILO_GPE_GEN7_MI_REPORT_PERF_COUNT
] = { 0, 3 },
685 [ILO_GPE_GEN7_STATE_BASE_ADDRESS
] = { 0, 10 },
686 [ILO_GPE_GEN7_STATE_SIP
] = { 0, 2 },
687 [ILO_GPE_GEN7_3DSTATE_VF_STATISTICS
] = { 0, 1 },
688 [ILO_GPE_GEN7_PIPELINE_SELECT
] = { 0, 1 },
689 [ILO_GPE_GEN7_MEDIA_VFE_STATE
] = { 0, 8 },
690 [ILO_GPE_GEN7_MEDIA_CURBE_LOAD
] = { 0, 4 },
691 [ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD
] = { 0, 4 },
692 [ILO_GPE_GEN7_MEDIA_STATE_FLUSH
] = { 0, 2 },
693 [ILO_GPE_GEN7_GPGPU_WALKER
] = { 0, 11 },
694 [ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS
] = { 0, 3 },
695 [ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER
] = { 0, 7 },
696 [ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER
] = { 0, 3 },
697 [ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER
] = { 0, 3 },
698 [ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS
] = { 1, 4 },
699 [ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS
] = { 1, 2 },
700 [ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER
] = { 0, 3 },
701 [ILO_GPE_GEN7_3DSTATE_VF
] = { 0, 2 },
702 [ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS
] = { 0, 2 },
703 [ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS
] = { 0, 2 },
704 [ILO_GPE_GEN7_3DSTATE_VS
] = { 0, 6 },
705 [ILO_GPE_GEN7_3DSTATE_GS
] = { 0, 7 },
706 [ILO_GPE_GEN7_3DSTATE_CLIP
] = { 0, 4 },
707 [ILO_GPE_GEN7_3DSTATE_SF
] = { 0, 7 },
708 [ILO_GPE_GEN7_3DSTATE_WM
] = { 0, 3 },
709 [ILO_GPE_GEN7_3DSTATE_CONSTANT_VS
] = { 0, 7 },
710 [ILO_GPE_GEN7_3DSTATE_CONSTANT_GS
] = { 0, 7 },
711 [ILO_GPE_GEN7_3DSTATE_CONSTANT_PS
] = { 0, 7 },
712 [ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK
] = { 0, 2 },
713 [ILO_GPE_GEN7_3DSTATE_CONSTANT_HS
] = { 0, 7 },
714 [ILO_GPE_GEN7_3DSTATE_CONSTANT_DS
] = { 0, 7 },
715 [ILO_GPE_GEN7_3DSTATE_HS
] = { 0, 7 },
716 [ILO_GPE_GEN7_3DSTATE_TE
] = { 0, 4 },
717 [ILO_GPE_GEN7_3DSTATE_DS
] = { 0, 6 },
718 [ILO_GPE_GEN7_3DSTATE_STREAMOUT
] = { 0, 3 },
719 [ILO_GPE_GEN7_3DSTATE_SBE
] = { 0, 14 },
720 [ILO_GPE_GEN7_3DSTATE_PS
] = { 0, 8 },
721 [ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
] = { 0, 2 },
722 [ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC
] = { 0, 2 },
723 [ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS
] = { 0, 2 },
724 [ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
] = { 0, 2 },
725 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS
] = { 0, 2 },
726 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS
] = { 0, 2 },
727 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS
] = { 0, 2 },
728 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS
] = { 0, 2 },
729 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS
] = { 0, 2 },
730 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS
] = { 0, 2 },
731 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS
] = { 0, 2 },
732 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS
] = { 0, 2 },
733 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS
] = { 0, 2 },
734 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS
] = { 0, 2 },
735 [ILO_GPE_GEN7_3DSTATE_URB_VS
] = { 0, 2 },
736 [ILO_GPE_GEN7_3DSTATE_URB_HS
] = { 0, 2 },
737 [ILO_GPE_GEN7_3DSTATE_URB_DS
] = { 0, 2 },
738 [ILO_GPE_GEN7_3DSTATE_URB_GS
] = { 0, 2 },
739 [ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE
] = { 0, 4 },
740 [ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET
] = { 0, 2 },
741 [ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN
] = { 0, 33, },
742 [ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE
] = { 0, 3 },
743 [ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS
] = { 0, 3 },
744 [ILO_GPE_GEN7_3DSTATE_MULTISAMPLE
] = { 0, 4 },
745 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS
] = { 0, 2 },
746 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS
] = { 0, 2 },
747 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS
] = { 0, 2 },
748 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS
] = { 0, 2 },
749 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS
] = { 0, 2 },
750 [ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST
] = { 3, 2 },
751 [ILO_GPE_GEN7_3DSTATE_SO_BUFFER
] = { 0, 4 },
752 [ILO_GPE_GEN7_PIPE_CONTROL
] = { 0, 5 },
753 [ILO_GPE_GEN7_3DPRIMITIVE
] = { 0, 7 },
755 const int header
= gen7_command_size_table
[cmd
].header
;
756 const int body
= gen7_command_size_table
[cmd
].body
;
757 const int count
= arg
;
759 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
760 assert(cmd
< ILO_GPE_GEN7_COMMAND_COUNT
);
762 return (likely(count
)) ? header
+ body
* count
: 0;
766 ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info
*dev
,
767 enum ilo_gpe_gen7_state state
,
770 static const struct {
774 } gen7_state_size_table
[ILO_GPE_GEN7_STATE_COUNT
] = {
775 [ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA
] = { 8, 8, true },
776 [ILO_GPE_GEN7_SF_CLIP_VIEWPORT
] = { 16, 16, true },
777 [ILO_GPE_GEN7_CC_VIEWPORT
] = { 8, 2, true },
778 [ILO_GPE_GEN7_COLOR_CALC_STATE
] = { 16, 6, false },
779 [ILO_GPE_GEN7_BLEND_STATE
] = { 16, 2, true },
780 [ILO_GPE_GEN7_DEPTH_STENCIL_STATE
] = { 16, 3, false },
781 [ILO_GPE_GEN7_SCISSOR_RECT
] = { 8, 2, true },
782 [ILO_GPE_GEN7_BINDING_TABLE_STATE
] = { 8, 1, true },
783 [ILO_GPE_GEN7_SURFACE_STATE
] = { 8, 8, false },
784 [ILO_GPE_GEN7_SAMPLER_STATE
] = { 8, 4, true },
785 [ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE
] = { 8, 4, false },
786 [ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER
] = { 8, 1, true },
788 const int alignment
= gen7_state_size_table
[state
].alignment
;
789 const int body
= gen7_state_size_table
[state
].body
;
790 const bool is_array
= gen7_state_size_table
[state
].is_array
;
791 const int count
= arg
;
794 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
795 assert(state
< ILO_GPE_GEN7_STATE_COUNT
);
799 estimate
= (alignment
- 1) + body
* count
;
802 estimate
= (alignment
- 1) + body
;
803 /* all states are aligned */
805 estimate
+= util_align_npot(body
, alignment
) * (count
- 1);