src/gallium/drivers/ilo/ilo_gpe_gen7.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "genhw/genhw.h"
  29 #include "util/u_resource.h"
  30
  31 #include "ilo_format.h"
  32 #include "ilo_resource.h"
  33 #include "ilo_shader.h"
  34 #include "ilo_gpe_gen7.h"
  35
  36 #define SET_FIELD(value, field) (((value) << field ## __SHIFT) & field ## __MASK)
  37
  38 void
  39 ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev,
  40                          const struct ilo_shader_state *gs,
  41                          struct ilo_shader_cso *cso)
  42 {
  43    int start_grf, vue_read_len, max_threads;
  44    uint32_t dw2, dw4, dw5;
  45
  46    ILO_GPE_VALID_GEN(dev, 7, 7.5);
  47
  48    start_grf = ilo_shader_get_kernel_param(gs, ILO_KERNEL_URB_DATA_START_REG);
  49    vue_read_len = ilo_shader_get_kernel_param(gs, ILO_KERNEL_INPUT_COUNT);
  50
  51    /* in pairs */
  52    vue_read_len = (vue_read_len + 1) / 2;
  53
  54    switch (dev->gen) {
  55    case ILO_GEN(7.5):
  56       max_threads = (dev->gt >= 2) ? 256 : 70;
  57       break;
  58    case ILO_GEN(7):
  59       max_threads = (dev->gt == 2) ? 128 : 36;
  60       break;
  61    default:
  62       max_threads = 1;
  63       break;
  64    }
  65
  66    dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
  67
  68    dw4 = vue_read_len << GEN7_GS_DW4_URB_READ_LEN__SHIFT |
  69          GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES |
  70          0 << GEN7_GS_DW4_URB_READ_OFFSET__SHIFT |
  71          start_grf << GEN7_GS_DW4_URB_GRF_START__SHIFT;
  72
  73    dw5 = (max_threads - 1) << GEN7_GS_DW5_MAX_THREADS__SHIFT |
  74          GEN7_GS_DW5_STATISTICS |
  75          GEN7_GS_DW5_GS_ENABLE;
  76
  77    STATIC_ASSERT(Elements(cso->payload) >= 3);
  78    cso->payload[0] = dw2;
  79    cso->payload[1] = dw4;
  80    cso->payload[2] = dw5;
  81 }
  82
  83 void
  84 ilo_gpe_init_rasterizer_wm_gen7(const struct ilo_dev_info *dev,
  85                                 const struct pipe_rasterizer_state *state,
  86                                 struct ilo_rasterizer_wm *wm)
  87 {
  88    uint32_t dw1, dw2;
  89
  90    ILO_GPE_VALID_GEN(dev, 7, 7.5);
  91
  92    dw1 = GEN7_WM_DW1_ZW_INTERP_PIXEL |
  93          GEN7_WM_DW1_AA_LINE_WIDTH_2_0 |
  94          GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL;
  95
  96    /* same value as in 3DSTATE_SF */
  97    if (state->line_smooth)
  98       dw1 |= GEN7_WM_DW1_AA_LINE_CAP_1_0;
  99
 100    if (state->poly_stipple_enable)
 101       dw1 |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
 102    if (state->line_stipple_enable)
 103       dw1 |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
 104
 105    if (state->bottom_edge_rule)
 106       dw1 |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
 107
 108    dw2 = GEN7_WM_DW2_MSDISPMODE_PERSAMPLE;
 109
 110    /*
 111     * assertion that makes sure
 112     *
 113     *   dw1 |= wm->dw_msaa_rast;
 114     *   dw2 |= wm->dw_msaa_disp;
 115     *
 116     * is valid
 117     */
 118    STATIC_ASSERT(GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL == 0 &&
 119                  GEN7_WM_DW2_MSDISPMODE_PERSAMPLE == 0);
 120
 121    wm->dw_msaa_rast =
 122       (state->multisample) ? GEN7_WM_DW1_MSRASTMODE_ON_PATTERN : 0;
 123    wm->dw_msaa_disp = GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
 124
 125    STATIC_ASSERT(Elements(wm->payload) >= 2);
 126    wm->payload[0] = dw1;
 127    wm->payload[1] = dw2;
 128 }
 129
 130 void
 131 ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info *dev,
 132                          const struct ilo_shader_state *fs,
 133                          struct ilo_shader_cso *cso)
 134 {
 135    int start_grf, max_threads;
 136    uint32_t dw2, dw4, dw5;
 137    uint32_t wm_interps, wm_dw1;
 138
 139    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 140
 141    start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
 142
 143    dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
 144
 145    dw4 = GEN7_PS_DW4_POSOFFSET_NONE;
 146
 147    /* see brwCreateContext() */
 148    switch (dev->gen) {
 149    case ILO_GEN(7.5):
 150       max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
 151       dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
 152       dw4 |= 1 << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
 153       break;
 154    case ILO_GEN(7):
 155    default:
 156       max_threads = (dev->gt == 2) ? 172 : 48;
 157       dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
 158       break;
 159    }
 160
 161    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE))
 162       dw4 |= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE;
 163
 164    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT))
 165       dw4 |= GEN7_PS_DW4_ATTR_ENABLE;
 166
 167    assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
 168    dw4 |= GEN7_PS_DW4_8_PIXEL_DISPATCH;
 169
 170    dw5 = start_grf << GEN7_PS_DW5_URB_GRF_START0__SHIFT |
 171          0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT |
 172          0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT;
 173
 174    /* FS affects 3DSTATE_WM too */
 175    wm_dw1 = 0;
 176
 177    /*
 178     * TODO set this bit only when
 179     *
 180     *  a) fs writes colors and color is not masked, or
 181     *  b) fs writes depth, or
 182     *  c) fs or cc kills
 183     */
 184    wm_dw1 |= GEN7_WM_DW1_PS_ENABLE;
 185
 186    /*
 187     * From the Ivy Bridge PRM, volume 2 part 1, page 278:
 188     *
 189     *     "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that
 190     *      the PS kernel or color calculator has the ability to kill
 191     *      (discard) pixels or samples, other than due to depth or stencil
 192     *      testing. This bit is required to be ENABLED in the following
 193     *      situations:
 194     *
 195     *      - The API pixel shader program contains "killpix" or "discard"
 196     *        instructions, or other code in the pixel shader kernel that
 197     *        can cause the final pixel mask to differ from the pixel mask
 198     *        received on dispatch.
 199     *
 200     *      - A sampler with chroma key enabled with kill pixel mode is used
 201     *        by the pixel shader.
 202     *
 203     *      - Any render target has Alpha Test Enable or AlphaToCoverage
 204     *        Enable enabled.
 205     *
 206     *      - The pixel shader kernel generates and outputs oMask.
 207     *
 208     *      Note: As ClipDistance clipping is fully supported in hardware
 209     *      and therefore not via PS instructions, there should be no need
 210     *      to ENABLE this bit due to ClipDistance clipping."
 211     */
 212    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
 213       wm_dw1 |= GEN7_WM_DW1_PS_KILL;
 214
 215    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
 216       wm_dw1 |= GEN7_WM_DW1_PSCDEPTH_ON;
 217
 218    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
 219       wm_dw1 |= GEN7_WM_DW1_PS_USE_DEPTH;
 220
 221    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
 222       wm_dw1 |= GEN7_WM_DW1_PS_USE_W;
 223
 224    wm_interps = ilo_shader_get_kernel_param(fs,
 225          ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS);
 226
 227    wm_dw1 |= wm_interps << GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT;
 228
 229    STATIC_ASSERT(Elements(cso->payload) >= 4);
 230    cso->payload[0] = dw2;
 231    cso->payload[1] = dw4;
 232    cso->payload[2] = dw5;
 233    cso->payload[3] = wm_dw1;
 234 }
 235
 236 void
 237 ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info *dev,
 238                                     unsigned width, unsigned height,
 239                                     unsigned depth, unsigned level,
 240                                     struct ilo_view_surface *surf)
 241 {
 242    uint32_t *dw;
 243
 244    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 245
 246    /*
 247     * From the Ivy Bridge PRM, volume 4 part 1, page 62:
 248     *
 249     *     "A null surface is used in instances where an actual surface is not
 250     *      bound. When a write message is generated to a null surface, no
 251     *      actual surface is written to. When a read message (including any
 252     *      sampling engine message) is generated to a null surface, the result
 253     *      is all zeros.  Note that a null surface type is allowed to be used
 254     *      with all messages, even if it is not specificially indicated as
 255     *      supported. All of the remaining fields in surface state are ignored
 256     *      for null surfaces, with the following exceptions:
 257     *
 258     *      * Width, Height, Depth, LOD, and Render Target View Extent fields
 259     *        must match the depth buffer's corresponding state for all render
 260     *        target surfaces, including null.
 261     *      * All sampling engine and data port messages support null surfaces
 262     *        with the above behavior, even if not mentioned as specifically
 263     *        supported, except for the following:
 264     *        * Data Port Media Block Read/Write messages.
 265     *      * The Surface Type of a surface used as a render target (accessed
 266     *        via the Data Port's Render Target Write message) must be the same
 267     *        as the Surface Type of all other render targets and of the depth
 268     *        buffer (defined in 3DSTATE_DEPTH_BUFFER), unless either the depth
 269     *        buffer or render targets are SURFTYPE_NULL."
 270     *
 271     * From the Ivy Bridge PRM, volume 4 part 1, page 65:
 272     *
 273     *     "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must be
 274     *      true"
 275     */
 276
 277    STATIC_ASSERT(Elements(surf->payload) >= 8);
 278    dw = surf->payload;
 279
 280    dw[0] = GEN6_SURFTYPE_NULL << GEN7_SURFACE_DW0_TYPE__SHIFT |
 281            GEN6_FORMAT_B8G8R8A8_UNORM << GEN7_SURFACE_DW0_FORMAT__SHIFT |
 282            GEN6_TILING_X << 13;
 283
 284    dw[1] = 0;
 285
 286    dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_DW2_HEIGHT) |
 287            SET_FIELD(width  - 1, GEN7_SURFACE_DW2_WIDTH);
 288
 289    dw[3] = SET_FIELD(depth - 1, GEN7_SURFACE_DW3_DEPTH);
 290
 291    dw[4] = 0;
 292    dw[5] = level;
 293
 294    dw[6] = 0;
 295    dw[7] = 0;
 296
 297    surf->bo = NULL;
 298 }
 299
 300 void
 301 ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
 302                                           const struct ilo_buffer *buf,
 303                                           unsigned offset, unsigned size,
 304                                           unsigned struct_size,
 305                                           enum pipe_format elem_format,
 306                                           bool is_rt, bool render_cache_rw,
 307                                           struct ilo_view_surface *surf)
 308 {
 309    const bool typed = (elem_format != PIPE_FORMAT_NONE);
 310    const bool structured = (!typed && struct_size > 1);
 311    const int elem_size = (typed) ?
 312       util_format_get_blocksize(elem_format) : 1;
 313    int width, height, depth, pitch;
 314    int surface_type, surface_format, num_entries;
 315    uint32_t *dw;
 316
 317    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 318
 319    surface_type = (structured) ? GEN7_SURFTYPE_STRBUF : GEN6_SURFTYPE_BUFFER;
 320
 321    surface_format = (typed) ?
 322       ilo_translate_color_format(elem_format) : GEN6_FORMAT_RAW;
 323
 324    num_entries = size / struct_size;
 325    /* see if there is enough space to fit another element */
 326    if (size % struct_size >= elem_size && !structured)
 327       num_entries++;
 328
 329    /*
 330     * From the Ivy Bridge PRM, volume 4 part 1, page 67:
 331     *
 332     *     "For SURFTYPE_BUFFER render targets, this field (Surface Base
 333     *      Address) specifies the base address of first element of the
 334     *      surface. The surface is interpreted as a simple array of that
 335     *      single element type. The address must be naturally-aligned to the
 336     *      element size (e.g., a buffer containing R32G32B32A32_FLOAT elements
 337     *      must be 16-byte aligned)
 338     *
 339     *      For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
 340     *      the base address of the first element of the surface, computed in
 341     *      software by adding the surface base address to the byte offset of
 342     *      the element in the buffer."
 343     */
 344    if (is_rt)
 345       assert(offset % elem_size == 0);
 346
 347    /*
 348     * From the Ivy Bridge PRM, volume 4 part 1, page 68:
 349     *
 350     *     "For typed buffer and structured buffer surfaces, the number of
 351     *      entries in the buffer ranges from 1 to 2^27.  For raw buffer
 352     *      surfaces, the number of entries in the buffer is the number of
 353     *      bytes which can range from 1 to 2^30."
 354     */
 355    assert(num_entries >= 1 &&
 356           num_entries <= 1 << ((typed || structured) ? 27 : 30));
 357
 358    /*
 359     * From the Ivy Bridge PRM, volume 4 part 1, page 69:
 360     *
 361     *     "For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
 362     *      11 if the Surface Format is RAW (the size of the buffer must be a
 363     *      multiple of 4 bytes)."
 364     *
 365     * From the Ivy Bridge PRM, volume 4 part 1, page 70:
 366     *
 367     *     "For surfaces of type SURFTYPE_BUFFER and SURFTYPE_STRBUF, this
 368     *      field (Surface Pitch) indicates the size of the structure."
 369     *
 370     *     "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the pitch
 371     *      must be a multiple of 4 bytes."
 372     */
 373    if (structured)
 374       assert(struct_size % 4 == 0);
 375    else if (!typed)
 376       assert(num_entries % 4 == 0);
 377
 378    pitch = struct_size;
 379
 380    pitch--;
 381    num_entries--;
 382    /* bits [6:0] */
 383    width  = (num_entries & 0x0000007f);
 384    /* bits [20:7] */
 385    height = (num_entries & 0x001fff80) >> 7;
 386    /* bits [30:21] */
 387    depth  = (num_entries & 0x7fe00000) >> 21;
 388    /* limit to [26:21] */
 389    if (typed || structured)
 390       depth &= 0x3f;
 391
 392    STATIC_ASSERT(Elements(surf->payload) >= 8);
 393    dw = surf->payload;
 394
 395    dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
 396            surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
 397    if (render_cache_rw)
 398       dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
 399
 400    dw[1] = offset;
 401
 402    dw[2] = SET_FIELD(height, GEN7_SURFACE_DW2_HEIGHT) |
 403            SET_FIELD(width, GEN7_SURFACE_DW2_WIDTH);
 404
 405    dw[3] = SET_FIELD(depth, GEN7_SURFACE_DW3_DEPTH) |
 406            pitch;
 407
 408    dw[4] = 0;
 409    dw[5] = 0;
 410
 411    dw[6] = 0;
 412    dw[7] = 0;
 413
 414    if (dev->gen >= ILO_GEN(7.5)) {
 415       dw[7] |= SET_FIELD(GEN75_SCS_RED,   GEN75_SURFACE_DW7_SCS_R) |
 416                SET_FIELD(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
 417                SET_FIELD(GEN75_SCS_BLUE,  GEN75_SURFACE_DW7_SCS_B) |
 418                SET_FIELD(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
 419    }
 420
 421    /* do not increment reference count */
 422    surf->bo = buf->bo;
 423 }
 424
 425 void
 426 ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
 427                                            const struct ilo_texture *tex,
 428                                            enum pipe_format format,
 429                                            unsigned first_level,
 430                                            unsigned num_levels,
 431                                            unsigned first_layer,
 432                                            unsigned num_layers,
 433                                            bool is_rt, bool offset_to_layer,
 434                                            struct ilo_view_surface *surf)
 435 {
 436    int surface_type, surface_format;
 437    int width, height, depth, pitch, lod;
 438    unsigned layer_offset, x_offset, y_offset;
 439    uint32_t *dw;
 440
 441    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 442
 443    surface_type = ilo_gpe_gen6_translate_texture(tex->base.target);
 444    assert(surface_type != GEN6_SURFTYPE_BUFFER);
 445
 446    if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && tex->separate_s8)
 447       format = PIPE_FORMAT_Z32_FLOAT;
 448
 449    if (is_rt)
 450       surface_format = ilo_translate_render_format(format);
 451    else
 452       surface_format = ilo_translate_texture_format(format);
 453    assert(surface_format >= 0);
 454
 455    width = tex->base.width0;
 456    height = tex->base.height0;
 457    depth = (tex->base.target == PIPE_TEXTURE_3D) ?
 458       tex->base.depth0 : num_layers;
 459    pitch = tex->bo_stride;
 460
 461    if (surface_type == GEN6_SURFTYPE_CUBE) {
 462       /*
 463        * From the Ivy Bridge PRM, volume 4 part 1, page 70:
 464        *
 465        *     "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of
 466        *      this field is [0,340], indicating the number of cube array
 467        *      elements (equal to the number of underlying 2D array elements
 468        *      divided by 6). For other surfaces, this field must be zero."
 469        *
 470        * When is_rt is true, we treat the texture as a 2D one to avoid the
 471        * restriction.
 472        */
 473       if (is_rt) {
 474          surface_type = GEN6_SURFTYPE_2D;
 475       }
 476       else {
 477          assert(num_layers % 6 == 0);
 478          depth = num_layers / 6;
 479       }
 480    }
 481
 482    /* sanity check the size */
 483    assert(width >= 1 && height >= 1 && depth >= 1 && pitch >= 1);
 484    assert(first_layer < 2048 && num_layers <= 2048);
 485    switch (surface_type) {
 486    case GEN6_SURFTYPE_1D:
 487       assert(width <= 16384 && height == 1 && depth <= 2048);
 488       break;
 489    case GEN6_SURFTYPE_2D:
 490       assert(width <= 16384 && height <= 16384 && depth <= 2048);
 491       break;
 492    case GEN6_SURFTYPE_3D:
 493       assert(width <= 2048 && height <= 2048 && depth <= 2048);
 494       if (!is_rt)
 495          assert(first_layer == 0);
 496       break;
 497    case GEN6_SURFTYPE_CUBE:
 498       assert(width <= 16384 && height <= 16384 && depth <= 86);
 499       assert(width == height);
 500       if (is_rt)
 501          assert(first_layer == 0);
 502       break;
 503    default:
 504       assert(!"unexpected surface type");
 505       break;
 506    }
 507
 508    if (is_rt) {
 509       assert(num_levels == 1);
 510       lod = first_level;
 511    }
 512    else {
 513       lod = num_levels - 1;
 514    }
 515
 516    /*
 517     * Offset to the layer.  When rendering, the hardware requires LOD and
 518     * Depth to be the same for all render targets and the depth buffer.  We
 519     * need to offset to the layer manually and always set LOD and Depth to 0.
 520     */
 521    if (offset_to_layer) {
 522       /* we lose the capability for layered rendering */
 523       assert(is_rt && num_layers == 1);
 524
 525       layer_offset = ilo_texture_get_slice_offset(tex,
 526             first_level, first_layer, &x_offset, &y_offset);
 527
 528       assert(x_offset % 4 == 0);
 529       assert(y_offset % 2 == 0);
 530       x_offset /= 4;
 531       y_offset /= 2;
 532
 533       /* derive the size for the LOD */
 534       width = u_minify(width, first_level);
 535       height = u_minify(height, first_level);
 536
 537       first_level = 0;
 538       first_layer = 0;
 539
 540       lod = 0;
 541       depth = 1;
 542    }
 543    else {
 544       layer_offset = 0;
 545       x_offset = 0;
 546       y_offset = 0;
 547    }
 548
 549    /*
 550     * From the Ivy Bridge PRM, volume 4 part 1, page 68:
 551     *
 552     *     "The Base Address for linear render target surfaces and surfaces
 553     *      accessed with the typed surface read/write data port messages must
 554     *      be element-size aligned, for non-YUV surface formats, or a multiple
 555     *      of 2 element-sizes for YUV surface formats.  Other linear surfaces
 556     *      have no alignment requirements (byte alignment is sufficient)."
 557     *
 558     * From the Ivy Bridge PRM, volume 4 part 1, page 70:
 559     *
 560     *     "For linear render target surfaces and surfaces accessed with the
 561     *      typed data port messages, the pitch must be a multiple of the
 562     *      element size for non-YUV surface formats. Pitch must be a multiple
 563     *      of 2 * element size for YUV surface formats. For linear surfaces
 564     *      with Surface Type of SURFTYPE_STRBUF, the pitch must be a multiple
 565     *      of 4 bytes.For other linear surfaces, the pitch can be any multiple
 566     *      of bytes."
 567     *
 568     * From the Ivy Bridge PRM, volume 4 part 1, page 74:
 569     *
 570     *     "For linear surfaces, this field (X Offset) must be zero."
 571     */
 572    if (tex->tiling == INTEL_TILING_NONE) {
 573       if (is_rt) {
 574          const int elem_size = util_format_get_blocksize(format);
 575          assert(layer_offset % elem_size == 0);
 576          assert(pitch % elem_size == 0);
 577       }
 578
 579       assert(!x_offset);
 580    }
 581
 582    STATIC_ASSERT(Elements(surf->payload) >= 8);
 583    dw = surf->payload;
 584
 585    dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
 586            surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT |
 587            ilo_gpe_gen6_translate_winsys_tiling(tex->tiling) << 13;
 588
 589    /*
 590     * From the Ivy Bridge PRM, volume 4 part 1, page 63:
 591     *
 592     *     "If this field (Surface Array) is enabled, the Surface Type must be
 593     *      SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
 594     *      disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
 595     *      SURFTYPE_CUBE, the Depth field must be set to zero."
 596     *
 597     * For non-3D sampler surfaces, resinfo (the sampler message) always
 598     * returns zero for the number of layers when this field is not set.
 599     */
 600    if (surface_type != GEN6_SURFTYPE_3D) {
 601       if (util_resource_is_array_texture(&tex->base))
 602          dw[0] |= GEN7_SURFACE_DW0_IS_ARRAY;
 603       else
 604          assert(depth == 1);
 605    }
 606
 607    if (tex->valign_4)
 608       dw[0] |= GEN7_SURFACE_DW0_VALIGN_4;
 609
 610    if (tex->halign_8)
 611       dw[0] |= GEN7_SURFACE_DW0_HALIGN_8;
 612
 613    if (tex->array_spacing_full)
 614       dw[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL;
 615    else
 616       dw[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
 617
 618    if (is_rt)
 619       dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
 620
 621    if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt)
 622       dw[0] |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
 623
 624    dw[1] = layer_offset;
 625
 626    dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_DW2_HEIGHT) |
 627            SET_FIELD(width - 1, GEN7_SURFACE_DW2_WIDTH);
 628
 629    dw[3] = SET_FIELD(depth - 1, GEN7_SURFACE_DW3_DEPTH) |
 630            (pitch - 1);
 631
 632    dw[4] = first_layer << 18 |
 633            (num_layers - 1) << 7;
 634
 635    /*
 636     * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
 637     * means the samples are interleaved.  The layouts are the same when the
 638     * number of samples is 1.
 639     */
 640    if (tex->interleaved && tex->base.nr_samples > 1) {
 641       assert(!is_rt);
 642       dw[4] |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL;
 643    }
 644    else {
 645       dw[4] |= GEN7_SURFACE_DW4_MSFMT_MSS;
 646    }
 647
 648    if (tex->base.nr_samples > 4)
 649       dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8;
 650    else if (tex->base.nr_samples > 2)
 651       dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4;
 652    else
 653       dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1;
 654
 655    dw[5] = x_offset << GEN7_SURFACE_DW5_X_OFFSET__SHIFT |
 656            y_offset << GEN7_SURFACE_DW5_Y_OFFSET__SHIFT |
 657            SET_FIELD(first_level, GEN7_SURFACE_DW5_MIN_LOD) |
 658            lod;
 659
 660    dw[6] = 0;
 661    dw[7] = 0;
 662
 663    if (dev->gen >= ILO_GEN(7.5)) {
 664       dw[7] |= SET_FIELD(GEN75_SCS_RED,   GEN75_SURFACE_DW7_SCS_R) |
 665                SET_FIELD(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
 666                SET_FIELD(GEN75_SCS_BLUE,  GEN75_SURFACE_DW7_SCS_B) |
 667                SET_FIELD(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
 668    }
 669
 670    /* do not increment reference count */
 671    surf->bo = tex->bo;
 672 }