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[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "brw_defines.h"
29 #include "intel_reg.h"
30
31 #include "ilo_cp.h"
32 #include "ilo_format.h"
33 #include "ilo_resource.h"
34 #include "ilo_shader.h"
35 #include "ilo_gpe_gen7.h"
36
37 static void
38 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
39 struct ilo_cp *cp)
40 {
41 assert(!"GPGPU_WALKER unsupported");
42 }
43
44 static void
45 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
46 uint32_t clear_val,
47 struct ilo_cp *cp)
48 {
49 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
50 const uint8_t cmd_len = 3;
51
52 ILO_GPE_VALID_GEN(dev, 7, 7);
53
54 ilo_cp_begin(cp, cmd_len);
55 ilo_cp_write(cp, cmd | (cmd_len - 2));
56 ilo_cp_write(cp, clear_val);
57 ilo_cp_write(cp, 1);
58 ilo_cp_end(cp);
59 }
60
61 static void
62 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
63 int subop, uint32_t pointer,
64 struct ilo_cp *cp)
65 {
66 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
67 const uint8_t cmd_len = 2;
68
69 ILO_GPE_VALID_GEN(dev, 7, 7);
70
71 ilo_cp_begin(cp, cmd_len);
72 ilo_cp_write(cp, cmd | (cmd_len - 2));
73 ilo_cp_write(cp, pointer);
74 ilo_cp_end(cp);
75 }
76
77 static void
78 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
79 uint32_t color_calc_state,
80 struct ilo_cp *cp)
81 {
82 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
83 }
84
85 static void
86 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
87 const struct ilo_shader *gs,
88 int num_samplers,
89 struct ilo_cp *cp)
90 {
91 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
92 const uint8_t cmd_len = 7;
93 uint32_t dw2, dw4, dw5;
94 int max_threads;
95
96 ILO_GPE_VALID_GEN(dev, 7, 7);
97
98 switch (dev->gen) {
99 case ILO_GEN(7):
100 max_threads = (dev->gt == 2) ? 128 : 36;
101 break;
102 default:
103 max_threads = 1;
104 break;
105 }
106
107 if (!gs) {
108 ilo_cp_begin(cp, cmd_len);
109 ilo_cp_write(cp, cmd | (cmd_len - 2));
110 ilo_cp_write(cp, 0);
111 ilo_cp_write(cp, 0);
112 ilo_cp_write(cp, 0);
113 ilo_cp_write(cp, 0);
114 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
115 ilo_cp_write(cp, 0);
116 ilo_cp_end(cp);
117 return;
118 }
119
120 dw2 = ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
121
122 dw4 = ((gs->in.count + 1) / 2) << GEN6_GS_URB_READ_LENGTH_SHIFT |
123 GEN7_GS_INCLUDE_VERTEX_HANDLES |
124 0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT |
125 gs->in.start_grf << GEN6_GS_DISPATCH_START_GRF_SHIFT;
126
127 dw5 = (max_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT |
128 GEN6_GS_STATISTICS_ENABLE |
129 GEN6_GS_ENABLE;
130
131 ilo_cp_begin(cp, cmd_len);
132 ilo_cp_write(cp, cmd | (cmd_len - 2));
133 ilo_cp_write(cp, gs->cache_offset);
134 ilo_cp_write(cp, dw2);
135 ilo_cp_write(cp, 0); /* scratch */
136 ilo_cp_write(cp, dw4);
137 ilo_cp_write(cp, dw5);
138 ilo_cp_write(cp, 0);
139 ilo_cp_end(cp);
140 }
141
142 static void
143 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
144 const struct pipe_rasterizer_state *rasterizer,
145 const struct pipe_surface *zs_surf,
146 struct ilo_cp *cp)
147 {
148 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
149 const uint8_t cmd_len = 7;
150 uint32_t dw[6];
151
152 ILO_GPE_VALID_GEN(dev, 7, 7);
153
154 ilo_gpe_gen6_fill_3dstate_sf_raster(dev, rasterizer,
155 1, (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE, true,
156 dw, Elements(dw));
157
158 ilo_cp_begin(cp, cmd_len);
159 ilo_cp_write(cp, cmd | (cmd_len - 2));
160 ilo_cp_write_multi(cp, dw, 6);
161 ilo_cp_end(cp);
162 }
163
164 static void
165 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
166 const struct ilo_shader *fs,
167 const struct pipe_rasterizer_state *rasterizer,
168 bool cc_may_kill,
169 struct ilo_cp *cp)
170 {
171 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
172 const uint8_t cmd_len = 3;
173 const int num_samples = 1;
174 uint32_t dw1, dw2;
175
176 ILO_GPE_VALID_GEN(dev, 7, 7);
177
178 dw1 = GEN7_WM_STATISTICS_ENABLE |
179 GEN7_WM_LINE_AA_WIDTH_2_0;
180
181 if (false) {
182 dw1 |= GEN7_WM_DEPTH_CLEAR;
183 dw1 |= GEN7_WM_DEPTH_RESOLVE;
184 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
185 }
186
187 if (fs) {
188 /*
189 * Set this bit if
190 *
191 * a) fs writes colors and color is not masked, or
192 * b) fs writes depth, or
193 * c) fs or cc kills
194 */
195 dw1 |= GEN7_WM_DISPATCH_ENABLE;
196
197 /*
198 * From the Ivy Bridge PRM, volume 2 part 1, page 278:
199 *
200 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that
201 * the PS kernel or color calculator has the ability to kill
202 * (discard) pixels or samples, other than due to depth or stencil
203 * testing. This bit is required to be ENABLED in the following
204 * situations:
205 *
206 * - The API pixel shader program contains "killpix" or "discard"
207 * instructions, or other code in the pixel shader kernel that
208 * can cause the final pixel mask to differ from the pixel mask
209 * received on dispatch.
210 *
211 * - A sampler with chroma key enabled with kill pixel mode is used
212 * by the pixel shader.
213 *
214 * - Any render target has Alpha Test Enable or AlphaToCoverage
215 * Enable enabled.
216 *
217 * - The pixel shader kernel generates and outputs oMask.
218 *
219 * Note: As ClipDistance clipping is fully supported in hardware
220 * and therefore not via PS instructions, there should be no need
221 * to ENABLE this bit due to ClipDistance clipping."
222 */
223 if (fs->has_kill || cc_may_kill)
224 dw1 |= GEN7_WM_KILL_ENABLE;
225
226 if (fs->out.has_pos)
227 dw1 |= GEN7_WM_PSCDEPTH_ON;
228 if (fs->in.has_pos)
229 dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
230
231 dw1 |= fs->in.barycentric_interpolation_mode <<
232 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
233 }
234 else if (cc_may_kill) {
235 dw1 |= GEN7_WM_DISPATCH_ENABLE |
236 GEN7_WM_KILL_ENABLE;
237 }
238
239 dw1 |= GEN7_WM_POSITION_ZW_PIXEL;
240
241 /* same value as in 3DSTATE_SF */
242 if (rasterizer->line_smooth)
243 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0;
244
245 if (rasterizer->poly_stipple_enable)
246 dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
247 if (rasterizer->line_stipple_enable)
248 dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
249
250 if (rasterizer->bottom_edge_rule)
251 dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
252
253 if (num_samples > 1) {
254 if (rasterizer->multisample)
255 dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
256 else
257 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
258
259 dw2 = GEN7_WM_MSDISPMODE_PERPIXEL;
260 }
261 else {
262 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
263
264 dw2 = GEN7_WM_MSDISPMODE_PERSAMPLE;
265 }
266
267 ilo_cp_begin(cp, cmd_len);
268 ilo_cp_write(cp, cmd | (cmd_len - 2));
269 ilo_cp_write(cp, dw1);
270 ilo_cp_write(cp, dw2);
271 ilo_cp_end(cp);
272 }
273
274 static void
275 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
276 int subop,
277 const uint32_t *bufs, const int *sizes,
278 int num_bufs,
279 struct ilo_cp *cp)
280 {
281 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
282 const uint8_t cmd_len = 7;
283 uint32_t dw[6];
284 int total_read_length, i;
285
286 ILO_GPE_VALID_GEN(dev, 7, 7);
287
288 /* VS, HS, DS, GS, and PS variants */
289 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
290
291 assert(num_bufs <= 4);
292
293 dw[0] = 0;
294 dw[1] = 0;
295
296 total_read_length = 0;
297 for (i = 0; i < 4; i++) {
298 int read_len;
299
300 /*
301 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
302 *
303 * "Constant buffers must be enabled in order from Constant Buffer 0
304 * to Constant Buffer 3 within this command. For example, it is
305 * not allowed to enable Constant Buffer 1 by programming a
306 * non-zero value in the VS Constant Buffer 1 Read Length without a
307 * non-zero value in VS Constant Buffer 0 Read Length."
308 */
309 if (i >= num_bufs || !sizes[i]) {
310 for (; i < 4; i++) {
311 assert(i >= num_bufs || !sizes[i]);
312 dw[2 + i] = 0;
313 }
314 break;
315 }
316
317 /* read lengths are in 256-bit units */
318 read_len = (sizes[i] + 31) / 32;
319 /* the lower 5 bits are used for memory object control state */
320 assert(bufs[i] % 32 == 0);
321
322 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
323 dw[2 + i] = bufs[i];
324
325 total_read_length += read_len;
326 }
327
328 /*
329 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
330 *
331 * "The sum of all four read length fields must be less than or equal
332 * to the size of 64"
333 */
334 assert(total_read_length <= 64);
335
336 ilo_cp_begin(cp, cmd_len);
337 ilo_cp_write(cp, cmd | (cmd_len - 2));
338 ilo_cp_write_multi(cp, dw, 6);
339 ilo_cp_end(cp);
340 }
341
342 static void
343 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
344 const uint32_t *bufs, const int *sizes,
345 int num_bufs,
346 struct ilo_cp *cp)
347 {
348 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
349 }
350
351 static void
352 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
353 const uint32_t *bufs, const int *sizes,
354 int num_bufs,
355 struct ilo_cp *cp)
356 {
357 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
358 }
359
360 static void
361 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
362 const uint32_t *bufs, const int *sizes,
363 int num_bufs,
364 struct ilo_cp *cp)
365 {
366 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
367 }
368
369 static void
370 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
371 unsigned sample_mask,
372 int num_samples,
373 struct ilo_cp *cp)
374 {
375 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
376 const uint8_t cmd_len = 2;
377 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
378
379 ILO_GPE_VALID_GEN(dev, 7, 7);
380
381 /*
382 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
383 *
384 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
385 * (Sample Mask) must be zero.
386 *
387 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
388 * must be zero."
389 */
390 sample_mask &= valid_mask;
391
392 ilo_cp_begin(cp, cmd_len);
393 ilo_cp_write(cp, cmd | (cmd_len - 2));
394 ilo_cp_write(cp, sample_mask);
395 ilo_cp_end(cp);
396 }
397
398 static void
399 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
400 const uint32_t *bufs, const int *sizes,
401 int num_bufs,
402 struct ilo_cp *cp)
403 {
404 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
405 }
406
407 static void
408 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
409 const uint32_t *bufs, const int *sizes,
410 int num_bufs,
411 struct ilo_cp *cp)
412 {
413 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
414 }
415
416 static void
417 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
418 const struct ilo_shader *hs,
419 int max_threads, int num_samplers,
420 struct ilo_cp *cp)
421 {
422 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
423 const uint8_t cmd_len = 7;
424 uint32_t dw1, dw2, dw5;
425
426 ILO_GPE_VALID_GEN(dev, 7, 7);
427
428 if (!hs) {
429 ilo_cp_begin(cp, cmd_len);
430 ilo_cp_write(cp, cmd | (cmd_len - 2));
431 ilo_cp_write(cp, 0);
432 ilo_cp_write(cp, 0);
433 ilo_cp_write(cp, 0);
434 ilo_cp_write(cp, 0);
435 ilo_cp_write(cp, 0);
436 ilo_cp_write(cp, 0);
437 ilo_cp_end(cp);
438
439 return;
440 }
441
442 dw1 = (num_samplers + 3) / 4 << 27 |
443 0 << 18 |
444 (max_threads - 1);
445 if (false)
446 dw1 |= 1 << 16;
447
448 dw2 = 1 << 31 | /* HS Enable */
449 1 << 29 | /* HS Statistics Enable */
450 0; /* Instance Count */
451
452 dw5 = hs->in.start_grf << 19 |
453 0 << 11 |
454 0 << 4;
455
456 ilo_cp_begin(cp, cmd_len);
457 ilo_cp_write(cp, cmd | (cmd_len - 2));
458 ilo_cp_write(cp, dw1);
459 ilo_cp_write(cp, dw2);
460 ilo_cp_write(cp, hs->cache_offset);
461 ilo_cp_write(cp, 0);
462 ilo_cp_write(cp, dw5);
463 ilo_cp_write(cp, 0);
464 ilo_cp_end(cp);
465 }
466
467 static void
468 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
469 struct ilo_cp *cp)
470 {
471 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
472 const uint8_t cmd_len = 4;
473
474 ILO_GPE_VALID_GEN(dev, 7, 7);
475
476 ilo_cp_begin(cp, cmd_len);
477 ilo_cp_write(cp, cmd | (cmd_len - 2));
478 ilo_cp_write(cp, 0);
479 ilo_cp_write(cp, 0);
480 ilo_cp_write(cp, 0);
481 ilo_cp_end(cp);
482 }
483
484 static void
485 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
486 const struct ilo_shader *ds,
487 int max_threads, int num_samplers,
488 struct ilo_cp *cp)
489 {
490 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
491 const uint8_t cmd_len = 6;
492 uint32_t dw2, dw4, dw5;
493
494 ILO_GPE_VALID_GEN(dev, 7, 7);
495
496 if (!ds) {
497 ilo_cp_begin(cp, cmd_len);
498 ilo_cp_write(cp, cmd | (cmd_len - 2));
499 ilo_cp_write(cp, 0);
500 ilo_cp_write(cp, 0);
501 ilo_cp_write(cp, 0);
502 ilo_cp_write(cp, 0);
503 ilo_cp_write(cp, 0);
504 ilo_cp_end(cp);
505
506 return;
507 }
508
509 dw2 = (num_samplers + 3) / 4 << 27 |
510 0 << 18 |
511 (max_threads - 1);
512 if (false)
513 dw2 |= 1 << 16;
514
515 dw4 = ds->in.start_grf << 20 |
516 0 << 11 |
517 0 << 4;
518
519 dw5 = (max_threads - 1) << 25 |
520 1 << 10 |
521 1;
522
523 ilo_cp_begin(cp, cmd_len);
524 ilo_cp_write(cp, cmd | (cmd_len - 2));
525 ilo_cp_write(cp, ds->cache_offset);
526 ilo_cp_write(cp, dw2);
527 ilo_cp_write(cp, 0);
528 ilo_cp_write(cp, dw4);
529 ilo_cp_write(cp, dw5);
530 ilo_cp_end(cp);
531 }
532
533 static void
534 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
535 unsigned buffer_mask,
536 int vertex_attrib_count,
537 bool rasterizer_discard,
538 struct ilo_cp *cp)
539 {
540 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
541 const uint8_t cmd_len = 3;
542 const bool enable = (buffer_mask != 0);
543 uint32_t dw1, dw2;
544 int read_len;
545
546 ILO_GPE_VALID_GEN(dev, 7, 7);
547
548 if (!enable) {
549 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
550 if (rasterizer_discard)
551 dw1 |= SO_RENDERING_DISABLE;
552
553 dw2 = 0;
554
555 ilo_cp_begin(cp, cmd_len);
556 ilo_cp_write(cp, cmd | (cmd_len - 2));
557 ilo_cp_write(cp, dw1);
558 ilo_cp_write(cp, dw2);
559 ilo_cp_end(cp);
560 return;
561 }
562
563 read_len = (vertex_attrib_count + 1) / 2;
564 if (!read_len)
565 read_len = 1;
566
567 dw1 = SO_FUNCTION_ENABLE |
568 0 << SO_RENDER_STREAM_SELECT_SHIFT |
569 SO_STATISTICS_ENABLE |
570 buffer_mask << 8;
571
572 if (rasterizer_discard)
573 dw1 |= SO_RENDERING_DISABLE;
574
575 /* API_OPENGL */
576 if (true)
577 dw1 |= SO_REORDER_TRAILING;
578
579 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
580 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
581 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
582 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
583 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
584 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
585 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
586 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
587
588 ilo_cp_begin(cp, cmd_len);
589 ilo_cp_write(cp, cmd | (cmd_len - 2));
590 ilo_cp_write(cp, dw1);
591 ilo_cp_write(cp, dw2);
592 ilo_cp_end(cp);
593 }
594
595 static void
596 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
597 const struct pipe_rasterizer_state *rasterizer,
598 const struct ilo_shader *fs,
599 const struct ilo_shader *last_sh,
600 struct ilo_cp *cp)
601 {
602 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
603 const uint8_t cmd_len = 14;
604 uint32_t dw[13];
605
606 ILO_GPE_VALID_GEN(dev, 7, 7);
607
608 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer,
609 fs, last_sh, dw, Elements(dw));
610
611 ilo_cp_begin(cp, cmd_len);
612 ilo_cp_write(cp, cmd | (cmd_len - 2));
613 ilo_cp_write_multi(cp, dw, 13);
614 ilo_cp_end(cp);
615 }
616
617 static void
618 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
619 const struct ilo_shader *fs,
620 int num_samplers, bool dual_blend,
621 struct ilo_cp *cp)
622 {
623 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
624 const uint8_t cmd_len = 8;
625 uint32_t dw2, dw4, dw5;
626 int max_threads;
627
628 ILO_GPE_VALID_GEN(dev, 7, 7);
629
630 /* see brwCreateContext() */
631 max_threads = (dev->gt == 2) ? 172 : 48;
632
633 if (!fs) {
634 ilo_cp_begin(cp, cmd_len);
635 ilo_cp_write(cp, cmd | (cmd_len - 2));
636 ilo_cp_write(cp, 0);
637 ilo_cp_write(cp, 0);
638 ilo_cp_write(cp, 0);
639 /* GPU hangs if none of the dispatch enable bits is set */
640 ilo_cp_write(cp, (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT |
641 GEN7_PS_8_DISPATCH_ENABLE);
642 ilo_cp_write(cp, 0);
643 ilo_cp_write(cp, 0);
644 ilo_cp_write(cp, 0);
645 ilo_cp_end(cp);
646
647 return;
648 }
649
650 dw2 = (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT |
651 0 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
652 if (false)
653 dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
654
655 dw4 = (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT |
656 GEN7_PS_POSOFFSET_NONE;
657
658 if (false)
659 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
660 if (fs->in.count)
661 dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
662 if (dual_blend)
663 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
664
665 if (fs->dispatch_16)
666 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
667 else
668 dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
669
670 dw5 = fs->in.start_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0 |
671 0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_1 |
672 0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
673
674 ilo_cp_begin(cp, cmd_len);
675 ilo_cp_write(cp, cmd | (cmd_len - 2));
676 ilo_cp_write(cp, fs->cache_offset);
677 ilo_cp_write(cp, dw2);
678 ilo_cp_write(cp, 0); /* scratch */
679 ilo_cp_write(cp, dw4);
680 ilo_cp_write(cp, dw5);
681 ilo_cp_write(cp, 0); /* kernel 1 */
682 ilo_cp_write(cp, 0); /* kernel 2 */
683 ilo_cp_end(cp);
684 }
685
686 static void
687 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
688 uint32_t sf_clip_viewport,
689 struct ilo_cp *cp)
690 {
691 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
692 }
693
694 static void
695 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
696 uint32_t cc_viewport,
697 struct ilo_cp *cp)
698 {
699 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
700 }
701
702 static void
703 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
704 uint32_t blend_state,
705 struct ilo_cp *cp)
706 {
707 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
708 }
709
710 static void
711 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
712 uint32_t depth_stencil_state,
713 struct ilo_cp *cp)
714 {
715 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
716 }
717
718 static void
719 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
720 uint32_t binding_table,
721 struct ilo_cp *cp)
722 {
723 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
724 }
725
726 static void
727 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
728 uint32_t binding_table,
729 struct ilo_cp *cp)
730 {
731 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
732 }
733
734 static void
735 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
736 uint32_t binding_table,
737 struct ilo_cp *cp)
738 {
739 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
740 }
741
742 static void
743 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
744 uint32_t binding_table,
745 struct ilo_cp *cp)
746 {
747 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
748 }
749
750 static void
751 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
752 uint32_t binding_table,
753 struct ilo_cp *cp)
754 {
755 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
756 }
757
758 static void
759 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
760 uint32_t sampler_state,
761 struct ilo_cp *cp)
762 {
763 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
764 }
765
766 static void
767 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
768 uint32_t sampler_state,
769 struct ilo_cp *cp)
770 {
771 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
772 }
773
774 static void
775 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
776 uint32_t sampler_state,
777 struct ilo_cp *cp)
778 {
779 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
780 }
781
782 static void
783 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
784 uint32_t sampler_state,
785 struct ilo_cp *cp)
786 {
787 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
788 }
789
790 static void
791 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
792 uint32_t sampler_state,
793 struct ilo_cp *cp)
794 {
795 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
796 }
797
798 static void
799 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
800 int subop, int offset, int size,
801 int entry_size,
802 struct ilo_cp *cp)
803 {
804 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
805 const uint8_t cmd_len = 2;
806 const int row_size = 64; /* 512 bits */
807 int alloc_size, num_entries, min_entries, max_entries;
808
809 ILO_GPE_VALID_GEN(dev, 7, 7);
810
811 /* VS, HS, DS, and GS variants */
812 assert(subop >= 0x30 && subop <= 0x33);
813
814 /* in multiples of 8KB */
815 assert(offset % 8192 == 0);
816 offset /= 8192;
817
818 /* in multiple of 512-bit rows */
819 alloc_size = (entry_size + row_size - 1) / row_size;
820 if (!alloc_size)
821 alloc_size = 1;
822
823 /*
824 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
825 *
826 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
827 * cause performance to decrease due to banking in the URB. Element
828 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
829 */
830 if (subop == 0x30 && alloc_size == 5)
831 alloc_size = 6;
832
833 /* in multiples of 8 */
834 num_entries = (size / row_size / alloc_size) & ~7;
835
836 switch (subop) {
837 case 0x30: /* 3DSTATE_URB_VS */
838 min_entries = 32;
839 max_entries = (dev->gt == 2) ? 704 : 512;
840
841 assert(num_entries >= min_entries);
842 if (num_entries > max_entries)
843 num_entries = max_entries;
844 break;
845 case 0x31: /* 3DSTATE_URB_HS */
846 max_entries = (dev->gt == 2) ? 64 : 32;
847 if (num_entries > max_entries)
848 num_entries = max_entries;
849 break;
850 case 0x32: /* 3DSTATE_URB_DS */
851 if (num_entries)
852 assert(num_entries >= 138);
853 break;
854 case 0x33: /* 3DSTATE_URB_GS */
855 max_entries = (dev->gt == 2) ? 320 : 192;
856 if (num_entries > max_entries)
857 num_entries = max_entries;
858 break;
859 default:
860 break;
861 }
862
863 ilo_cp_begin(cp, cmd_len);
864 ilo_cp_write(cp, cmd | (cmd_len - 2));
865 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
866 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
867 num_entries);
868 ilo_cp_end(cp);
869 }
870
871 static void
872 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
873 int offset, int size, int entry_size,
874 struct ilo_cp *cp)
875 {
876 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
877 }
878
879 static void
880 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
881 int offset, int size, int entry_size,
882 struct ilo_cp *cp)
883 {
884 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
885 }
886
887 static void
888 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
889 int offset, int size, int entry_size,
890 struct ilo_cp *cp)
891 {
892 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
893 }
894
895 static void
896 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
897 int offset, int size, int entry_size,
898 struct ilo_cp *cp)
899 {
900 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
901 }
902
903 static void
904 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
905 int subop, int offset, int size,
906 struct ilo_cp *cp)
907 {
908 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
909 const uint8_t cmd_len = 2;
910 int end;
911
912 ILO_GPE_VALID_GEN(dev, 7, 7);
913
914 /* VS, HS, DS, GS, and PS variants */
915 assert(subop >= 0x12 && subop <= 0x16);
916
917 /*
918 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
919 *
920 * "(A table that says the maximum size of each constant buffer is
921 * 16KB")
922 *
923 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
924 *
925 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
926 * may not exceed the maximum value of the Constant Buffer Size."
927 *
928 * Thus, the valid range of buffer end is [0KB, 16KB].
929 */
930 end = (offset + size) / 1024;
931 if (end > 16) {
932 assert(!"invalid constant buffer end");
933 end = 16;
934 }
935
936 /* the valid range of buffer offset is [0KB, 15KB] */
937 offset = (offset + 1023) / 1024;
938 if (offset > 15) {
939 assert(!"invalid constant buffer offset");
940 offset = 15;
941 }
942
943 if (offset > end) {
944 assert(!size);
945 offset = end;
946 }
947
948 /* the valid range of buffer size is [0KB, 15KB] */
949 size = end - offset;
950 if (size > 15) {
951 assert(!"invalid constant buffer size");
952 size = 15;
953 }
954
955 ilo_cp_begin(cp, cmd_len);
956 ilo_cp_write(cp, cmd | (cmd_len - 2));
957 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
958 size);
959 ilo_cp_end(cp);
960 }
961
962 static void
963 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
964 int offset, int size,
965 struct ilo_cp *cp)
966 {
967 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
968 }
969
970 static void
971 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
972 int offset, int size,
973 struct ilo_cp *cp)
974 {
975 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
976 }
977
978 static void
979 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
980 int offset, int size,
981 struct ilo_cp *cp)
982 {
983 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
984 }
985
986 static void
987 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
988 int offset, int size,
989 struct ilo_cp *cp)
990 {
991 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
992 }
993
994 static void
995 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
996 int offset, int size,
997 struct ilo_cp *cp)
998 {
999 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
1000 }
1001
1002 static void
1003 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
1004 const struct pipe_stream_output_info *so_info,
1005 const struct ilo_shader *sh,
1006 struct ilo_cp *cp)
1007 {
1008 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
1009 uint16_t cmd_len;
1010 int buffer_selects, num_entries, i;
1011 uint16_t so_decls[128];
1012
1013 ILO_GPE_VALID_GEN(dev, 7, 7);
1014
1015 buffer_selects = 0;
1016 num_entries = 0;
1017
1018 if (so_info) {
1019 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
1020
1021 memset(buffer_offsets, 0, sizeof(buffer_offsets));
1022
1023 for (i = 0; i < so_info->num_outputs; i++) {
1024 unsigned decl, buf, attr, mask;
1025
1026 buf = so_info->output[i].output_buffer;
1027
1028 /* pad with holes */
1029 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
1030 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
1031 int num_dwords;
1032
1033 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1034 if (num_dwords > 4)
1035 num_dwords = 4;
1036
1037 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1038 SO_DECL_HOLE_FLAG |
1039 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1040
1041 so_decls[num_entries++] = decl;
1042 buffer_offsets[buf] += num_dwords;
1043 }
1044
1045 /* figure out which attribute is sourced */
1046 for (attr = 0; attr < sh->out.count; attr++) {
1047 const int idx = sh->out.register_indices[attr];
1048 if (idx == so_info->output[i].register_index)
1049 break;
1050 }
1051
1052 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT;
1053
1054 if (attr < sh->out.count) {
1055 mask = ((1 << so_info->output[i].num_components) - 1) <<
1056 so_info->output[i].start_component;
1057
1058 /* PSIZE is at W channel */
1059 if (sh->out.semantic_names[attr] == TGSI_SEMANTIC_PSIZE) {
1060 assert(mask == 0x1);
1061 mask = (mask << 3) & 0xf;
1062 }
1063
1064 decl |= attr << SO_DECL_REGISTER_INDEX_SHIFT |
1065 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1066 }
1067 else {
1068 assert(!"stream output an undefined register");
1069 mask = (1 << so_info->output[i].num_components) - 1;
1070 decl |= SO_DECL_HOLE_FLAG |
1071 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1072 }
1073
1074 so_decls[num_entries++] = decl;
1075 buffer_selects |= 1 << buf;
1076 buffer_offsets[buf] += so_info->output[i].num_components;
1077 }
1078 }
1079
1080 /*
1081 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1082 *
1083 * "Errata: All 128 decls for all four streams must be included
1084 * whenever this command is issued. The "Num Entries [n]" fields still
1085 * contain the actual numbers of valid decls."
1086 *
1087 * Also note that "DWord Length" has 9 bits for this command, and the type
1088 * of cmd_len is thus uint16_t.
1089 */
1090 cmd_len = 2 * 128 + 3;
1091
1092 ilo_cp_begin(cp, cmd_len);
1093 ilo_cp_write(cp, cmd | (cmd_len - 2));
1094 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1095 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1096 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1097 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1098 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1099 0 << SO_NUM_ENTRIES_2_SHIFT |
1100 0 << SO_NUM_ENTRIES_1_SHIFT |
1101 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1102
1103 for (i = 0; i < num_entries; i++) {
1104 ilo_cp_write(cp, so_decls[i]);
1105 ilo_cp_write(cp, 0);
1106 }
1107 for (; i < 128; i++) {
1108 ilo_cp_write(cp, 0);
1109 ilo_cp_write(cp, 0);
1110 }
1111
1112 ilo_cp_end(cp);
1113 }
1114
1115 static void
1116 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1117 int index, int base, int stride,
1118 const struct pipe_stream_output_target *so_target,
1119 struct ilo_cp *cp)
1120 {
1121 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1122 const uint8_t cmd_len = 4;
1123 struct ilo_buffer *buf;
1124 int end;
1125
1126 ILO_GPE_VALID_GEN(dev, 7, 7);
1127
1128 if (!so_target || !so_target->buffer) {
1129 ilo_cp_begin(cp, cmd_len);
1130 ilo_cp_write(cp, cmd | (cmd_len - 2));
1131 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1132 ilo_cp_write(cp, 0);
1133 ilo_cp_write(cp, 0);
1134 ilo_cp_end(cp);
1135 return;
1136 }
1137
1138 buf = ilo_buffer(so_target->buffer);
1139
1140 /* DWord-aligned */
1141 assert(stride % 4 == 0 && base % 4 == 0);
1142 assert(so_target->buffer_offset % 4 == 0);
1143
1144 stride &= ~3;
1145 base = (base + so_target->buffer_offset) & ~3;
1146 end = (base + so_target->buffer_size) & ~3;
1147
1148 ilo_cp_begin(cp, cmd_len);
1149 ilo_cp_write(cp, cmd | (cmd_len - 2));
1150 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1151 stride);
1152 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1153 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1154 ilo_cp_end(cp);
1155 }
1156
1157 static void
1158 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1159 const struct pipe_draw_info *info,
1160 bool rectlist,
1161 struct ilo_cp *cp)
1162 {
1163 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1164 const uint8_t cmd_len = 7;
1165 const int prim = (rectlist) ?
1166 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1167 const int vb_access = (info->indexed) ?
1168 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1169 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1170
1171 ILO_GPE_VALID_GEN(dev, 7, 7);
1172
1173 ilo_cp_begin(cp, cmd_len);
1174 ilo_cp_write(cp, cmd | (cmd_len - 2));
1175 ilo_cp_write(cp, vb_access | prim);
1176 ilo_cp_write(cp, info->count);
1177 ilo_cp_write(cp, info->start);
1178 ilo_cp_write(cp, info->instance_count);
1179 ilo_cp_write(cp, info->start_instance);
1180 ilo_cp_write(cp, info->index_bias);
1181 ilo_cp_end(cp);
1182 }
1183
1184 static uint32_t
1185 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1186 const struct ilo_viewport_cso *viewports,
1187 unsigned num_viewports,
1188 struct ilo_cp *cp)
1189 {
1190 const int state_align = 64 / 4;
1191 const int state_len = 16 * num_viewports;
1192 uint32_t state_offset, *dw;
1193 unsigned i;
1194
1195 ILO_GPE_VALID_GEN(dev, 7, 7);
1196
1197 /*
1198 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1199 *
1200 * "The viewport-specific state used by both the SF and CL units
1201 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1202 * of which contains the DWords described below. The start of each
1203 * element is spaced 16 DWords apart. The location of first element of
1204 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1205 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1206 */
1207 assert(num_viewports && num_viewports <= 16);
1208
1209 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1210 state_len, state_align, &state_offset);
1211
1212 for (i = 0; i < num_viewports; i++) {
1213 const struct ilo_viewport_cso *vp = &viewports[i];
1214
1215 dw[0] = fui(vp->m00);
1216 dw[1] = fui(vp->m11);
1217 dw[2] = fui(vp->m22);
1218 dw[3] = fui(vp->m30);
1219 dw[4] = fui(vp->m31);
1220 dw[5] = fui(vp->m32);
1221 dw[6] = 0;
1222 dw[7] = 0;
1223 dw[8] = fui(vp->min_gbx);
1224 dw[9] = fui(vp->max_gbx);
1225 dw[10] = fui(vp->min_gby);
1226 dw[11] = fui(vp->max_gby);
1227 dw[12] = 0;
1228 dw[13] = 0;
1229 dw[14] = 0;
1230 dw[15] = 0;
1231
1232 dw += 16;
1233 }
1234
1235 return state_offset;
1236 }
1237
1238 void
1239 ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info *dev,
1240 unsigned width, unsigned height,
1241 unsigned depth, unsigned level,
1242 struct ilo_view_surface *surf)
1243 {
1244 uint32_t *dw;
1245
1246 ILO_GPE_VALID_GEN(dev, 7, 7);
1247
1248 /*
1249 * From the Ivy Bridge PRM, volume 4 part 1, page 62:
1250 *
1251 * "A null surface is used in instances where an actual surface is not
1252 * bound. When a write message is generated to a null surface, no
1253 * actual surface is written to. When a read message (including any
1254 * sampling engine message) is generated to a null surface, the result
1255 * is all zeros. Note that a null surface type is allowed to be used
1256 * with all messages, even if it is not specificially indicated as
1257 * supported. All of the remaining fields in surface state are ignored
1258 * for null surfaces, with the following exceptions:
1259 *
1260 * * Width, Height, Depth, LOD, and Render Target View Extent fields
1261 * must match the depth buffer's corresponding state for all render
1262 * target surfaces, including null.
1263 * * All sampling engine and data port messages support null surfaces
1264 * with the above behavior, even if not mentioned as specifically
1265 * supported, except for the following:
1266 * * Data Port Media Block Read/Write messages.
1267 * * The Surface Type of a surface used as a render target (accessed
1268 * via the Data Port's Render Target Write message) must be the same
1269 * as the Surface Type of all other render targets and of the depth
1270 * buffer (defined in 3DSTATE_DEPTH_BUFFER), unless either the depth
1271 * buffer or render targets are SURFTYPE_NULL."
1272 *
1273 * From the Ivy Bridge PRM, volume 4 part 1, page 65:
1274 *
1275 * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must be
1276 * true"
1277 */
1278
1279 STATIC_ASSERT(Elements(surf->payload) >= 8);
1280 dw = surf->payload;
1281
1282 dw[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
1283 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
1284 BRW_SURFACE_TILED << 13;
1285
1286 dw[1] = 0;
1287
1288 dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT) |
1289 SET_FIELD(width - 1, GEN7_SURFACE_WIDTH);
1290
1291 dw[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH);
1292
1293 dw[4] = 0;
1294 dw[5] = level;
1295
1296 dw[6] = 0;
1297 dw[7] = 0;
1298
1299 surf->bo = NULL;
1300 }
1301
1302 void
1303 ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
1304 const struct ilo_buffer *buf,
1305 unsigned offset, unsigned size,
1306 unsigned struct_size,
1307 enum pipe_format elem_format,
1308 bool is_rt, bool render_cache_rw,
1309 struct ilo_view_surface *surf)
1310 {
1311 const bool typed = (elem_format != PIPE_FORMAT_NONE);
1312 const bool structured = (!typed && struct_size > 1);
1313 const int elem_size = (typed) ?
1314 util_format_get_blocksize(elem_format) : 1;
1315 int width, height, depth, pitch;
1316 int surface_type, surface_format, num_entries;
1317 uint32_t *dw;
1318
1319 ILO_GPE_VALID_GEN(dev, 7, 7);
1320
1321 surface_type = (structured) ? 5 : BRW_SURFACE_BUFFER;
1322
1323 surface_format = (typed) ?
1324 ilo_translate_color_format(elem_format) : BRW_SURFACEFORMAT_RAW;
1325
1326 num_entries = size / struct_size;
1327 /* see if there is enough space to fit another element */
1328 if (size % struct_size >= elem_size && !structured)
1329 num_entries++;
1330
1331 /*
1332 * From the Ivy Bridge PRM, volume 4 part 1, page 67:
1333 *
1334 * "For SURFTYPE_BUFFER render targets, this field (Surface Base
1335 * Address) specifies the base address of first element of the
1336 * surface. The surface is interpreted as a simple array of that
1337 * single element type. The address must be naturally-aligned to the
1338 * element size (e.g., a buffer containing R32G32B32A32_FLOAT elements
1339 * must be 16-byte aligned)
1340 *
1341 * For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
1342 * the base address of the first element of the surface, computed in
1343 * software by adding the surface base address to the byte offset of
1344 * the element in the buffer."
1345 */
1346 if (is_rt)
1347 assert(offset % elem_size == 0);
1348
1349 /*
1350 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
1351 *
1352 * "For typed buffer and structured buffer surfaces, the number of
1353 * entries in the buffer ranges from 1 to 2^27. For raw buffer
1354 * surfaces, the number of entries in the buffer is the number of
1355 * bytes which can range from 1 to 2^30."
1356 */
1357 assert(num_entries >= 1 &&
1358 num_entries <= 1 << ((typed || structured) ? 27 : 30));
1359
1360 /*
1361 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
1362 *
1363 * "For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
1364 * 11 if the Surface Format is RAW (the size of the buffer must be a
1365 * multiple of 4 bytes)."
1366 *
1367 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
1368 *
1369 * "For surfaces of type SURFTYPE_BUFFER and SURFTYPE_STRBUF, this
1370 * field (Surface Pitch) indicates the size of the structure."
1371 *
1372 * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the pitch
1373 * must be a multiple of 4 bytes."
1374 */
1375 if (structured)
1376 assert(struct_size % 4 == 0);
1377 else if (!typed)
1378 assert(num_entries % 4 == 0);
1379
1380 pitch = struct_size;
1381
1382 pitch--;
1383 num_entries--;
1384 /* bits [6:0] */
1385 width = (num_entries & 0x0000007f);
1386 /* bits [20:7] */
1387 height = (num_entries & 0x001fff80) >> 7;
1388 /* bits [30:21] */
1389 depth = (num_entries & 0x7fe00000) >> 21;
1390 /* limit to [26:21] */
1391 if (typed || structured)
1392 depth &= 0x3f;
1393
1394 STATIC_ASSERT(Elements(surf->payload) >= 8);
1395 dw = surf->payload;
1396
1397 dw[0] = surface_type << BRW_SURFACE_TYPE_SHIFT |
1398 surface_format << BRW_SURFACE_FORMAT_SHIFT;
1399 if (render_cache_rw)
1400 dw[0] |= BRW_SURFACE_RC_READ_WRITE;
1401
1402 dw[1] = offset;
1403
1404 dw[2] = SET_FIELD(height, GEN7_SURFACE_HEIGHT) |
1405 SET_FIELD(width, GEN7_SURFACE_WIDTH);
1406
1407 dw[3] = SET_FIELD(depth, BRW_SURFACE_DEPTH) |
1408 pitch;
1409
1410 dw[4] = 0;
1411 dw[5] = 0;
1412
1413 dw[6] = 0;
1414 dw[7] = 0;
1415
1416 /* do not increment reference count */
1417 surf->bo = buf->bo;
1418 }
1419
1420 void
1421 ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
1422 const struct ilo_texture *tex,
1423 enum pipe_format format,
1424 unsigned first_level,
1425 unsigned num_levels,
1426 unsigned first_layer,
1427 unsigned num_layers,
1428 bool is_rt, bool render_cache_rw,
1429 struct ilo_view_surface *surf)
1430 {
1431 int surface_type, surface_format;
1432 int width, height, depth, pitch, lod;
1433 unsigned layer_offset, x_offset, y_offset;
1434 uint32_t *dw;
1435
1436 ILO_GPE_VALID_GEN(dev, 7, 7);
1437
1438 surface_type = ilo_gpe_gen6_translate_texture(tex->base.target);
1439 assert(surface_type != BRW_SURFACE_BUFFER);
1440
1441 if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && tex->separate_s8)
1442 format = PIPE_FORMAT_Z32_FLOAT;
1443
1444 if (is_rt)
1445 surface_format = ilo_translate_render_format(format);
1446 else
1447 surface_format = ilo_translate_texture_format(format);
1448 assert(surface_format >= 0);
1449
1450 width = tex->base.width0;
1451 height = tex->base.height0;
1452 depth = (tex->base.target == PIPE_TEXTURE_3D) ?
1453 tex->base.depth0 : num_layers;
1454 pitch = tex->bo_stride;
1455
1456 if (surface_type == BRW_SURFACE_CUBE) {
1457 /*
1458 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
1459 *
1460 * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of
1461 * this field is [0,340], indicating the number of cube array
1462 * elements (equal to the number of underlying 2D array elements
1463 * divided by 6). For other surfaces, this field must be zero."
1464 *
1465 * When is_rt is true, we treat the texture as a 2D one to avoid the
1466 * restriction.
1467 */
1468 if (is_rt) {
1469 surface_type = BRW_SURFACE_2D;
1470 }
1471 else {
1472 assert(num_layers % 6 == 0);
1473 depth = num_layers / 6;
1474 }
1475 }
1476
1477 /* sanity check the size */
1478 assert(width >= 1 && height >= 1 && depth >= 1 && pitch >= 1);
1479 assert(first_layer < 2048 && num_layers <= 2048);
1480 switch (surface_type) {
1481 case BRW_SURFACE_1D:
1482 assert(width <= 16384 && height == 1 && depth <= 2048);
1483 break;
1484 case BRW_SURFACE_2D:
1485 assert(width <= 16384 && height <= 16384 && depth <= 2048);
1486 break;
1487 case BRW_SURFACE_3D:
1488 assert(width <= 2048 && height <= 2048 && depth <= 2048);
1489 if (!is_rt)
1490 assert(first_layer == 0);
1491 break;
1492 case BRW_SURFACE_CUBE:
1493 assert(width <= 16384 && height <= 16384 && depth <= 86);
1494 assert(width == height);
1495 if (is_rt)
1496 assert(first_layer == 0);
1497 break;
1498 default:
1499 assert(!"unexpected surface type");
1500 break;
1501 }
1502
1503 if (is_rt) {
1504 /*
1505 * Compute the offset to the layer manually.
1506 *
1507 * For rendering, the hardware requires LOD to be the same for all
1508 * render targets and the depth buffer. We need to compute the offset
1509 * to the layer manually and always set LOD to 0.
1510 */
1511 if (true) {
1512 /* we lose the capability for layered rendering */
1513 assert(num_layers == 1);
1514
1515 layer_offset = ilo_texture_get_slice_offset(tex,
1516 first_level, first_layer, &x_offset, &y_offset);
1517
1518 assert(x_offset % 4 == 0);
1519 assert(y_offset % 2 == 0);
1520 x_offset /= 4;
1521 y_offset /= 2;
1522
1523 /* derive the size for the LOD */
1524 width = u_minify(width, first_level);
1525 height = u_minify(height, first_level);
1526 if (surface_type == BRW_SURFACE_3D)
1527 depth = u_minify(depth, first_level);
1528 else
1529 depth = 1;
1530
1531 first_level = 0;
1532 first_layer = 0;
1533 lod = 0;
1534 }
1535 else {
1536 layer_offset = 0;
1537 x_offset = 0;
1538 y_offset = 0;
1539 }
1540
1541 assert(num_levels == 1);
1542 lod = first_level;
1543 }
1544 else {
1545 layer_offset = 0;
1546 x_offset = 0;
1547 y_offset = 0;
1548
1549 lod = num_levels - 1;
1550 }
1551
1552 /*
1553 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
1554 *
1555 * "The Base Address for linear render target surfaces and surfaces
1556 * accessed with the typed surface read/write data port messages must
1557 * be element-size aligned, for non-YUV surface formats, or a multiple
1558 * of 2 element-sizes for YUV surface formats. Other linear surfaces
1559 * have no alignment requirements (byte alignment is sufficient)."
1560 *
1561 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
1562 *
1563 * "For linear render target surfaces and surfaces accessed with the
1564 * typed data port messages, the pitch must be a multiple of the
1565 * element size for non-YUV surface formats. Pitch must be a multiple
1566 * of 2 * element size for YUV surface formats. For linear surfaces
1567 * with Surface Type of SURFTYPE_STRBUF, the pitch must be a multiple
1568 * of 4 bytes.For other linear surfaces, the pitch can be any multiple
1569 * of bytes."
1570 *
1571 * From the Ivy Bridge PRM, volume 4 part 1, page 74:
1572 *
1573 * "For linear surfaces, this field (X Offset) must be zero."
1574 */
1575 if (tex->tiling == INTEL_TILING_NONE) {
1576 if (is_rt) {
1577 const int elem_size = util_format_get_blocksize(format);
1578 assert(layer_offset % elem_size == 0);
1579 assert(pitch % elem_size == 0);
1580 }
1581
1582 assert(!x_offset);
1583 }
1584
1585 STATIC_ASSERT(Elements(surf->payload) >= 8);
1586 dw = surf->payload;
1587
1588 dw[0] = surface_type << BRW_SURFACE_TYPE_SHIFT |
1589 surface_format << BRW_SURFACE_FORMAT_SHIFT |
1590 ilo_gpe_gen6_translate_winsys_tiling(tex->tiling) << 13;
1591
1592 if (surface_type != BRW_SURFACE_3D && depth > 1)
1593 dw[0] |= GEN7_SURFACE_IS_ARRAY;
1594
1595 if (tex->valign_4)
1596 dw[0] |= GEN7_SURFACE_VALIGN_4;
1597
1598 if (tex->halign_8)
1599 dw[0] |= GEN7_SURFACE_HALIGN_8;
1600
1601 if (tex->array_spacing_full)
1602 dw[0] |= GEN7_SURFACE_ARYSPC_FULL;
1603 else
1604 dw[0] |= GEN7_SURFACE_ARYSPC_LOD0;
1605
1606 if (render_cache_rw)
1607 dw[0] |= BRW_SURFACE_RC_READ_WRITE;
1608
1609 if (surface_type == BRW_SURFACE_CUBE && !is_rt)
1610 dw[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
1611
1612 dw[1] = layer_offset;
1613
1614 dw[2] = SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT) |
1615 SET_FIELD(width - 1, GEN7_SURFACE_WIDTH);
1616
1617 dw[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
1618 (pitch - 1);
1619
1620 dw[4] = first_layer << 18 |
1621 (num_layers - 1) << 7;
1622
1623 /*
1624 * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
1625 * means the samples are interleaved. The layouts are the same when the
1626 * number of samples is 1.
1627 */
1628 if (tex->interleaved && tex->base.nr_samples > 1) {
1629 assert(!is_rt);
1630 dw[4] |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
1631 }
1632 else {
1633 dw[4] |= GEN7_SURFACE_MSFMT_MSS;
1634 }
1635
1636 if (tex->base.nr_samples > 4)
1637 dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
1638 else if (tex->base.nr_samples > 2)
1639 dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
1640 else
1641 dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
1642
1643 dw[5] = x_offset << BRW_SURFACE_X_OFFSET_SHIFT |
1644 y_offset << BRW_SURFACE_Y_OFFSET_SHIFT |
1645 SET_FIELD(first_level, GEN7_SURFACE_MIN_LOD) |
1646 lod;
1647
1648 dw[6] = 0;
1649 dw[7] = 0;
1650
1651 /* do not increment reference count */
1652 surf->bo = tex->bo;
1653 }
1654
1655 static int
1656 gen7_estimate_command_size(const struct ilo_dev_info *dev,
1657 enum ilo_gpe_gen7_command cmd,
1658 int arg)
1659 {
1660 static const struct {
1661 int header;
1662 int body;
1663 } gen7_command_size_table[ILO_GPE_GEN7_COMMAND_COUNT] = {
1664 [ILO_GPE_GEN7_STATE_BASE_ADDRESS] = { 0, 10 },
1665 [ILO_GPE_GEN7_STATE_SIP] = { 0, 2 },
1666 [ILO_GPE_GEN7_3DSTATE_VF_STATISTICS] = { 0, 1 },
1667 [ILO_GPE_GEN7_PIPELINE_SELECT] = { 0, 1 },
1668 [ILO_GPE_GEN7_MEDIA_VFE_STATE] = { 0, 8 },
1669 [ILO_GPE_GEN7_MEDIA_CURBE_LOAD] = { 0, 4 },
1670 [ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD] = { 0, 4 },
1671 [ILO_GPE_GEN7_MEDIA_STATE_FLUSH] = { 0, 2 },
1672 [ILO_GPE_GEN7_GPGPU_WALKER] = { 0, 11 },
1673 [ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS] = { 0, 3 },
1674 [ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER] = { 0, 7 },
1675 [ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER] = { 0, 3 },
1676 [ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER] = { 0, 3 },
1677 [ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS] = { 1, 4 },
1678 [ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS] = { 1, 2 },
1679 [ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER] = { 0, 3 },
1680 [ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS] = { 0, 2 },
1681 [ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS] = { 0, 2 },
1682 [ILO_GPE_GEN7_3DSTATE_VS] = { 0, 6 },
1683 [ILO_GPE_GEN7_3DSTATE_GS] = { 0, 7 },
1684 [ILO_GPE_GEN7_3DSTATE_CLIP] = { 0, 4 },
1685 [ILO_GPE_GEN7_3DSTATE_SF] = { 0, 7 },
1686 [ILO_GPE_GEN7_3DSTATE_WM] = { 0, 3 },
1687 [ILO_GPE_GEN7_3DSTATE_CONSTANT_VS] = { 0, 7 },
1688 [ILO_GPE_GEN7_3DSTATE_CONSTANT_GS] = { 0, 7 },
1689 [ILO_GPE_GEN7_3DSTATE_CONSTANT_PS] = { 0, 7 },
1690 [ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK] = { 0, 2 },
1691 [ILO_GPE_GEN7_3DSTATE_CONSTANT_HS] = { 0, 7 },
1692 [ILO_GPE_GEN7_3DSTATE_CONSTANT_DS] = { 0, 7 },
1693 [ILO_GPE_GEN7_3DSTATE_HS] = { 0, 7 },
1694 [ILO_GPE_GEN7_3DSTATE_TE] = { 0, 4 },
1695 [ILO_GPE_GEN7_3DSTATE_DS] = { 0, 6 },
1696 [ILO_GPE_GEN7_3DSTATE_STREAMOUT] = { 0, 3 },
1697 [ILO_GPE_GEN7_3DSTATE_SBE] = { 0, 14 },
1698 [ILO_GPE_GEN7_3DSTATE_PS] = { 0, 8 },
1699 [ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP] = { 0, 2 },
1700 [ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC] = { 0, 2 },
1701 [ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS] = { 0, 2 },
1702 [ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS] = { 0, 2 },
1703 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS] = { 0, 2 },
1704 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS] = { 0, 2 },
1705 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS] = { 0, 2 },
1706 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS] = { 0, 2 },
1707 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS] = { 0, 2 },
1708 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS] = { 0, 2 },
1709 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS] = { 0, 2 },
1710 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS] = { 0, 2 },
1711 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS] = { 0, 2 },
1712 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS] = { 0, 2 },
1713 [ILO_GPE_GEN7_3DSTATE_URB_VS] = { 0, 2 },
1714 [ILO_GPE_GEN7_3DSTATE_URB_HS] = { 0, 2 },
1715 [ILO_GPE_GEN7_3DSTATE_URB_DS] = { 0, 2 },
1716 [ILO_GPE_GEN7_3DSTATE_URB_GS] = { 0, 2 },
1717 [ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE] = { 0, 4 },
1718 [ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET] = { 0, 2 },
1719 [ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN] = { 0, 33, },
1720 [ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE] = { 0, 3 },
1721 [ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS] = { 0, 3 },
1722 [ILO_GPE_GEN7_3DSTATE_MULTISAMPLE] = { 0, 4 },
1723 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS] = { 0, 2 },
1724 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS] = { 0, 2 },
1725 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS] = { 0, 2 },
1726 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS] = { 0, 2 },
1727 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS] = { 0, 2 },
1728 [ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST] = { 3, 2 },
1729 [ILO_GPE_GEN7_3DSTATE_SO_BUFFER] = { 0, 4 },
1730 [ILO_GPE_GEN7_PIPE_CONTROL] = { 0, 5 },
1731 [ILO_GPE_GEN7_3DPRIMITIVE] = { 0, 7 },
1732 };
1733 const int header = gen7_command_size_table[cmd].header;
1734 const int body = gen7_command_size_table[cmd].body;
1735 const int count = arg;
1736
1737 ILO_GPE_VALID_GEN(dev, 7, 7);
1738 assert(cmd < ILO_GPE_GEN7_COMMAND_COUNT);
1739
1740 return (likely(count)) ? header + body * count : 0;
1741 }
1742
1743 static int
1744 gen7_estimate_state_size(const struct ilo_dev_info *dev,
1745 enum ilo_gpe_gen7_state state,
1746 int arg)
1747 {
1748 static const struct {
1749 int alignment;
1750 int body;
1751 bool is_array;
1752 } gen7_state_size_table[ILO_GPE_GEN7_STATE_COUNT] = {
1753 [ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA] = { 8, 8, true },
1754 [ILO_GPE_GEN7_SF_CLIP_VIEWPORT] = { 16, 16, true },
1755 [ILO_GPE_GEN7_CC_VIEWPORT] = { 8, 2, true },
1756 [ILO_GPE_GEN7_COLOR_CALC_STATE] = { 16, 6, false },
1757 [ILO_GPE_GEN7_BLEND_STATE] = { 16, 2, true },
1758 [ILO_GPE_GEN7_DEPTH_STENCIL_STATE] = { 16, 3, false },
1759 [ILO_GPE_GEN7_SCISSOR_RECT] = { 8, 2, true },
1760 [ILO_GPE_GEN7_BINDING_TABLE_STATE] = { 8, 1, true },
1761 [ILO_GPE_GEN7_SURFACE_STATE] = { 8, 8, false },
1762 [ILO_GPE_GEN7_SAMPLER_STATE] = { 8, 4, true },
1763 [ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE] = { 8, 4, false },
1764 [ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER] = { 8, 1, true },
1765 };
1766 const int alignment = gen7_state_size_table[state].alignment;
1767 const int body = gen7_state_size_table[state].body;
1768 const bool is_array = gen7_state_size_table[state].is_array;
1769 const int count = arg;
1770 int estimate;
1771
1772 ILO_GPE_VALID_GEN(dev, 7, 7);
1773 assert(state < ILO_GPE_GEN7_STATE_COUNT);
1774
1775 if (likely(count)) {
1776 if (is_array) {
1777 estimate = (alignment - 1) + body * count;
1778 }
1779 else {
1780 estimate = (alignment - 1) + body;
1781 /* all states are aligned */
1782 if (count > 1)
1783 estimate += util_align_npot(body, alignment) * (count - 1);
1784 }
1785 }
1786 else {
1787 estimate = 0;
1788 }
1789
1790 return estimate;
1791 }
1792
1793 static void
1794 gen7_init(struct ilo_gpe_gen7 *gen7)
1795 {
1796 const struct ilo_gpe_gen6 *gen6 = ilo_gpe_gen6_get();
1797
1798 gen7->estimate_command_size = gen7_estimate_command_size;
1799 gen7->estimate_state_size = gen7_estimate_state_size;
1800
1801 #define GEN7_USE(gen7, name, from) gen7->emit_ ## name = from->emit_ ## name
1802 #define GEN7_SET(gen7, name) gen7->emit_ ## name = gen7_emit_ ## name
1803 GEN7_USE(gen7, STATE_BASE_ADDRESS, gen6);
1804 GEN7_USE(gen7, STATE_SIP, gen6);
1805 GEN7_USE(gen7, 3DSTATE_VF_STATISTICS, gen6);
1806 GEN7_USE(gen7, PIPELINE_SELECT, gen6);
1807 GEN7_USE(gen7, MEDIA_VFE_STATE, gen6);
1808 GEN7_USE(gen7, MEDIA_CURBE_LOAD, gen6);
1809 GEN7_USE(gen7, MEDIA_INTERFACE_DESCRIPTOR_LOAD, gen6);
1810 GEN7_USE(gen7, MEDIA_STATE_FLUSH, gen6);
1811 GEN7_SET(gen7, GPGPU_WALKER);
1812 GEN7_SET(gen7, 3DSTATE_CLEAR_PARAMS);
1813 GEN7_USE(gen7, 3DSTATE_DEPTH_BUFFER, gen6);
1814 GEN7_USE(gen7, 3DSTATE_STENCIL_BUFFER, gen6);
1815 GEN7_USE(gen7, 3DSTATE_HIER_DEPTH_BUFFER, gen6);
1816 GEN7_USE(gen7, 3DSTATE_VERTEX_BUFFERS, gen6);
1817 GEN7_USE(gen7, 3DSTATE_VERTEX_ELEMENTS, gen6);
1818 GEN7_USE(gen7, 3DSTATE_INDEX_BUFFER, gen6);
1819 GEN7_SET(gen7, 3DSTATE_CC_STATE_POINTERS);
1820 GEN7_USE(gen7, 3DSTATE_SCISSOR_STATE_POINTERS, gen6);
1821 GEN7_USE(gen7, 3DSTATE_VS, gen6);
1822 GEN7_SET(gen7, 3DSTATE_GS);
1823 GEN7_USE(gen7, 3DSTATE_CLIP, gen6);
1824 GEN7_SET(gen7, 3DSTATE_SF);
1825 GEN7_SET(gen7, 3DSTATE_WM);
1826 GEN7_SET(gen7, 3DSTATE_CONSTANT_VS);
1827 GEN7_SET(gen7, 3DSTATE_CONSTANT_GS);
1828 GEN7_SET(gen7, 3DSTATE_CONSTANT_PS);
1829 GEN7_SET(gen7, 3DSTATE_SAMPLE_MASK);
1830 GEN7_SET(gen7, 3DSTATE_CONSTANT_HS);
1831 GEN7_SET(gen7, 3DSTATE_CONSTANT_DS);
1832 GEN7_SET(gen7, 3DSTATE_HS);
1833 GEN7_SET(gen7, 3DSTATE_TE);
1834 GEN7_SET(gen7, 3DSTATE_DS);
1835 GEN7_SET(gen7, 3DSTATE_STREAMOUT);
1836 GEN7_SET(gen7, 3DSTATE_SBE);
1837 GEN7_SET(gen7, 3DSTATE_PS);
1838 GEN7_SET(gen7, 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);
1839 GEN7_SET(gen7, 3DSTATE_VIEWPORT_STATE_POINTERS_CC);
1840 GEN7_SET(gen7, 3DSTATE_BLEND_STATE_POINTERS);
1841 GEN7_SET(gen7, 3DSTATE_DEPTH_STENCIL_STATE_POINTERS);
1842 GEN7_SET(gen7, 3DSTATE_BINDING_TABLE_POINTERS_VS);
1843 GEN7_SET(gen7, 3DSTATE_BINDING_TABLE_POINTERS_HS);
1844 GEN7_SET(gen7, 3DSTATE_BINDING_TABLE_POINTERS_DS);
1845 GEN7_SET(gen7, 3DSTATE_BINDING_TABLE_POINTERS_GS);
1846 GEN7_SET(gen7, 3DSTATE_BINDING_TABLE_POINTERS_PS);
1847 GEN7_SET(gen7, 3DSTATE_SAMPLER_STATE_POINTERS_VS);
1848 GEN7_SET(gen7, 3DSTATE_SAMPLER_STATE_POINTERS_HS);
1849 GEN7_SET(gen7, 3DSTATE_SAMPLER_STATE_POINTERS_DS);
1850 GEN7_SET(gen7, 3DSTATE_SAMPLER_STATE_POINTERS_GS);
1851 GEN7_SET(gen7, 3DSTATE_SAMPLER_STATE_POINTERS_PS);
1852 GEN7_SET(gen7, 3DSTATE_URB_VS);
1853 GEN7_SET(gen7, 3DSTATE_URB_HS);
1854 GEN7_SET(gen7, 3DSTATE_URB_DS);
1855 GEN7_SET(gen7, 3DSTATE_URB_GS);
1856 GEN7_USE(gen7, 3DSTATE_DRAWING_RECTANGLE, gen6);
1857 GEN7_USE(gen7, 3DSTATE_POLY_STIPPLE_OFFSET, gen6);
1858 GEN7_USE(gen7, 3DSTATE_POLY_STIPPLE_PATTERN, gen6);
1859 GEN7_USE(gen7, 3DSTATE_LINE_STIPPLE, gen6);
1860 GEN7_USE(gen7, 3DSTATE_AA_LINE_PARAMETERS, gen6);
1861 GEN7_USE(gen7, 3DSTATE_MULTISAMPLE, gen6);
1862 GEN7_SET(gen7, 3DSTATE_PUSH_CONSTANT_ALLOC_VS);
1863 GEN7_SET(gen7, 3DSTATE_PUSH_CONSTANT_ALLOC_HS);
1864 GEN7_SET(gen7, 3DSTATE_PUSH_CONSTANT_ALLOC_DS);
1865 GEN7_SET(gen7, 3DSTATE_PUSH_CONSTANT_ALLOC_GS);
1866 GEN7_SET(gen7, 3DSTATE_PUSH_CONSTANT_ALLOC_PS);
1867 GEN7_SET(gen7, 3DSTATE_SO_DECL_LIST);
1868 GEN7_SET(gen7, 3DSTATE_SO_BUFFER);
1869 GEN7_USE(gen7, PIPE_CONTROL, gen6);
1870 GEN7_SET(gen7, 3DPRIMITIVE);
1871 GEN7_USE(gen7, INTERFACE_DESCRIPTOR_DATA, gen6);
1872 GEN7_SET(gen7, SF_CLIP_VIEWPORT);
1873 GEN7_USE(gen7, CC_VIEWPORT, gen6);
1874 GEN7_USE(gen7, COLOR_CALC_STATE, gen6);
1875 GEN7_USE(gen7, BLEND_STATE, gen6);
1876 GEN7_USE(gen7, DEPTH_STENCIL_STATE, gen6);
1877 GEN7_USE(gen7, SCISSOR_RECT, gen6);
1878 GEN7_USE(gen7, BINDING_TABLE_STATE, gen6);
1879 GEN7_USE(gen7, SURFACE_STATE, gen6);
1880 GEN7_USE(gen7, SAMPLER_STATE, gen6);
1881 GEN7_USE(gen7, SAMPLER_BORDER_COLOR_STATE, gen6);
1882 GEN7_USE(gen7, push_constant_buffer, gen6);
1883 #undef GEN7_USE
1884 #undef GEN7_SET
1885 }
1886
1887 static struct ilo_gpe_gen7 gen7_gpe;
1888
1889 const struct ilo_gpe_gen7 *
1890 ilo_gpe_gen7_get(void)
1891 {
1892 if (!gen7_gpe.estimate_command_size)
1893 gen7_init(&gen7_gpe);
1894
1895 return &gen7_gpe;
1896 }