2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_resource.h"
31 #include "ilo_format.h"
32 #include "ilo_resource.h"
33 #include "ilo_shader.h"
34 #include "ilo_gpe_gen7.h"
36 #define SET_FIELD(value, field) (((value) << field ## __SHIFT) & field ## __MASK)
39 ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info
*dev
,
40 const struct ilo_shader_state
*gs
,
41 struct ilo_shader_cso
*cso
)
43 int start_grf
, vue_read_len
, max_threads
;
44 uint32_t dw2
, dw4
, dw5
;
46 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
48 start_grf
= ilo_shader_get_kernel_param(gs
, ILO_KERNEL_URB_DATA_START_REG
);
49 vue_read_len
= ilo_shader_get_kernel_param(gs
, ILO_KERNEL_INPUT_COUNT
);
52 vue_read_len
= (vue_read_len
+ 1) / 2;
56 max_threads
= (dev
->gt
>= 2) ? 256 : 70;
59 max_threads
= (dev
->gt
== 2) ? 128 : 36;
66 dw2
= (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT
;
68 dw4
= vue_read_len
<< GEN7_GS_DW4_URB_READ_LEN__SHIFT
|
69 GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES
|
70 0 << GEN7_GS_DW4_URB_READ_OFFSET__SHIFT
|
71 start_grf
<< GEN7_GS_DW4_URB_GRF_START__SHIFT
;
73 dw5
= (max_threads
- 1) << GEN7_GS_DW5_MAX_THREADS__SHIFT
|
74 GEN7_GS_DW5_STATISTICS
|
75 GEN7_GS_DW5_GS_ENABLE
;
77 STATIC_ASSERT(Elements(cso
->payload
) >= 3);
78 cso
->payload
[0] = dw2
;
79 cso
->payload
[1] = dw4
;
80 cso
->payload
[2] = dw5
;
84 ilo_gpe_init_rasterizer_wm_gen7(const struct ilo_dev_info
*dev
,
85 const struct pipe_rasterizer_state
*state
,
86 struct ilo_rasterizer_wm
*wm
)
90 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
92 dw1
= GEN7_WM_DW1_ZW_INTERP_PIXEL
|
93 GEN7_WM_DW1_AA_LINE_WIDTH_2_0
|
94 GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL
;
96 /* same value as in 3DSTATE_SF */
97 if (state
->line_smooth
)
98 dw1
|= GEN7_WM_DW1_AA_LINE_CAP_1_0
;
100 if (state
->poly_stipple_enable
)
101 dw1
|= GEN7_WM_DW1_POLY_STIPPLE_ENABLE
;
102 if (state
->line_stipple_enable
)
103 dw1
|= GEN7_WM_DW1_LINE_STIPPLE_ENABLE
;
105 if (state
->bottom_edge_rule
)
106 dw1
|= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT
;
108 dw2
= GEN7_WM_DW2_MSDISPMODE_PERSAMPLE
;
111 * assertion that makes sure
113 * dw1 |= wm->dw_msaa_rast;
114 * dw2 |= wm->dw_msaa_disp;
118 STATIC_ASSERT(GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL
== 0 &&
119 GEN7_WM_DW2_MSDISPMODE_PERSAMPLE
== 0);
122 (state
->multisample
) ? GEN7_WM_DW1_MSRASTMODE_ON_PATTERN
: 0;
123 wm
->dw_msaa_disp
= GEN7_WM_DW2_MSDISPMODE_PERPIXEL
;
125 STATIC_ASSERT(Elements(wm
->payload
) >= 2);
126 wm
->payload
[0] = dw1
;
127 wm
->payload
[1] = dw2
;
131 ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info
*dev
,
132 const struct ilo_shader_state
*fs
,
133 struct ilo_shader_cso
*cso
)
135 int start_grf
, max_threads
;
136 uint32_t dw2
, dw4
, dw5
;
137 uint32_t wm_interps
, wm_dw1
;
139 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
141 start_grf
= ilo_shader_get_kernel_param(fs
, ILO_KERNEL_URB_DATA_START_REG
);
143 dw2
= (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT
;
145 dw4
= GEN7_PS_DW4_POSOFFSET_NONE
;
147 /* see brwCreateContext() */
150 max_threads
= (dev
->gt
== 3) ? 408 : (dev
->gt
== 2) ? 204 : 102;
151 dw4
|= (max_threads
- 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT
;
152 dw4
|= 1 << GEN75_PS_DW4_SAMPLE_MASK__SHIFT
;
156 max_threads
= (dev
->gt
== 2) ? 172 : 48;
157 dw4
|= (max_threads
- 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT
;
161 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_PCB_CBUF0_SIZE
))
162 dw4
|= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE
;
164 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_INPUT_COUNT
))
165 dw4
|= GEN7_PS_DW4_ATTR_ENABLE
;
167 assert(!ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_DISPATCH_16_OFFSET
));
168 dw4
|= GEN7_PS_DW4_8_PIXEL_DISPATCH
;
170 dw5
= start_grf
<< GEN7_PS_DW5_URB_GRF_START0__SHIFT
|
171 0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT
|
172 0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT
;
174 /* FS affects 3DSTATE_WM too */
178 * TODO set this bit only when
180 * a) fs writes colors and color is not masked, or
181 * b) fs writes depth, or
184 wm_dw1
|= GEN7_WM_DW1_PS_ENABLE
;
187 * From the Ivy Bridge PRM, volume 2 part 1, page 278:
189 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that
190 * the PS kernel or color calculator has the ability to kill
191 * (discard) pixels or samples, other than due to depth or stencil
192 * testing. This bit is required to be ENABLED in the following
195 * - The API pixel shader program contains "killpix" or "discard"
196 * instructions, or other code in the pixel shader kernel that
197 * can cause the final pixel mask to differ from the pixel mask
198 * received on dispatch.
200 * - A sampler with chroma key enabled with kill pixel mode is used
201 * by the pixel shader.
203 * - Any render target has Alpha Test Enable or AlphaToCoverage
206 * - The pixel shader kernel generates and outputs oMask.
208 * Note: As ClipDistance clipping is fully supported in hardware
209 * and therefore not via PS instructions, there should be no need
210 * to ENABLE this bit due to ClipDistance clipping."
212 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_USE_KILL
))
213 wm_dw1
|= GEN7_WM_DW1_PS_KILL
;
215 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_OUTPUT_Z
))
216 wm_dw1
|= GEN7_WM_DW1_PSCDEPTH_ON
;
218 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_INPUT_Z
))
219 wm_dw1
|= GEN7_WM_DW1_PS_USE_DEPTH
;
221 if (ilo_shader_get_kernel_param(fs
, ILO_KERNEL_FS_INPUT_W
))
222 wm_dw1
|= GEN7_WM_DW1_PS_USE_W
;
224 wm_interps
= ilo_shader_get_kernel_param(fs
,
225 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS
);
227 wm_dw1
|= wm_interps
<< GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT
;
229 STATIC_ASSERT(Elements(cso
->payload
) >= 4);
230 cso
->payload
[0] = dw2
;
231 cso
->payload
[1] = dw4
;
232 cso
->payload
[2] = dw5
;
233 cso
->payload
[3] = wm_dw1
;
237 ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info
*dev
,
238 unsigned width
, unsigned height
,
239 unsigned depth
, unsigned level
,
240 struct ilo_view_surface
*surf
)
244 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
247 * From the Ivy Bridge PRM, volume 4 part 1, page 62:
249 * "A null surface is used in instances where an actual surface is not
250 * bound. When a write message is generated to a null surface, no
251 * actual surface is written to. When a read message (including any
252 * sampling engine message) is generated to a null surface, the result
253 * is all zeros. Note that a null surface type is allowed to be used
254 * with all messages, even if it is not specificially indicated as
255 * supported. All of the remaining fields in surface state are ignored
256 * for null surfaces, with the following exceptions:
258 * * Width, Height, Depth, LOD, and Render Target View Extent fields
259 * must match the depth buffer's corresponding state for all render
260 * target surfaces, including null.
261 * * All sampling engine and data port messages support null surfaces
262 * with the above behavior, even if not mentioned as specifically
263 * supported, except for the following:
264 * * Data Port Media Block Read/Write messages.
265 * * The Surface Type of a surface used as a render target (accessed
266 * via the Data Port's Render Target Write message) must be the same
267 * as the Surface Type of all other render targets and of the depth
268 * buffer (defined in 3DSTATE_DEPTH_BUFFER), unless either the depth
269 * buffer or render targets are SURFTYPE_NULL."
271 * From the Ivy Bridge PRM, volume 4 part 1, page 65:
273 * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must be
277 STATIC_ASSERT(Elements(surf
->payload
) >= 8);
280 dw
[0] = GEN6_SURFTYPE_NULL
<< GEN7_SURFACE_DW0_TYPE__SHIFT
|
281 GEN6_FORMAT_B8G8R8A8_UNORM
<< GEN7_SURFACE_DW0_FORMAT__SHIFT
|
286 dw
[2] = SET_FIELD(height
- 1, GEN7_SURFACE_DW2_HEIGHT
) |
287 SET_FIELD(width
- 1, GEN7_SURFACE_DW2_WIDTH
);
289 dw
[3] = SET_FIELD(depth
- 1, GEN7_SURFACE_DW3_DEPTH
);
301 ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info
*dev
,
302 const struct ilo_buffer
*buf
,
303 unsigned offset
, unsigned size
,
304 unsigned struct_size
,
305 enum pipe_format elem_format
,
306 bool is_rt
, bool render_cache_rw
,
307 struct ilo_view_surface
*surf
)
309 const bool typed
= (elem_format
!= PIPE_FORMAT_NONE
);
310 const bool structured
= (!typed
&& struct_size
> 1);
311 const int elem_size
= (typed
) ?
312 util_format_get_blocksize(elem_format
) : 1;
313 int width
, height
, depth
, pitch
;
314 int surface_type
, surface_format
, num_entries
;
317 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
319 surface_type
= (structured
) ? GEN7_SURFTYPE_STRBUF
: GEN6_SURFTYPE_BUFFER
;
321 surface_format
= (typed
) ?
322 ilo_translate_color_format(elem_format
) : GEN6_FORMAT_RAW
;
324 num_entries
= size
/ struct_size
;
325 /* see if there is enough space to fit another element */
326 if (size
% struct_size
>= elem_size
&& !structured
)
330 * From the Ivy Bridge PRM, volume 4 part 1, page 67:
332 * "For SURFTYPE_BUFFER render targets, this field (Surface Base
333 * Address) specifies the base address of first element of the
334 * surface. The surface is interpreted as a simple array of that
335 * single element type. The address must be naturally-aligned to the
336 * element size (e.g., a buffer containing R32G32B32A32_FLOAT elements
337 * must be 16-byte aligned)
339 * For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
340 * the base address of the first element of the surface, computed in
341 * software by adding the surface base address to the byte offset of
342 * the element in the buffer."
345 assert(offset
% elem_size
== 0);
348 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
350 * "For typed buffer and structured buffer surfaces, the number of
351 * entries in the buffer ranges from 1 to 2^27. For raw buffer
352 * surfaces, the number of entries in the buffer is the number of
353 * bytes which can range from 1 to 2^30."
355 assert(num_entries
>= 1 &&
356 num_entries
<= 1 << ((typed
|| structured
) ? 27 : 30));
359 * From the Ivy Bridge PRM, volume 4 part 1, page 69:
361 * "For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
362 * 11 if the Surface Format is RAW (the size of the buffer must be a
363 * multiple of 4 bytes)."
365 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
367 * "For surfaces of type SURFTYPE_BUFFER and SURFTYPE_STRBUF, this
368 * field (Surface Pitch) indicates the size of the structure."
370 * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the pitch
371 * must be a multiple of 4 bytes."
374 assert(struct_size
% 4 == 0);
376 assert(num_entries
% 4 == 0);
383 width
= (num_entries
& 0x0000007f);
385 height
= (num_entries
& 0x001fff80) >> 7;
387 depth
= (num_entries
& 0x7fe00000) >> 21;
388 /* limit to [26:21] */
389 if (typed
|| structured
)
392 STATIC_ASSERT(Elements(surf
->payload
) >= 8);
395 dw
[0] = surface_type
<< GEN7_SURFACE_DW0_TYPE__SHIFT
|
396 surface_format
<< GEN7_SURFACE_DW0_FORMAT__SHIFT
;
398 dw
[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW
;
402 dw
[2] = SET_FIELD(height
, GEN7_SURFACE_DW2_HEIGHT
) |
403 SET_FIELD(width
, GEN7_SURFACE_DW2_WIDTH
);
405 dw
[3] = SET_FIELD(depth
, GEN7_SURFACE_DW3_DEPTH
) |
414 if (dev
->gen
>= ILO_GEN(7.5)) {
415 dw
[7] |= SET_FIELD(GEN75_SCS_RED
, GEN75_SURFACE_DW7_SCS_R
) |
416 SET_FIELD(GEN75_SCS_GREEN
, GEN75_SURFACE_DW7_SCS_G
) |
417 SET_FIELD(GEN75_SCS_BLUE
, GEN75_SURFACE_DW7_SCS_B
) |
418 SET_FIELD(GEN75_SCS_ALPHA
, GEN75_SURFACE_DW7_SCS_A
);
421 /* do not increment reference count */
426 ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info
*dev
,
427 const struct ilo_texture
*tex
,
428 enum pipe_format format
,
429 unsigned first_level
,
431 unsigned first_layer
,
433 bool is_rt
, bool offset_to_layer
,
434 struct ilo_view_surface
*surf
)
436 int surface_type
, surface_format
;
437 int width
, height
, depth
, pitch
, lod
;
438 unsigned layer_offset
, x_offset
, y_offset
;
441 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
443 surface_type
= ilo_gpe_gen6_translate_texture(tex
->base
.target
);
444 assert(surface_type
!= GEN6_SURFTYPE_BUFFER
);
446 if (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
&& tex
->separate_s8
)
447 format
= PIPE_FORMAT_Z32_FLOAT
;
450 surface_format
= ilo_translate_render_format(format
);
452 surface_format
= ilo_translate_texture_format(format
);
453 assert(surface_format
>= 0);
455 width
= tex
->base
.width0
;
456 height
= tex
->base
.height0
;
457 depth
= (tex
->base
.target
== PIPE_TEXTURE_3D
) ?
458 tex
->base
.depth0
: num_layers
;
459 pitch
= tex
->bo_stride
;
461 if (surface_type
== GEN6_SURFTYPE_CUBE
) {
463 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
465 * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of
466 * this field is [0,340], indicating the number of cube array
467 * elements (equal to the number of underlying 2D array elements
468 * divided by 6). For other surfaces, this field must be zero."
470 * When is_rt is true, we treat the texture as a 2D one to avoid the
474 surface_type
= GEN6_SURFTYPE_2D
;
477 assert(num_layers
% 6 == 0);
478 depth
= num_layers
/ 6;
482 /* sanity check the size */
483 assert(width
>= 1 && height
>= 1 && depth
>= 1 && pitch
>= 1);
484 assert(first_layer
< 2048 && num_layers
<= 2048);
485 switch (surface_type
) {
486 case GEN6_SURFTYPE_1D
:
487 assert(width
<= 16384 && height
== 1 && depth
<= 2048);
489 case GEN6_SURFTYPE_2D
:
490 assert(width
<= 16384 && height
<= 16384 && depth
<= 2048);
492 case GEN6_SURFTYPE_3D
:
493 assert(width
<= 2048 && height
<= 2048 && depth
<= 2048);
495 assert(first_layer
== 0);
497 case GEN6_SURFTYPE_CUBE
:
498 assert(width
<= 16384 && height
<= 16384 && depth
<= 86);
499 assert(width
== height
);
501 assert(first_layer
== 0);
504 assert(!"unexpected surface type");
509 assert(num_levels
== 1);
513 lod
= num_levels
- 1;
517 * Offset to the layer. When rendering, the hardware requires LOD and
518 * Depth to be the same for all render targets and the depth buffer. We
519 * need to offset to the layer manually and always set LOD and Depth to 0.
521 if (offset_to_layer
) {
522 /* we lose the capability for layered rendering */
523 assert(is_rt
&& num_layers
== 1);
525 layer_offset
= ilo_texture_get_slice_offset(tex
,
526 first_level
, first_layer
, &x_offset
, &y_offset
);
528 assert(x_offset
% 4 == 0);
529 assert(y_offset
% 2 == 0);
533 /* derive the size for the LOD */
534 width
= u_minify(width
, first_level
);
535 height
= u_minify(height
, first_level
);
550 * From the Ivy Bridge PRM, volume 4 part 1, page 68:
552 * "The Base Address for linear render target surfaces and surfaces
553 * accessed with the typed surface read/write data port messages must
554 * be element-size aligned, for non-YUV surface formats, or a multiple
555 * of 2 element-sizes for YUV surface formats. Other linear surfaces
556 * have no alignment requirements (byte alignment is sufficient)."
558 * From the Ivy Bridge PRM, volume 4 part 1, page 70:
560 * "For linear render target surfaces and surfaces accessed with the
561 * typed data port messages, the pitch must be a multiple of the
562 * element size for non-YUV surface formats. Pitch must be a multiple
563 * of 2 * element size for YUV surface formats. For linear surfaces
564 * with Surface Type of SURFTYPE_STRBUF, the pitch must be a multiple
565 * of 4 bytes.For other linear surfaces, the pitch can be any multiple
568 * From the Ivy Bridge PRM, volume 4 part 1, page 74:
570 * "For linear surfaces, this field (X Offset) must be zero."
572 if (tex
->tiling
== INTEL_TILING_NONE
) {
574 const int elem_size
= util_format_get_blocksize(format
);
575 assert(layer_offset
% elem_size
== 0);
576 assert(pitch
% elem_size
== 0);
582 STATIC_ASSERT(Elements(surf
->payload
) >= 8);
585 dw
[0] = surface_type
<< GEN7_SURFACE_DW0_TYPE__SHIFT
|
586 surface_format
<< GEN7_SURFACE_DW0_FORMAT__SHIFT
|
587 ilo_gpe_gen6_translate_winsys_tiling(tex
->tiling
) << 13;
590 * From the Ivy Bridge PRM, volume 4 part 1, page 63:
592 * "If this field (Surface Array) is enabled, the Surface Type must be
593 * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
594 * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
595 * SURFTYPE_CUBE, the Depth field must be set to zero."
597 * For non-3D sampler surfaces, resinfo (the sampler message) always
598 * returns zero for the number of layers when this field is not set.
600 if (surface_type
!= GEN6_SURFTYPE_3D
) {
601 if (util_resource_is_array_texture(&tex
->base
))
602 dw
[0] |= GEN7_SURFACE_DW0_IS_ARRAY
;
608 dw
[0] |= GEN7_SURFACE_DW0_VALIGN_4
;
611 dw
[0] |= GEN7_SURFACE_DW0_HALIGN_8
;
613 if (tex
->array_spacing_full
)
614 dw
[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL
;
616 dw
[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0
;
619 dw
[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW
;
621 if (surface_type
== GEN6_SURFTYPE_CUBE
&& !is_rt
)
622 dw
[0] |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK
;
624 dw
[1] = layer_offset
;
626 dw
[2] = SET_FIELD(height
- 1, GEN7_SURFACE_DW2_HEIGHT
) |
627 SET_FIELD(width
- 1, GEN7_SURFACE_DW2_WIDTH
);
629 dw
[3] = SET_FIELD(depth
- 1, GEN7_SURFACE_DW3_DEPTH
) |
632 dw
[4] = first_layer
<< 18 |
633 (num_layers
- 1) << 7;
636 * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
637 * means the samples are interleaved. The layouts are the same when the
638 * number of samples is 1.
640 if (tex
->interleaved
&& tex
->base
.nr_samples
> 1) {
642 dw
[4] |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL
;
645 dw
[4] |= GEN7_SURFACE_DW4_MSFMT_MSS
;
648 if (tex
->base
.nr_samples
> 4)
649 dw
[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8
;
650 else if (tex
->base
.nr_samples
> 2)
651 dw
[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4
;
653 dw
[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1
;
655 dw
[5] = x_offset
<< GEN7_SURFACE_DW5_X_OFFSET__SHIFT
|
656 y_offset
<< GEN7_SURFACE_DW5_Y_OFFSET__SHIFT
|
657 SET_FIELD(first_level
, GEN7_SURFACE_DW5_MIN_LOD
) |
663 if (dev
->gen
>= ILO_GEN(7.5)) {
664 dw
[7] |= SET_FIELD(GEN75_SCS_RED
, GEN75_SURFACE_DW7_SCS_R
) |
665 SET_FIELD(GEN75_SCS_GREEN
, GEN75_SURFACE_DW7_SCS_G
) |
666 SET_FIELD(GEN75_SCS_BLUE
, GEN75_SURFACE_DW7_SCS_B
) |
667 SET_FIELD(GEN75_SCS_ALPHA
, GEN75_SURFACE_DW7_SCS_A
);
670 /* do not increment reference count */
675 ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info
*dev
,
676 enum ilo_gpe_gen7_command cmd
,
679 static const struct {
682 } gen7_command_size_table
[ILO_GPE_GEN7_COMMAND_COUNT
] = {
683 [ILO_GPE_GEN7_MI_STORE_DATA_IMM
] = { 0, 5 },
684 [ILO_GPE_GEN7_MI_LOAD_REGISTER_IMM
] = { 0, 3 },
685 [ILO_GPE_GEN7_MI_STORE_REGISTER_MEM
] = { 0, 3 },
686 [ILO_GPE_GEN7_MI_REPORT_PERF_COUNT
] = { 0, 3 },
687 [ILO_GPE_GEN7_STATE_BASE_ADDRESS
] = { 0, 10 },
688 [ILO_GPE_GEN7_STATE_SIP
] = { 0, 2 },
689 [ILO_GPE_GEN7_3DSTATE_VF_STATISTICS
] = { 0, 1 },
690 [ILO_GPE_GEN7_PIPELINE_SELECT
] = { 0, 1 },
691 [ILO_GPE_GEN7_MEDIA_VFE_STATE
] = { 0, 8 },
692 [ILO_GPE_GEN7_MEDIA_CURBE_LOAD
] = { 0, 4 },
693 [ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD
] = { 0, 4 },
694 [ILO_GPE_GEN7_MEDIA_STATE_FLUSH
] = { 0, 2 },
695 [ILO_GPE_GEN7_GPGPU_WALKER
] = { 0, 11 },
696 [ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS
] = { 0, 3 },
697 [ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER
] = { 0, 7 },
698 [ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER
] = { 0, 3 },
699 [ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER
] = { 0, 3 },
700 [ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS
] = { 1, 4 },
701 [ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS
] = { 1, 2 },
702 [ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER
] = { 0, 3 },
703 [ILO_GPE_GEN7_3DSTATE_VF
] = { 0, 2 },
704 [ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS
] = { 0, 2 },
705 [ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS
] = { 0, 2 },
706 [ILO_GPE_GEN7_3DSTATE_VS
] = { 0, 6 },
707 [ILO_GPE_GEN7_3DSTATE_GS
] = { 0, 7 },
708 [ILO_GPE_GEN7_3DSTATE_CLIP
] = { 0, 4 },
709 [ILO_GPE_GEN7_3DSTATE_SF
] = { 0, 7 },
710 [ILO_GPE_GEN7_3DSTATE_WM
] = { 0, 3 },
711 [ILO_GPE_GEN7_3DSTATE_CONSTANT_VS
] = { 0, 7 },
712 [ILO_GPE_GEN7_3DSTATE_CONSTANT_GS
] = { 0, 7 },
713 [ILO_GPE_GEN7_3DSTATE_CONSTANT_PS
] = { 0, 7 },
714 [ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK
] = { 0, 2 },
715 [ILO_GPE_GEN7_3DSTATE_CONSTANT_HS
] = { 0, 7 },
716 [ILO_GPE_GEN7_3DSTATE_CONSTANT_DS
] = { 0, 7 },
717 [ILO_GPE_GEN7_3DSTATE_HS
] = { 0, 7 },
718 [ILO_GPE_GEN7_3DSTATE_TE
] = { 0, 4 },
719 [ILO_GPE_GEN7_3DSTATE_DS
] = { 0, 6 },
720 [ILO_GPE_GEN7_3DSTATE_STREAMOUT
] = { 0, 3 },
721 [ILO_GPE_GEN7_3DSTATE_SBE
] = { 0, 14 },
722 [ILO_GPE_GEN7_3DSTATE_PS
] = { 0, 8 },
723 [ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
] = { 0, 2 },
724 [ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC
] = { 0, 2 },
725 [ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS
] = { 0, 2 },
726 [ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
] = { 0, 2 },
727 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS
] = { 0, 2 },
728 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS
] = { 0, 2 },
729 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS
] = { 0, 2 },
730 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS
] = { 0, 2 },
731 [ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS
] = { 0, 2 },
732 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS
] = { 0, 2 },
733 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS
] = { 0, 2 },
734 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS
] = { 0, 2 },
735 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS
] = { 0, 2 },
736 [ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS
] = { 0, 2 },
737 [ILO_GPE_GEN7_3DSTATE_URB_VS
] = { 0, 2 },
738 [ILO_GPE_GEN7_3DSTATE_URB_HS
] = { 0, 2 },
739 [ILO_GPE_GEN7_3DSTATE_URB_DS
] = { 0, 2 },
740 [ILO_GPE_GEN7_3DSTATE_URB_GS
] = { 0, 2 },
741 [ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE
] = { 0, 4 },
742 [ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET
] = { 0, 2 },
743 [ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN
] = { 0, 33, },
744 [ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE
] = { 0, 3 },
745 [ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS
] = { 0, 3 },
746 [ILO_GPE_GEN7_3DSTATE_MULTISAMPLE
] = { 0, 4 },
747 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS
] = { 0, 2 },
748 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS
] = { 0, 2 },
749 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS
] = { 0, 2 },
750 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS
] = { 0, 2 },
751 [ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS
] = { 0, 2 },
752 [ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST
] = { 3, 2 },
753 [ILO_GPE_GEN7_3DSTATE_SO_BUFFER
] = { 0, 4 },
754 [ILO_GPE_GEN7_PIPE_CONTROL
] = { 0, 5 },
755 [ILO_GPE_GEN7_3DPRIMITIVE
] = { 0, 7 },
757 const int header
= gen7_command_size_table
[cmd
].header
;
758 const int body
= gen7_command_size_table
[cmd
].body
;
759 const int count
= arg
;
761 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
762 assert(cmd
< ILO_GPE_GEN7_COMMAND_COUNT
);
764 return (likely(count
)) ? header
+ body
* count
: 0;
768 ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info
*dev
,
769 enum ilo_gpe_gen7_state state
,
772 static const struct {
776 } gen7_state_size_table
[ILO_GPE_GEN7_STATE_COUNT
] = {
777 [ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA
] = { 8, 8, true },
778 [ILO_GPE_GEN7_SF_CLIP_VIEWPORT
] = { 16, 16, true },
779 [ILO_GPE_GEN7_CC_VIEWPORT
] = { 8, 2, true },
780 [ILO_GPE_GEN7_COLOR_CALC_STATE
] = { 16, 6, false },
781 [ILO_GPE_GEN7_BLEND_STATE
] = { 16, 2, true },
782 [ILO_GPE_GEN7_DEPTH_STENCIL_STATE
] = { 16, 3, false },
783 [ILO_GPE_GEN7_SCISSOR_RECT
] = { 8, 2, true },
784 [ILO_GPE_GEN7_BINDING_TABLE_STATE
] = { 8, 1, true },
785 [ILO_GPE_GEN7_SURFACE_STATE
] = { 8, 8, false },
786 [ILO_GPE_GEN7_SAMPLER_STATE
] = { 8, 4, true },
787 [ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE
] = { 8, 4, false },
788 [ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER
] = { 8, 1, true },
790 const int alignment
= gen7_state_size_table
[state
].alignment
;
791 const int body
= gen7_state_size_table
[state
].body
;
792 const bool is_array
= gen7_state_size_table
[state
].is_array
;
793 const int count
= arg
;
796 ILO_GPE_VALID_GEN(dev
, 7, 7.5);
797 assert(state
< ILO_GPE_GEN7_STATE_COUNT
);
801 estimate
= (alignment
- 1) + body
* count
;
804 estimate
= (alignment
- 1) + body
;
805 /* all states are aligned */
807 estimate
+= util_align_npot(body
, alignment
) * (count
- 1);