projects / mesa.git / blob
? search:


02feec096c2ad5b7d311d06ae357a1742c3f5734
[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "intel_winsys.h"
32
33 #include "ilo_common.h"
34 #include "ilo_cp.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_gpe_gen6.h"
38
39 /**
40 * Commands that GEN7 GPE could emit.
41 */
42 enum ilo_gpe_gen7_command {
43 ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
44 ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
45 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
46 ILO_GPE_GEN7_PIPELINE_SELECT, /* (0x1, 0x1, 0x04) */
47 ILO_GPE_GEN7_MEDIA_VFE_STATE, /* (0x2, 0x0, 0x00) */
48 ILO_GPE_GEN7_MEDIA_CURBE_LOAD, /* (0x2, 0x0, 0x01) */
49 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD, /* (0x2, 0x0, 0x02) */
50 ILO_GPE_GEN7_MEDIA_STATE_FLUSH, /* (0x2, 0x0, 0x04) */
51 ILO_GPE_GEN7_GPGPU_WALKER, /* (0x2, 0x1, 0x05) */
52 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS, /* (0x3, 0x0, 0x04) */
53 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER, /* (0x3, 0x0, 0x05) */
54 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER, /* (0x3, 0x0, 0x06) */
55 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER, /* (0x3, 0x0, 0x07) */
56 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS, /* (0x3, 0x0, 0x08) */
57 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS, /* (0x3, 0x0, 0x09) */
58 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER, /* (0x3, 0x0, 0x0a) */
59 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS, /* (0x3, 0x0, 0x0e) */
60 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS, /* (0x3, 0x0, 0x0f) */
61 ILO_GPE_GEN7_3DSTATE_VS, /* (0x3, 0x0, 0x10) */
62 ILO_GPE_GEN7_3DSTATE_GS, /* (0x3, 0x0, 0x11) */
63 ILO_GPE_GEN7_3DSTATE_CLIP, /* (0x3, 0x0, 0x12) */
64 ILO_GPE_GEN7_3DSTATE_SF, /* (0x3, 0x0, 0x13) */
65 ILO_GPE_GEN7_3DSTATE_WM, /* (0x3, 0x0, 0x14) */
66 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS, /* (0x3, 0x0, 0x15) */
67 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS, /* (0x3, 0x0, 0x16) */
68 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS, /* (0x3, 0x0, 0x17) */
69 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK, /* (0x3, 0x0, 0x18) */
70 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS, /* (0x3, 0x0, 0x19) */
71 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS, /* (0x3, 0x0, 0x1a) */
72 ILO_GPE_GEN7_3DSTATE_HS, /* (0x3, 0x0, 0x1b) */
73 ILO_GPE_GEN7_3DSTATE_TE, /* (0x3, 0x0, 0x1c) */
74 ILO_GPE_GEN7_3DSTATE_DS, /* (0x3, 0x0, 0x1d) */
75 ILO_GPE_GEN7_3DSTATE_STREAMOUT, /* (0x3, 0x0, 0x1e) */
76 ILO_GPE_GEN7_3DSTATE_SBE, /* (0x3, 0x0, 0x1f) */
77 ILO_GPE_GEN7_3DSTATE_PS, /* (0x3, 0x0, 0x20) */
78 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, /* (0x3, 0x0, 0x21) */
79 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC, /* (0x3, 0x0, 0x23) */
80 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS, /* (0x3, 0x0, 0x24) */
81 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, /* (0x3, 0x0, 0x25) */
82 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, /* (0x3, 0x0, 0x26) */
83 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, /* (0x3, 0x0, 0x27) */
84 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, /* (0x3, 0x0, 0x28) */
85 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, /* (0x3, 0x0, 0x29) */
86 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, /* (0x3, 0x0, 0x2a) */
87 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, /* (0x3, 0x0, 0x2b) */
88 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, /* (0x3, 0x0, 0x2c) */
89 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, /* (0x3, 0x0, 0x2d) */
90 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, /* (0x3, 0x0, 0x2e) */
91 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, /* (0x3, 0x0, 0x2f) */
92 ILO_GPE_GEN7_3DSTATE_URB_VS, /* (0x3, 0x0, 0x30) */
93 ILO_GPE_GEN7_3DSTATE_URB_HS, /* (0x3, 0x0, 0x31) */
94 ILO_GPE_GEN7_3DSTATE_URB_DS, /* (0x3, 0x0, 0x32) */
95 ILO_GPE_GEN7_3DSTATE_URB_GS, /* (0x3, 0x0, 0x33) */
96 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE, /* (0x3, 0x1, 0x00) */
97 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET, /* (0x3, 0x1, 0x06) */
98 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN, /* (0x3, 0x1, 0x07) */
99 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE, /* (0x3, 0x1, 0x08) */
100 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS, /* (0x3, 0x1, 0x0a) */
101 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE, /* (0x3, 0x1, 0x0d) */
102 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, /* (0x3, 0x1, 0x12) */
103 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, /* (0x3, 0x1, 0x13) */
104 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, /* (0x3, 0x1, 0x14) */
105 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, /* (0x3, 0x1, 0x15) */
106 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, /* (0x3, 0x1, 0x16) */
107 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST, /* (0x3, 0x1, 0x17) */
108 ILO_GPE_GEN7_3DSTATE_SO_BUFFER, /* (0x3, 0x1, 0x18) */
109 ILO_GPE_GEN7_PIPE_CONTROL, /* (0x3, 0x2, 0x00) */
110 ILO_GPE_GEN7_3DPRIMITIVE, /* (0x3, 0x3, 0x00) */
111
112 ILO_GPE_GEN7_COMMAND_COUNT,
113 };
114
115 /**
116 * Indirect states that GEN7 GPE could emit.
117 */
118 enum ilo_gpe_gen7_state {
119 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA,
120 ILO_GPE_GEN7_SF_CLIP_VIEWPORT,
121 ILO_GPE_GEN7_CC_VIEWPORT,
122 ILO_GPE_GEN7_COLOR_CALC_STATE,
123 ILO_GPE_GEN7_BLEND_STATE,
124 ILO_GPE_GEN7_DEPTH_STENCIL_STATE,
125 ILO_GPE_GEN7_SCISSOR_RECT,
126 ILO_GPE_GEN7_BINDING_TABLE_STATE,
127 ILO_GPE_GEN7_SURFACE_STATE,
128 ILO_GPE_GEN7_SAMPLER_STATE,
129 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE,
130 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER,
131
132 ILO_GPE_GEN7_STATE_COUNT,
133 };
134
135 int
136 ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
137 enum ilo_gpe_gen7_command cmd,
138 int arg);
139
140 int
141 ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev,
142 enum ilo_gpe_gen7_state state,
143 int arg);
144
145 static inline void
146 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
147 struct ilo_cp *cp)
148 {
149 assert(!"GPGPU_WALKER unsupported");
150 }
151
152 static inline void
153 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
154 uint32_t clear_val,
155 struct ilo_cp *cp)
156 {
157 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
158 const uint8_t cmd_len = 3;
159
160 ILO_GPE_VALID_GEN(dev, 7, 7);
161
162 ilo_cp_begin(cp, cmd_len);
163 ilo_cp_write(cp, cmd | (cmd_len - 2));
164 ilo_cp_write(cp, clear_val);
165 ilo_cp_write(cp, 1);
166 ilo_cp_end(cp);
167 }
168
169 static inline void
170 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
171 int subop, uint32_t pointer,
172 struct ilo_cp *cp)
173 {
174 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
175 const uint8_t cmd_len = 2;
176
177 ILO_GPE_VALID_GEN(dev, 7, 7);
178
179 ilo_cp_begin(cp, cmd_len);
180 ilo_cp_write(cp, cmd | (cmd_len - 2));
181 ilo_cp_write(cp, pointer);
182 ilo_cp_end(cp);
183 }
184
185 static inline void
186 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
187 uint32_t color_calc_state,
188 struct ilo_cp *cp)
189 {
190 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
191 }
192
193 static inline void
194 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
195 const struct ilo_shader_state *gs,
196 int num_samplers,
197 struct ilo_cp *cp)
198 {
199 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
200 const uint8_t cmd_len = 7;
201 const struct ilo_shader_cso *cso;
202 uint32_t dw2, dw4, dw5;
203
204 ILO_GPE_VALID_GEN(dev, 7, 7);
205
206 if (!gs) {
207 ilo_cp_begin(cp, cmd_len);
208 ilo_cp_write(cp, cmd | (cmd_len - 2));
209 ilo_cp_write(cp, 0);
210 ilo_cp_write(cp, 0);
211 ilo_cp_write(cp, 0);
212 ilo_cp_write(cp, 0);
213 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
214 ilo_cp_write(cp, 0);
215 ilo_cp_end(cp);
216 return;
217 }
218
219 cso = ilo_shader_get_kernel_cso(gs);
220 dw2 = cso->payload[0];
221 dw4 = cso->payload[1];
222 dw5 = cso->payload[2];
223
224 dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
225
226 ilo_cp_begin(cp, cmd_len);
227 ilo_cp_write(cp, cmd | (cmd_len - 2));
228 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
229 ilo_cp_write(cp, dw2);
230 ilo_cp_write(cp, 0); /* scratch */
231 ilo_cp_write(cp, dw4);
232 ilo_cp_write(cp, dw5);
233 ilo_cp_write(cp, 0);
234 ilo_cp_end(cp);
235 }
236
237 static inline void
238 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
239 const struct ilo_rasterizer_state *rasterizer,
240 const struct pipe_surface *zs_surf,
241 struct ilo_cp *cp)
242 {
243 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
244 const uint8_t cmd_len = 7;
245 const int num_samples = 1;
246 uint32_t payload[6];
247
248 ILO_GPE_VALID_GEN(dev, 7, 7);
249
250 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
251 rasterizer, num_samples,
252 (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE,
253 payload, Elements(payload));
254
255 ilo_cp_begin(cp, cmd_len);
256 ilo_cp_write(cp, cmd | (cmd_len - 2));
257 ilo_cp_write_multi(cp, payload, 6);
258 ilo_cp_end(cp);
259 }
260
261 static inline void
262 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
263 const struct ilo_shader_state *fs,
264 const struct ilo_rasterizer_state *rasterizer,
265 bool cc_may_kill,
266 struct ilo_cp *cp)
267 {
268 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
269 const uint8_t cmd_len = 3;
270 const int num_samples = 1;
271 uint32_t dw1, dw2;
272
273 ILO_GPE_VALID_GEN(dev, 7, 7);
274
275 /* see ilo_gpe_init_rasterizer_wm() */
276 dw1 = rasterizer->wm.payload[0];
277 dw2 = rasterizer->wm.payload[1];
278
279 dw1 |= GEN7_WM_STATISTICS_ENABLE;
280
281 if (false) {
282 dw1 |= GEN7_WM_DEPTH_CLEAR;
283 dw1 |= GEN7_WM_DEPTH_RESOLVE;
284 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
285 }
286
287 if (fs) {
288 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
289
290 dw1 |= fs_cso->payload[3];
291 }
292
293 if (cc_may_kill) {
294 dw1 |= GEN7_WM_DISPATCH_ENABLE |
295 GEN7_WM_KILL_ENABLE;
296 }
297
298 if (num_samples > 1) {
299 dw1 |= rasterizer->wm.dw_msaa_rast;
300 dw2 |= rasterizer->wm.dw_msaa_disp;
301 }
302
303 ilo_cp_begin(cp, cmd_len);
304 ilo_cp_write(cp, cmd | (cmd_len - 2));
305 ilo_cp_write(cp, dw1);
306 ilo_cp_write(cp, dw2);
307 ilo_cp_end(cp);
308 }
309
310 static inline void
311 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
312 int subop,
313 const uint32_t *bufs, const int *sizes,
314 int num_bufs,
315 struct ilo_cp *cp)
316 {
317 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
318 const uint8_t cmd_len = 7;
319 uint32_t dw[6];
320 int total_read_length, i;
321
322 ILO_GPE_VALID_GEN(dev, 7, 7);
323
324 /* VS, HS, DS, GS, and PS variants */
325 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
326
327 assert(num_bufs <= 4);
328
329 dw[0] = 0;
330 dw[1] = 0;
331
332 total_read_length = 0;
333 for (i = 0; i < 4; i++) {
334 int read_len;
335
336 /*
337 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
338 *
339 * "Constant buffers must be enabled in order from Constant Buffer 0
340 * to Constant Buffer 3 within this command. For example, it is
341 * not allowed to enable Constant Buffer 1 by programming a
342 * non-zero value in the VS Constant Buffer 1 Read Length without a
343 * non-zero value in VS Constant Buffer 0 Read Length."
344 */
345 if (i >= num_bufs || !sizes[i]) {
346 for (; i < 4; i++) {
347 assert(i >= num_bufs || !sizes[i]);
348 dw[2 + i] = 0;
349 }
350 break;
351 }
352
353 /* read lengths are in 256-bit units */
354 read_len = (sizes[i] + 31) / 32;
355 /* the lower 5 bits are used for memory object control state */
356 assert(bufs[i] % 32 == 0);
357
358 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
359 dw[2 + i] = bufs[i];
360
361 total_read_length += read_len;
362 }
363
364 /*
365 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
366 *
367 * "The sum of all four read length fields must be less than or equal
368 * to the size of 64"
369 */
370 assert(total_read_length <= 64);
371
372 ilo_cp_begin(cp, cmd_len);
373 ilo_cp_write(cp, cmd | (cmd_len - 2));
374 ilo_cp_write_multi(cp, dw, 6);
375 ilo_cp_end(cp);
376 }
377
378 static inline void
379 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
380 const uint32_t *bufs, const int *sizes,
381 int num_bufs,
382 struct ilo_cp *cp)
383 {
384 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
385 }
386
387 static inline void
388 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
389 const uint32_t *bufs, const int *sizes,
390 int num_bufs,
391 struct ilo_cp *cp)
392 {
393 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
394 }
395
396 static inline void
397 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
398 const uint32_t *bufs, const int *sizes,
399 int num_bufs,
400 struct ilo_cp *cp)
401 {
402 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
403 }
404
405 static inline void
406 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
407 unsigned sample_mask,
408 int num_samples,
409 struct ilo_cp *cp)
410 {
411 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
412 const uint8_t cmd_len = 2;
413 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
414
415 ILO_GPE_VALID_GEN(dev, 7, 7);
416
417 /*
418 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
419 *
420 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
421 * (Sample Mask) must be zero.
422 *
423 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
424 * must be zero."
425 */
426 sample_mask &= valid_mask;
427
428 ilo_cp_begin(cp, cmd_len);
429 ilo_cp_write(cp, cmd | (cmd_len - 2));
430 ilo_cp_write(cp, sample_mask);
431 ilo_cp_end(cp);
432 }
433
434 static inline void
435 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
436 const uint32_t *bufs, const int *sizes,
437 int num_bufs,
438 struct ilo_cp *cp)
439 {
440 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
441 }
442
443 static inline void
444 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
445 const uint32_t *bufs, const int *sizes,
446 int num_bufs,
447 struct ilo_cp *cp)
448 {
449 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
450 }
451
452 static inline void
453 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
454 const struct ilo_shader_state *hs,
455 int num_samplers,
456 struct ilo_cp *cp)
457 {
458 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
459 const uint8_t cmd_len = 7;
460
461 ILO_GPE_VALID_GEN(dev, 7, 7);
462
463 assert(!hs);
464
465 ilo_cp_begin(cp, cmd_len);
466 ilo_cp_write(cp, cmd | (cmd_len - 2));
467 ilo_cp_write(cp, 0);
468 ilo_cp_write(cp, 0);
469 ilo_cp_write(cp, 0);
470 ilo_cp_write(cp, 0);
471 ilo_cp_write(cp, 0);
472 ilo_cp_write(cp, 0);
473 ilo_cp_end(cp);
474 }
475
476 static inline void
477 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
478 struct ilo_cp *cp)
479 {
480 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
481 const uint8_t cmd_len = 4;
482
483 ILO_GPE_VALID_GEN(dev, 7, 7);
484
485 ilo_cp_begin(cp, cmd_len);
486 ilo_cp_write(cp, cmd | (cmd_len - 2));
487 ilo_cp_write(cp, 0);
488 ilo_cp_write(cp, 0);
489 ilo_cp_write(cp, 0);
490 ilo_cp_end(cp);
491 }
492
493 static inline void
494 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
495 const struct ilo_shader_state *ds,
496 int num_samplers,
497 struct ilo_cp *cp)
498 {
499 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
500 const uint8_t cmd_len = 6;
501
502 ILO_GPE_VALID_GEN(dev, 7, 7);
503
504 assert(!ds);
505
506 ilo_cp_begin(cp, cmd_len);
507 ilo_cp_write(cp, cmd | (cmd_len - 2));
508 ilo_cp_write(cp, 0);
509 ilo_cp_write(cp, 0);
510 ilo_cp_write(cp, 0);
511 ilo_cp_write(cp, 0);
512 ilo_cp_write(cp, 0);
513 ilo_cp_end(cp);
514
515 }
516
517 static inline void
518 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
519 unsigned buffer_mask,
520 int vertex_attrib_count,
521 bool rasterizer_discard,
522 struct ilo_cp *cp)
523 {
524 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
525 const uint8_t cmd_len = 3;
526 const bool enable = (buffer_mask != 0);
527 uint32_t dw1, dw2;
528 int read_len;
529
530 ILO_GPE_VALID_GEN(dev, 7, 7);
531
532 if (!enable) {
533 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
534 if (rasterizer_discard)
535 dw1 |= SO_RENDERING_DISABLE;
536
537 dw2 = 0;
538
539 ilo_cp_begin(cp, cmd_len);
540 ilo_cp_write(cp, cmd | (cmd_len - 2));
541 ilo_cp_write(cp, dw1);
542 ilo_cp_write(cp, dw2);
543 ilo_cp_end(cp);
544 return;
545 }
546
547 read_len = (vertex_attrib_count + 1) / 2;
548 if (!read_len)
549 read_len = 1;
550
551 dw1 = SO_FUNCTION_ENABLE |
552 0 << SO_RENDER_STREAM_SELECT_SHIFT |
553 SO_STATISTICS_ENABLE |
554 buffer_mask << 8;
555
556 if (rasterizer_discard)
557 dw1 |= SO_RENDERING_DISABLE;
558
559 /* API_OPENGL */
560 if (true)
561 dw1 |= SO_REORDER_TRAILING;
562
563 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
564 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
565 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
566 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
567 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
568 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
569 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
570 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
571
572 ilo_cp_begin(cp, cmd_len);
573 ilo_cp_write(cp, cmd | (cmd_len - 2));
574 ilo_cp_write(cp, dw1);
575 ilo_cp_write(cp, dw2);
576 ilo_cp_end(cp);
577 }
578
579 static inline void
580 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
581 const struct ilo_rasterizer_state *rasterizer,
582 const struct ilo_shader_state *fs,
583 const struct ilo_shader_state *last_sh,
584 struct ilo_cp *cp)
585 {
586 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
587 const uint8_t cmd_len = 14;
588 uint32_t dw[13];
589
590 ILO_GPE_VALID_GEN(dev, 7, 7);
591
592 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer,
593 fs, last_sh, dw, Elements(dw));
594
595 ilo_cp_begin(cp, cmd_len);
596 ilo_cp_write(cp, cmd | (cmd_len - 2));
597 ilo_cp_write_multi(cp, dw, 13);
598 ilo_cp_end(cp);
599 }
600
601 static inline void
602 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
603 const struct ilo_shader_state *fs,
604 int num_samplers, bool dual_blend,
605 struct ilo_cp *cp)
606 {
607 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
608 const uint8_t cmd_len = 8;
609 const struct ilo_shader_cso *cso;
610 uint32_t dw2, dw4, dw5;
611
612 ILO_GPE_VALID_GEN(dev, 7, 7);
613
614 if (!fs) {
615 /* see brwCreateContext() */
616 const int max_threads = (dev->gt == 2) ? 172 : 48;
617
618 ilo_cp_begin(cp, cmd_len);
619 ilo_cp_write(cp, cmd | (cmd_len - 2));
620 ilo_cp_write(cp, 0);
621 ilo_cp_write(cp, 0);
622 ilo_cp_write(cp, 0);
623 /* GPU hangs if none of the dispatch enable bits is set */
624 ilo_cp_write(cp, (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT |
625 GEN7_PS_8_DISPATCH_ENABLE);
626 ilo_cp_write(cp, 0);
627 ilo_cp_write(cp, 0);
628 ilo_cp_write(cp, 0);
629 ilo_cp_end(cp);
630
631 return;
632 }
633
634 cso = ilo_shader_get_kernel_cso(fs);
635 dw2 = cso->payload[0];
636 dw4 = cso->payload[1];
637 dw5 = cso->payload[2];
638
639 dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT;
640
641 if (dual_blend)
642 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
643
644 ilo_cp_begin(cp, cmd_len);
645 ilo_cp_write(cp, cmd | (cmd_len - 2));
646 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
647 ilo_cp_write(cp, dw2);
648 ilo_cp_write(cp, 0); /* scratch */
649 ilo_cp_write(cp, dw4);
650 ilo_cp_write(cp, dw5);
651 ilo_cp_write(cp, 0); /* kernel 1 */
652 ilo_cp_write(cp, 0); /* kernel 2 */
653 ilo_cp_end(cp);
654 }
655
656 static inline void
657 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
658 uint32_t sf_clip_viewport,
659 struct ilo_cp *cp)
660 {
661 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
662 }
663
664 static inline void
665 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
666 uint32_t cc_viewport,
667 struct ilo_cp *cp)
668 {
669 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
670 }
671
672 static inline void
673 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
674 uint32_t blend_state,
675 struct ilo_cp *cp)
676 {
677 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
678 }
679
680 static inline void
681 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
682 uint32_t depth_stencil_state,
683 struct ilo_cp *cp)
684 {
685 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
686 }
687
688 static inline void
689 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
690 uint32_t binding_table,
691 struct ilo_cp *cp)
692 {
693 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
694 }
695
696 static inline void
697 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
698 uint32_t binding_table,
699 struct ilo_cp *cp)
700 {
701 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
702 }
703
704 static inline void
705 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
706 uint32_t binding_table,
707 struct ilo_cp *cp)
708 {
709 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
710 }
711
712 static inline void
713 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
714 uint32_t binding_table,
715 struct ilo_cp *cp)
716 {
717 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
718 }
719
720 static inline void
721 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
722 uint32_t binding_table,
723 struct ilo_cp *cp)
724 {
725 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
726 }
727
728 static inline void
729 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
730 uint32_t sampler_state,
731 struct ilo_cp *cp)
732 {
733 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
734 }
735
736 static inline void
737 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
738 uint32_t sampler_state,
739 struct ilo_cp *cp)
740 {
741 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
742 }
743
744 static inline void
745 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
746 uint32_t sampler_state,
747 struct ilo_cp *cp)
748 {
749 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
750 }
751
752 static inline void
753 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
754 uint32_t sampler_state,
755 struct ilo_cp *cp)
756 {
757 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
758 }
759
760 static inline void
761 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
762 uint32_t sampler_state,
763 struct ilo_cp *cp)
764 {
765 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
766 }
767
768 static inline void
769 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
770 int subop, int offset, int size,
771 int entry_size,
772 struct ilo_cp *cp)
773 {
774 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
775 const uint8_t cmd_len = 2;
776 const int row_size = 64; /* 512 bits */
777 int alloc_size, num_entries, min_entries, max_entries;
778
779 ILO_GPE_VALID_GEN(dev, 7, 7);
780
781 /* VS, HS, DS, and GS variants */
782 assert(subop >= 0x30 && subop <= 0x33);
783
784 /* in multiples of 8KB */
785 assert(offset % 8192 == 0);
786 offset /= 8192;
787
788 /* in multiple of 512-bit rows */
789 alloc_size = (entry_size + row_size - 1) / row_size;
790 if (!alloc_size)
791 alloc_size = 1;
792
793 /*
794 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
795 *
796 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
797 * cause performance to decrease due to banking in the URB. Element
798 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
799 */
800 if (subop == 0x30 && alloc_size == 5)
801 alloc_size = 6;
802
803 /* in multiples of 8 */
804 num_entries = (size / row_size / alloc_size) & ~7;
805
806 switch (subop) {
807 case 0x30: /* 3DSTATE_URB_VS */
808 min_entries = 32;
809 max_entries = (dev->gt == 2) ? 704 : 512;
810
811 assert(num_entries >= min_entries);
812 if (num_entries > max_entries)
813 num_entries = max_entries;
814 break;
815 case 0x31: /* 3DSTATE_URB_HS */
816 max_entries = (dev->gt == 2) ? 64 : 32;
817 if (num_entries > max_entries)
818 num_entries = max_entries;
819 break;
820 case 0x32: /* 3DSTATE_URB_DS */
821 if (num_entries)
822 assert(num_entries >= 138);
823 break;
824 case 0x33: /* 3DSTATE_URB_GS */
825 max_entries = (dev->gt == 2) ? 320 : 192;
826 if (num_entries > max_entries)
827 num_entries = max_entries;
828 break;
829 default:
830 break;
831 }
832
833 ilo_cp_begin(cp, cmd_len);
834 ilo_cp_write(cp, cmd | (cmd_len - 2));
835 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
836 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
837 num_entries);
838 ilo_cp_end(cp);
839 }
840
841 static inline void
842 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
843 int offset, int size, int entry_size,
844 struct ilo_cp *cp)
845 {
846 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
847 }
848
849 static inline void
850 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
851 int offset, int size, int entry_size,
852 struct ilo_cp *cp)
853 {
854 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
855 }
856
857 static inline void
858 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
859 int offset, int size, int entry_size,
860 struct ilo_cp *cp)
861 {
862 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
863 }
864
865 static inline void
866 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
867 int offset, int size, int entry_size,
868 struct ilo_cp *cp)
869 {
870 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
871 }
872
873 static inline void
874 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
875 int subop, int offset, int size,
876 struct ilo_cp *cp)
877 {
878 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
879 const uint8_t cmd_len = 2;
880 int end;
881
882 ILO_GPE_VALID_GEN(dev, 7, 7);
883
884 /* VS, HS, DS, GS, and PS variants */
885 assert(subop >= 0x12 && subop <= 0x16);
886
887 /*
888 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
889 *
890 * "(A table that says the maximum size of each constant buffer is
891 * 16KB")
892 *
893 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
894 *
895 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
896 * may not exceed the maximum value of the Constant Buffer Size."
897 *
898 * Thus, the valid range of buffer end is [0KB, 16KB].
899 */
900 end = (offset + size) / 1024;
901 if (end > 16) {
902 assert(!"invalid constant buffer end");
903 end = 16;
904 }
905
906 /* the valid range of buffer offset is [0KB, 15KB] */
907 offset = (offset + 1023) / 1024;
908 if (offset > 15) {
909 assert(!"invalid constant buffer offset");
910 offset = 15;
911 }
912
913 if (offset > end) {
914 assert(!size);
915 offset = end;
916 }
917
918 /* the valid range of buffer size is [0KB, 15KB] */
919 size = end - offset;
920 if (size > 15) {
921 assert(!"invalid constant buffer size");
922 size = 15;
923 }
924
925 ilo_cp_begin(cp, cmd_len);
926 ilo_cp_write(cp, cmd | (cmd_len - 2));
927 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
928 size);
929 ilo_cp_end(cp);
930 }
931
932 static inline void
933 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
934 int offset, int size,
935 struct ilo_cp *cp)
936 {
937 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
938 }
939
940 static inline void
941 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
942 int offset, int size,
943 struct ilo_cp *cp)
944 {
945 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
946 }
947
948 static inline void
949 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
950 int offset, int size,
951 struct ilo_cp *cp)
952 {
953 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
954 }
955
956 static inline void
957 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
958 int offset, int size,
959 struct ilo_cp *cp)
960 {
961 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
962 }
963
964 static inline void
965 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
966 int offset, int size,
967 struct ilo_cp *cp)
968 {
969 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
970 }
971
972 static inline void
973 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
974 const struct pipe_stream_output_info *so_info,
975 struct ilo_cp *cp)
976 {
977 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
978 uint16_t cmd_len;
979 int buffer_selects, num_entries, i;
980 uint16_t so_decls[128];
981
982 ILO_GPE_VALID_GEN(dev, 7, 7);
983
984 buffer_selects = 0;
985 num_entries = 0;
986
987 if (so_info) {
988 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
989
990 memset(buffer_offsets, 0, sizeof(buffer_offsets));
991
992 for (i = 0; i < so_info->num_outputs; i++) {
993 unsigned decl, buf, reg, mask;
994
995 buf = so_info->output[i].output_buffer;
996
997 /* pad with holes */
998 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
999 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
1000 int num_dwords;
1001
1002 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1003 if (num_dwords > 4)
1004 num_dwords = 4;
1005
1006 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1007 SO_DECL_HOLE_FLAG |
1008 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1009
1010 so_decls[num_entries++] = decl;
1011 buffer_offsets[buf] += num_dwords;
1012 }
1013
1014 reg = so_info->output[i].register_index;
1015 mask = ((1 << so_info->output[i].num_components) - 1) <<
1016 so_info->output[i].start_component;
1017
1018 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1019 reg << SO_DECL_REGISTER_INDEX_SHIFT |
1020 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1021
1022 so_decls[num_entries++] = decl;
1023 buffer_selects |= 1 << buf;
1024 buffer_offsets[buf] += so_info->output[i].num_components;
1025 }
1026 }
1027
1028 /*
1029 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1030 *
1031 * "Errata: All 128 decls for all four streams must be included
1032 * whenever this command is issued. The "Num Entries [n]" fields still
1033 * contain the actual numbers of valid decls."
1034 *
1035 * Also note that "DWord Length" has 9 bits for this command, and the type
1036 * of cmd_len is thus uint16_t.
1037 */
1038 cmd_len = 2 * 128 + 3;
1039
1040 ilo_cp_begin(cp, cmd_len);
1041 ilo_cp_write(cp, cmd | (cmd_len - 2));
1042 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1043 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1044 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1045 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1046 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1047 0 << SO_NUM_ENTRIES_2_SHIFT |
1048 0 << SO_NUM_ENTRIES_1_SHIFT |
1049 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1050
1051 for (i = 0; i < num_entries; i++) {
1052 ilo_cp_write(cp, so_decls[i]);
1053 ilo_cp_write(cp, 0);
1054 }
1055 for (; i < 128; i++) {
1056 ilo_cp_write(cp, 0);
1057 ilo_cp_write(cp, 0);
1058 }
1059
1060 ilo_cp_end(cp);
1061 }
1062
1063 static inline void
1064 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1065 int index, int base, int stride,
1066 const struct pipe_stream_output_target *so_target,
1067 struct ilo_cp *cp)
1068 {
1069 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1070 const uint8_t cmd_len = 4;
1071 struct ilo_buffer *buf;
1072 int end;
1073
1074 ILO_GPE_VALID_GEN(dev, 7, 7);
1075
1076 if (!so_target || !so_target->buffer) {
1077 ilo_cp_begin(cp, cmd_len);
1078 ilo_cp_write(cp, cmd | (cmd_len - 2));
1079 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1080 ilo_cp_write(cp, 0);
1081 ilo_cp_write(cp, 0);
1082 ilo_cp_end(cp);
1083 return;
1084 }
1085
1086 buf = ilo_buffer(so_target->buffer);
1087
1088 /* DWord-aligned */
1089 assert(stride % 4 == 0 && base % 4 == 0);
1090 assert(so_target->buffer_offset % 4 == 0);
1091
1092 stride &= ~3;
1093 base = (base + so_target->buffer_offset) & ~3;
1094 end = (base + so_target->buffer_size) & ~3;
1095
1096 ilo_cp_begin(cp, cmd_len);
1097 ilo_cp_write(cp, cmd | (cmd_len - 2));
1098 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1099 stride);
1100 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1101 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1102 ilo_cp_end(cp);
1103 }
1104
1105 static inline void
1106 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1107 const struct pipe_draw_info *info,
1108 const struct ilo_ib_state *ib,
1109 bool rectlist,
1110 struct ilo_cp *cp)
1111 {
1112 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1113 const uint8_t cmd_len = 7;
1114 const int prim = (rectlist) ?
1115 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1116 const int vb_access = (info->indexed) ?
1117 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1118 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1119 const uint32_t vb_start = info->start +
1120 ((info->indexed) ? ib->draw_start_offset : 0);
1121
1122 ILO_GPE_VALID_GEN(dev, 7, 7);
1123
1124 ilo_cp_begin(cp, cmd_len);
1125 ilo_cp_write(cp, cmd | (cmd_len - 2));
1126 ilo_cp_write(cp, vb_access | prim);
1127 ilo_cp_write(cp, info->count);
1128 ilo_cp_write(cp, vb_start);
1129 ilo_cp_write(cp, info->instance_count);
1130 ilo_cp_write(cp, info->start_instance);
1131 ilo_cp_write(cp, info->index_bias);
1132 ilo_cp_end(cp);
1133 }
1134
1135 static inline uint32_t
1136 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1137 const struct ilo_viewport_cso *viewports,
1138 unsigned num_viewports,
1139 struct ilo_cp *cp)
1140 {
1141 const int state_align = 64 / 4;
1142 const int state_len = 16 * num_viewports;
1143 uint32_t state_offset, *dw;
1144 unsigned i;
1145
1146 ILO_GPE_VALID_GEN(dev, 7, 7);
1147
1148 /*
1149 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1150 *
1151 * "The viewport-specific state used by both the SF and CL units
1152 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1153 * of which contains the DWords described below. The start of each
1154 * element is spaced 16 DWords apart. The location of first element of
1155 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1156 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1157 */
1158 assert(num_viewports && num_viewports <= 16);
1159
1160 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1161 state_len, state_align, &state_offset);
1162
1163 for (i = 0; i < num_viewports; i++) {
1164 const struct ilo_viewport_cso *vp = &viewports[i];
1165
1166 dw[0] = fui(vp->m00);
1167 dw[1] = fui(vp->m11);
1168 dw[2] = fui(vp->m22);
1169 dw[3] = fui(vp->m30);
1170 dw[4] = fui(vp->m31);
1171 dw[5] = fui(vp->m32);
1172 dw[6] = 0;
1173 dw[7] = 0;
1174 dw[8] = fui(vp->min_gbx);
1175 dw[9] = fui(vp->max_gbx);
1176 dw[10] = fui(vp->min_gby);
1177 dw[11] = fui(vp->max_gby);
1178 dw[12] = 0;
1179 dw[13] = 0;
1180 dw[14] = 0;
1181 dw[15] = 0;
1182
1183 dw += 16;
1184 }
1185
1186 return state_offset;
1187 }
1188
1189 #endif /* ILO_GPE_GEN7_H */