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[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "intel_winsys.h"
32
33 #include "ilo_common.h"
34 #include "ilo_cp.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_gpe_gen6.h"
38
39 /**
40 * Commands that GEN7 GPE could emit.
41 */
42 enum ilo_gpe_gen7_command {
43 ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
44 ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
45 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
46 ILO_GPE_GEN7_PIPELINE_SELECT, /* (0x1, 0x1, 0x04) */
47 ILO_GPE_GEN7_MEDIA_VFE_STATE, /* (0x2, 0x0, 0x00) */
48 ILO_GPE_GEN7_MEDIA_CURBE_LOAD, /* (0x2, 0x0, 0x01) */
49 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD, /* (0x2, 0x0, 0x02) */
50 ILO_GPE_GEN7_MEDIA_STATE_FLUSH, /* (0x2, 0x0, 0x04) */
51 ILO_GPE_GEN7_GPGPU_WALKER, /* (0x2, 0x1, 0x05) */
52 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS, /* (0x3, 0x0, 0x04) */
53 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER, /* (0x3, 0x0, 0x05) */
54 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER, /* (0x3, 0x0, 0x06) */
55 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER, /* (0x3, 0x0, 0x07) */
56 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS, /* (0x3, 0x0, 0x08) */
57 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS, /* (0x3, 0x0, 0x09) */
58 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER, /* (0x3, 0x0, 0x0a) */
59 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS, /* (0x3, 0x0, 0x0e) */
60 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS, /* (0x3, 0x0, 0x0f) */
61 ILO_GPE_GEN7_3DSTATE_VS, /* (0x3, 0x0, 0x10) */
62 ILO_GPE_GEN7_3DSTATE_GS, /* (0x3, 0x0, 0x11) */
63 ILO_GPE_GEN7_3DSTATE_CLIP, /* (0x3, 0x0, 0x12) */
64 ILO_GPE_GEN7_3DSTATE_SF, /* (0x3, 0x0, 0x13) */
65 ILO_GPE_GEN7_3DSTATE_WM, /* (0x3, 0x0, 0x14) */
66 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS, /* (0x3, 0x0, 0x15) */
67 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS, /* (0x3, 0x0, 0x16) */
68 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS, /* (0x3, 0x0, 0x17) */
69 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK, /* (0x3, 0x0, 0x18) */
70 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS, /* (0x3, 0x0, 0x19) */
71 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS, /* (0x3, 0x0, 0x1a) */
72 ILO_GPE_GEN7_3DSTATE_HS, /* (0x3, 0x0, 0x1b) */
73 ILO_GPE_GEN7_3DSTATE_TE, /* (0x3, 0x0, 0x1c) */
74 ILO_GPE_GEN7_3DSTATE_DS, /* (0x3, 0x0, 0x1d) */
75 ILO_GPE_GEN7_3DSTATE_STREAMOUT, /* (0x3, 0x0, 0x1e) */
76 ILO_GPE_GEN7_3DSTATE_SBE, /* (0x3, 0x0, 0x1f) */
77 ILO_GPE_GEN7_3DSTATE_PS, /* (0x3, 0x0, 0x20) */
78 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, /* (0x3, 0x0, 0x21) */
79 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC, /* (0x3, 0x0, 0x23) */
80 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS, /* (0x3, 0x0, 0x24) */
81 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, /* (0x3, 0x0, 0x25) */
82 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, /* (0x3, 0x0, 0x26) */
83 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, /* (0x3, 0x0, 0x27) */
84 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, /* (0x3, 0x0, 0x28) */
85 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, /* (0x3, 0x0, 0x29) */
86 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, /* (0x3, 0x0, 0x2a) */
87 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, /* (0x3, 0x0, 0x2b) */
88 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, /* (0x3, 0x0, 0x2c) */
89 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, /* (0x3, 0x0, 0x2d) */
90 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, /* (0x3, 0x0, 0x2e) */
91 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, /* (0x3, 0x0, 0x2f) */
92 ILO_GPE_GEN7_3DSTATE_URB_VS, /* (0x3, 0x0, 0x30) */
93 ILO_GPE_GEN7_3DSTATE_URB_HS, /* (0x3, 0x0, 0x31) */
94 ILO_GPE_GEN7_3DSTATE_URB_DS, /* (0x3, 0x0, 0x32) */
95 ILO_GPE_GEN7_3DSTATE_URB_GS, /* (0x3, 0x0, 0x33) */
96 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE, /* (0x3, 0x1, 0x00) */
97 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET, /* (0x3, 0x1, 0x06) */
98 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN, /* (0x3, 0x1, 0x07) */
99 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE, /* (0x3, 0x1, 0x08) */
100 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS, /* (0x3, 0x1, 0x0a) */
101 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE, /* (0x3, 0x1, 0x0d) */
102 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, /* (0x3, 0x1, 0x12) */
103 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, /* (0x3, 0x1, 0x13) */
104 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, /* (0x3, 0x1, 0x14) */
105 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, /* (0x3, 0x1, 0x15) */
106 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, /* (0x3, 0x1, 0x16) */
107 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST, /* (0x3, 0x1, 0x17) */
108 ILO_GPE_GEN7_3DSTATE_SO_BUFFER, /* (0x3, 0x1, 0x18) */
109 ILO_GPE_GEN7_PIPE_CONTROL, /* (0x3, 0x2, 0x00) */
110 ILO_GPE_GEN7_3DPRIMITIVE, /* (0x3, 0x3, 0x00) */
111
112 ILO_GPE_GEN7_COMMAND_COUNT,
113 };
114
115 /**
116 * Indirect states that GEN7 GPE could emit.
117 */
118 enum ilo_gpe_gen7_state {
119 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA,
120 ILO_GPE_GEN7_SF_CLIP_VIEWPORT,
121 ILO_GPE_GEN7_CC_VIEWPORT,
122 ILO_GPE_GEN7_COLOR_CALC_STATE,
123 ILO_GPE_GEN7_BLEND_STATE,
124 ILO_GPE_GEN7_DEPTH_STENCIL_STATE,
125 ILO_GPE_GEN7_SCISSOR_RECT,
126 ILO_GPE_GEN7_BINDING_TABLE_STATE,
127 ILO_GPE_GEN7_SURFACE_STATE,
128 ILO_GPE_GEN7_SAMPLER_STATE,
129 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE,
130 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER,
131
132 ILO_GPE_GEN7_STATE_COUNT,
133 };
134
135 int
136 ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
137 enum ilo_gpe_gen7_command cmd,
138 int arg);
139
140 int
141 ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev,
142 enum ilo_gpe_gen7_state state,
143 int arg);
144
145 static inline void
146 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
147 struct ilo_cp *cp)
148 {
149 assert(!"GPGPU_WALKER unsupported");
150 }
151
152 static inline void
153 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
154 uint32_t clear_val,
155 struct ilo_cp *cp)
156 {
157 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
158 const uint8_t cmd_len = 3;
159
160 ILO_GPE_VALID_GEN(dev, 7, 7);
161
162 ilo_cp_begin(cp, cmd_len);
163 ilo_cp_write(cp, cmd | (cmd_len - 2));
164 ilo_cp_write(cp, clear_val);
165 ilo_cp_write(cp, 1);
166 ilo_cp_end(cp);
167 }
168
169 static inline void
170 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
171 int subop, uint32_t pointer,
172 struct ilo_cp *cp)
173 {
174 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
175 const uint8_t cmd_len = 2;
176
177 ILO_GPE_VALID_GEN(dev, 7, 7);
178
179 ilo_cp_begin(cp, cmd_len);
180 ilo_cp_write(cp, cmd | (cmd_len - 2));
181 ilo_cp_write(cp, pointer);
182 ilo_cp_end(cp);
183 }
184
185 static inline void
186 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
187 uint32_t color_calc_state,
188 struct ilo_cp *cp)
189 {
190 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
191 }
192
193 static inline void
194 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
195 const struct ilo_shader_state *gs,
196 int num_samplers,
197 struct ilo_cp *cp)
198 {
199 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
200 const uint8_t cmd_len = 7;
201 const struct ilo_shader_cso *cso;
202 uint32_t dw2, dw4, dw5;
203
204 ILO_GPE_VALID_GEN(dev, 7, 7);
205
206 if (!gs) {
207 ilo_cp_begin(cp, cmd_len);
208 ilo_cp_write(cp, cmd | (cmd_len - 2));
209 ilo_cp_write(cp, 0);
210 ilo_cp_write(cp, 0);
211 ilo_cp_write(cp, 0);
212 ilo_cp_write(cp, 0);
213 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
214 ilo_cp_write(cp, 0);
215 ilo_cp_end(cp);
216 return;
217 }
218
219 cso = ilo_shader_get_kernel_cso(gs);
220 dw2 = cso->payload[0];
221 dw4 = cso->payload[1];
222 dw5 = cso->payload[2];
223
224 dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
225
226 ilo_cp_begin(cp, cmd_len);
227 ilo_cp_write(cp, cmd | (cmd_len - 2));
228 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
229 ilo_cp_write(cp, dw2);
230 ilo_cp_write(cp, 0); /* scratch */
231 ilo_cp_write(cp, dw4);
232 ilo_cp_write(cp, dw5);
233 ilo_cp_write(cp, 0);
234 ilo_cp_end(cp);
235 }
236
237 static inline void
238 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
239 const struct ilo_rasterizer_state *rasterizer,
240 const struct pipe_surface *zs_surf,
241 struct ilo_cp *cp)
242 {
243 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
244 const uint8_t cmd_len = 7;
245 const int num_samples = 1;
246 uint32_t payload[6];
247
248 ILO_GPE_VALID_GEN(dev, 7, 7);
249
250 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
251 rasterizer, num_samples,
252 (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE,
253 payload, Elements(payload));
254
255 ilo_cp_begin(cp, cmd_len);
256 ilo_cp_write(cp, cmd | (cmd_len - 2));
257 ilo_cp_write_multi(cp, payload, 6);
258 ilo_cp_end(cp);
259 }
260
261 static inline void
262 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
263 const struct ilo_shader_state *fs,
264 const struct ilo_rasterizer_state *rasterizer,
265 bool cc_may_kill,
266 struct ilo_cp *cp)
267 {
268 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
269 const uint8_t cmd_len = 3;
270 const int num_samples = 1;
271 uint32_t dw1, dw2;
272
273 ILO_GPE_VALID_GEN(dev, 7, 7);
274
275 /* see ilo_gpe_init_rasterizer_wm() */
276 dw1 = rasterizer->wm.payload[0];
277 dw2 = rasterizer->wm.payload[1];
278
279 dw1 |= GEN7_WM_STATISTICS_ENABLE;
280
281 if (false) {
282 dw1 |= GEN7_WM_DEPTH_CLEAR;
283 dw1 |= GEN7_WM_DEPTH_RESOLVE;
284 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
285 }
286
287 if (fs) {
288 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
289
290 dw1 |= fs_cso->payload[3];
291 }
292
293 if (cc_may_kill) {
294 dw1 |= GEN7_WM_DISPATCH_ENABLE |
295 GEN7_WM_KILL_ENABLE;
296 }
297
298 if (num_samples > 1) {
299 dw1 |= rasterizer->wm.dw_msaa_rast;
300 dw2 |= rasterizer->wm.dw_msaa_disp;
301 }
302
303 ilo_cp_begin(cp, cmd_len);
304 ilo_cp_write(cp, cmd | (cmd_len - 2));
305 ilo_cp_write(cp, dw1);
306 ilo_cp_write(cp, dw2);
307 ilo_cp_end(cp);
308 }
309
310 static inline void
311 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
312 int subop,
313 const uint32_t *bufs, const int *sizes,
314 int num_bufs,
315 struct ilo_cp *cp)
316 {
317 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
318 const uint8_t cmd_len = 7;
319 uint32_t dw[6];
320 int total_read_length, i;
321
322 ILO_GPE_VALID_GEN(dev, 7, 7);
323
324 /* VS, HS, DS, GS, and PS variants */
325 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
326
327 assert(num_bufs <= 4);
328
329 dw[0] = 0;
330 dw[1] = 0;
331
332 total_read_length = 0;
333 for (i = 0; i < 4; i++) {
334 int read_len;
335
336 /*
337 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
338 *
339 * "Constant buffers must be enabled in order from Constant Buffer 0
340 * to Constant Buffer 3 within this command. For example, it is
341 * not allowed to enable Constant Buffer 1 by programming a
342 * non-zero value in the VS Constant Buffer 1 Read Length without a
343 * non-zero value in VS Constant Buffer 0 Read Length."
344 */
345 if (i >= num_bufs || !sizes[i]) {
346 for (; i < 4; i++) {
347 assert(i >= num_bufs || !sizes[i]);
348 dw[2 + i] = 0;
349 }
350 break;
351 }
352
353 /* read lengths are in 256-bit units */
354 read_len = (sizes[i] + 31) / 32;
355 /* the lower 5 bits are used for memory object control state */
356 assert(bufs[i] % 32 == 0);
357
358 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
359 dw[2 + i] = bufs[i];
360
361 total_read_length += read_len;
362 }
363
364 /*
365 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
366 *
367 * "The sum of all four read length fields must be less than or equal
368 * to the size of 64"
369 */
370 assert(total_read_length <= 64);
371
372 ilo_cp_begin(cp, cmd_len);
373 ilo_cp_write(cp, cmd | (cmd_len - 2));
374 ilo_cp_write_multi(cp, dw, 6);
375 ilo_cp_end(cp);
376 }
377
378 static inline void
379 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
380 const uint32_t *bufs, const int *sizes,
381 int num_bufs,
382 struct ilo_cp *cp)
383 {
384 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
385 }
386
387 static inline void
388 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
389 const uint32_t *bufs, const int *sizes,
390 int num_bufs,
391 struct ilo_cp *cp)
392 {
393 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
394 }
395
396 static inline void
397 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
398 const uint32_t *bufs, const int *sizes,
399 int num_bufs,
400 struct ilo_cp *cp)
401 {
402 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
403 }
404
405 static inline void
406 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
407 unsigned sample_mask,
408 int num_samples,
409 struct ilo_cp *cp)
410 {
411 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
412 const uint8_t cmd_len = 2;
413 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
414
415 ILO_GPE_VALID_GEN(dev, 7, 7);
416
417 /*
418 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
419 *
420 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
421 * (Sample Mask) must be zero.
422 *
423 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
424 * must be zero."
425 */
426 sample_mask &= valid_mask;
427
428 ilo_cp_begin(cp, cmd_len);
429 ilo_cp_write(cp, cmd | (cmd_len - 2));
430 ilo_cp_write(cp, sample_mask);
431 ilo_cp_end(cp);
432 }
433
434 static inline void
435 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
436 const uint32_t *bufs, const int *sizes,
437 int num_bufs,
438 struct ilo_cp *cp)
439 {
440 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
441 }
442
443 static inline void
444 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
445 const uint32_t *bufs, const int *sizes,
446 int num_bufs,
447 struct ilo_cp *cp)
448 {
449 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
450 }
451
452 static inline void
453 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
454 const struct ilo_shader_state *hs,
455 int num_samplers,
456 struct ilo_cp *cp)
457 {
458 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
459 const uint8_t cmd_len = 7;
460
461 ILO_GPE_VALID_GEN(dev, 7, 7);
462
463 assert(!hs);
464
465 ilo_cp_begin(cp, cmd_len);
466 ilo_cp_write(cp, cmd | (cmd_len - 2));
467 ilo_cp_write(cp, 0);
468 ilo_cp_write(cp, 0);
469 ilo_cp_write(cp, 0);
470 ilo_cp_write(cp, 0);
471 ilo_cp_write(cp, 0);
472 ilo_cp_write(cp, 0);
473 ilo_cp_end(cp);
474 }
475
476 static inline void
477 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
478 struct ilo_cp *cp)
479 {
480 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
481 const uint8_t cmd_len = 4;
482
483 ILO_GPE_VALID_GEN(dev, 7, 7);
484
485 ilo_cp_begin(cp, cmd_len);
486 ilo_cp_write(cp, cmd | (cmd_len - 2));
487 ilo_cp_write(cp, 0);
488 ilo_cp_write(cp, 0);
489 ilo_cp_write(cp, 0);
490 ilo_cp_end(cp);
491 }
492
493 static inline void
494 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
495 const struct ilo_shader_state *ds,
496 int num_samplers,
497 struct ilo_cp *cp)
498 {
499 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
500 const uint8_t cmd_len = 6;
501
502 ILO_GPE_VALID_GEN(dev, 7, 7);
503
504 assert(!ds);
505
506 ilo_cp_begin(cp, cmd_len);
507 ilo_cp_write(cp, cmd | (cmd_len - 2));
508 ilo_cp_write(cp, 0);
509 ilo_cp_write(cp, 0);
510 ilo_cp_write(cp, 0);
511 ilo_cp_write(cp, 0);
512 ilo_cp_write(cp, 0);
513 ilo_cp_end(cp);
514
515 }
516
517 static inline void
518 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
519 unsigned buffer_mask,
520 int vertex_attrib_count,
521 bool rasterizer_discard,
522 struct ilo_cp *cp)
523 {
524 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
525 const uint8_t cmd_len = 3;
526 const bool enable = (buffer_mask != 0);
527 uint32_t dw1, dw2;
528 int read_len;
529
530 ILO_GPE_VALID_GEN(dev, 7, 7);
531
532 if (!enable) {
533 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
534 if (rasterizer_discard)
535 dw1 |= SO_RENDERING_DISABLE;
536
537 dw2 = 0;
538
539 ilo_cp_begin(cp, cmd_len);
540 ilo_cp_write(cp, cmd | (cmd_len - 2));
541 ilo_cp_write(cp, dw1);
542 ilo_cp_write(cp, dw2);
543 ilo_cp_end(cp);
544 return;
545 }
546
547 read_len = (vertex_attrib_count + 1) / 2;
548 if (!read_len)
549 read_len = 1;
550
551 dw1 = SO_FUNCTION_ENABLE |
552 0 << SO_RENDER_STREAM_SELECT_SHIFT |
553 SO_STATISTICS_ENABLE |
554 buffer_mask << 8;
555
556 if (rasterizer_discard)
557 dw1 |= SO_RENDERING_DISABLE;
558
559 /* API_OPENGL */
560 if (true)
561 dw1 |= SO_REORDER_TRAILING;
562
563 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
564 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
565 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
566 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
567 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
568 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
569 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
570 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
571
572 ilo_cp_begin(cp, cmd_len);
573 ilo_cp_write(cp, cmd | (cmd_len - 2));
574 ilo_cp_write(cp, dw1);
575 ilo_cp_write(cp, dw2);
576 ilo_cp_end(cp);
577 }
578
579 static inline void
580 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
581 const struct ilo_rasterizer_state *rasterizer,
582 const struct ilo_shader_state *fs,
583 struct ilo_cp *cp)
584 {
585 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
586 const uint8_t cmd_len = 14;
587 uint32_t dw[13];
588
589 ILO_GPE_VALID_GEN(dev, 7, 7);
590
591 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer, fs, dw, Elements(dw));
592
593 ilo_cp_begin(cp, cmd_len);
594 ilo_cp_write(cp, cmd | (cmd_len - 2));
595 ilo_cp_write_multi(cp, dw, 13);
596 ilo_cp_end(cp);
597 }
598
599 static inline void
600 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
601 const struct ilo_shader_state *fs,
602 int num_samplers, bool dual_blend,
603 struct ilo_cp *cp)
604 {
605 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
606 const uint8_t cmd_len = 8;
607 const struct ilo_shader_cso *cso;
608 uint32_t dw2, dw4, dw5;
609
610 ILO_GPE_VALID_GEN(dev, 7, 7);
611
612 if (!fs) {
613 /* see brwCreateContext() */
614 const int max_threads = (dev->gt == 2) ? 172 : 48;
615
616 ilo_cp_begin(cp, cmd_len);
617 ilo_cp_write(cp, cmd | (cmd_len - 2));
618 ilo_cp_write(cp, 0);
619 ilo_cp_write(cp, 0);
620 ilo_cp_write(cp, 0);
621 /* GPU hangs if none of the dispatch enable bits is set */
622 ilo_cp_write(cp, (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT |
623 GEN7_PS_8_DISPATCH_ENABLE);
624 ilo_cp_write(cp, 0);
625 ilo_cp_write(cp, 0);
626 ilo_cp_write(cp, 0);
627 ilo_cp_end(cp);
628
629 return;
630 }
631
632 cso = ilo_shader_get_kernel_cso(fs);
633 dw2 = cso->payload[0];
634 dw4 = cso->payload[1];
635 dw5 = cso->payload[2];
636
637 dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT;
638
639 if (dual_blend)
640 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
641
642 ilo_cp_begin(cp, cmd_len);
643 ilo_cp_write(cp, cmd | (cmd_len - 2));
644 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
645 ilo_cp_write(cp, dw2);
646 ilo_cp_write(cp, 0); /* scratch */
647 ilo_cp_write(cp, dw4);
648 ilo_cp_write(cp, dw5);
649 ilo_cp_write(cp, 0); /* kernel 1 */
650 ilo_cp_write(cp, 0); /* kernel 2 */
651 ilo_cp_end(cp);
652 }
653
654 static inline void
655 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
656 uint32_t sf_clip_viewport,
657 struct ilo_cp *cp)
658 {
659 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
660 }
661
662 static inline void
663 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
664 uint32_t cc_viewport,
665 struct ilo_cp *cp)
666 {
667 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
668 }
669
670 static inline void
671 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
672 uint32_t blend_state,
673 struct ilo_cp *cp)
674 {
675 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
676 }
677
678 static inline void
679 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
680 uint32_t depth_stencil_state,
681 struct ilo_cp *cp)
682 {
683 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
684 }
685
686 static inline void
687 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
688 uint32_t binding_table,
689 struct ilo_cp *cp)
690 {
691 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
692 }
693
694 static inline void
695 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
696 uint32_t binding_table,
697 struct ilo_cp *cp)
698 {
699 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
700 }
701
702 static inline void
703 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
704 uint32_t binding_table,
705 struct ilo_cp *cp)
706 {
707 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
708 }
709
710 static inline void
711 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
712 uint32_t binding_table,
713 struct ilo_cp *cp)
714 {
715 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
716 }
717
718 static inline void
719 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
720 uint32_t binding_table,
721 struct ilo_cp *cp)
722 {
723 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
724 }
725
726 static inline void
727 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
728 uint32_t sampler_state,
729 struct ilo_cp *cp)
730 {
731 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
732 }
733
734 static inline void
735 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
736 uint32_t sampler_state,
737 struct ilo_cp *cp)
738 {
739 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
740 }
741
742 static inline void
743 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
744 uint32_t sampler_state,
745 struct ilo_cp *cp)
746 {
747 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
748 }
749
750 static inline void
751 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
752 uint32_t sampler_state,
753 struct ilo_cp *cp)
754 {
755 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
756 }
757
758 static inline void
759 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
760 uint32_t sampler_state,
761 struct ilo_cp *cp)
762 {
763 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
764 }
765
766 static inline void
767 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
768 int subop, int offset, int size,
769 int entry_size,
770 struct ilo_cp *cp)
771 {
772 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
773 const uint8_t cmd_len = 2;
774 const int row_size = 64; /* 512 bits */
775 int alloc_size, num_entries, min_entries, max_entries;
776
777 ILO_GPE_VALID_GEN(dev, 7, 7);
778
779 /* VS, HS, DS, and GS variants */
780 assert(subop >= 0x30 && subop <= 0x33);
781
782 /* in multiples of 8KB */
783 assert(offset % 8192 == 0);
784 offset /= 8192;
785
786 /* in multiple of 512-bit rows */
787 alloc_size = (entry_size + row_size - 1) / row_size;
788 if (!alloc_size)
789 alloc_size = 1;
790
791 /*
792 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
793 *
794 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
795 * cause performance to decrease due to banking in the URB. Element
796 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
797 */
798 if (subop == 0x30 && alloc_size == 5)
799 alloc_size = 6;
800
801 /* in multiples of 8 */
802 num_entries = (size / row_size / alloc_size) & ~7;
803
804 switch (subop) {
805 case 0x30: /* 3DSTATE_URB_VS */
806 min_entries = 32;
807 max_entries = (dev->gt == 2) ? 704 : 512;
808
809 assert(num_entries >= min_entries);
810 if (num_entries > max_entries)
811 num_entries = max_entries;
812 break;
813 case 0x31: /* 3DSTATE_URB_HS */
814 max_entries = (dev->gt == 2) ? 64 : 32;
815 if (num_entries > max_entries)
816 num_entries = max_entries;
817 break;
818 case 0x32: /* 3DSTATE_URB_DS */
819 if (num_entries)
820 assert(num_entries >= 138);
821 break;
822 case 0x33: /* 3DSTATE_URB_GS */
823 max_entries = (dev->gt == 2) ? 320 : 192;
824 if (num_entries > max_entries)
825 num_entries = max_entries;
826 break;
827 default:
828 break;
829 }
830
831 ilo_cp_begin(cp, cmd_len);
832 ilo_cp_write(cp, cmd | (cmd_len - 2));
833 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
834 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
835 num_entries);
836 ilo_cp_end(cp);
837 }
838
839 static inline void
840 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
841 int offset, int size, int entry_size,
842 struct ilo_cp *cp)
843 {
844 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
845 }
846
847 static inline void
848 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
849 int offset, int size, int entry_size,
850 struct ilo_cp *cp)
851 {
852 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
853 }
854
855 static inline void
856 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
857 int offset, int size, int entry_size,
858 struct ilo_cp *cp)
859 {
860 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
861 }
862
863 static inline void
864 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
865 int offset, int size, int entry_size,
866 struct ilo_cp *cp)
867 {
868 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
869 }
870
871 static inline void
872 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
873 int subop, int offset, int size,
874 struct ilo_cp *cp)
875 {
876 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
877 const uint8_t cmd_len = 2;
878 int end;
879
880 ILO_GPE_VALID_GEN(dev, 7, 7);
881
882 /* VS, HS, DS, GS, and PS variants */
883 assert(subop >= 0x12 && subop <= 0x16);
884
885 /*
886 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
887 *
888 * "(A table that says the maximum size of each constant buffer is
889 * 16KB")
890 *
891 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
892 *
893 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
894 * may not exceed the maximum value of the Constant Buffer Size."
895 *
896 * Thus, the valid range of buffer end is [0KB, 16KB].
897 */
898 end = (offset + size) / 1024;
899 if (end > 16) {
900 assert(!"invalid constant buffer end");
901 end = 16;
902 }
903
904 /* the valid range of buffer offset is [0KB, 15KB] */
905 offset = (offset + 1023) / 1024;
906 if (offset > 15) {
907 assert(!"invalid constant buffer offset");
908 offset = 15;
909 }
910
911 if (offset > end) {
912 assert(!size);
913 offset = end;
914 }
915
916 /* the valid range of buffer size is [0KB, 15KB] */
917 size = end - offset;
918 if (size > 15) {
919 assert(!"invalid constant buffer size");
920 size = 15;
921 }
922
923 ilo_cp_begin(cp, cmd_len);
924 ilo_cp_write(cp, cmd | (cmd_len - 2));
925 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
926 size);
927 ilo_cp_end(cp);
928 }
929
930 static inline void
931 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
932 int offset, int size,
933 struct ilo_cp *cp)
934 {
935 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
936 }
937
938 static inline void
939 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
940 int offset, int size,
941 struct ilo_cp *cp)
942 {
943 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
944 }
945
946 static inline void
947 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
948 int offset, int size,
949 struct ilo_cp *cp)
950 {
951 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
952 }
953
954 static inline void
955 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
956 int offset, int size,
957 struct ilo_cp *cp)
958 {
959 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
960 }
961
962 static inline void
963 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
964 int offset, int size,
965 struct ilo_cp *cp)
966 {
967 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
968 }
969
970 static inline void
971 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
972 const struct pipe_stream_output_info *so_info,
973 struct ilo_cp *cp)
974 {
975 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
976 uint16_t cmd_len;
977 int buffer_selects, num_entries, i;
978 uint16_t so_decls[128];
979
980 ILO_GPE_VALID_GEN(dev, 7, 7);
981
982 buffer_selects = 0;
983 num_entries = 0;
984
985 if (so_info) {
986 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
987
988 memset(buffer_offsets, 0, sizeof(buffer_offsets));
989
990 for (i = 0; i < so_info->num_outputs; i++) {
991 unsigned decl, buf, reg, mask;
992
993 buf = so_info->output[i].output_buffer;
994
995 /* pad with holes */
996 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
997 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
998 int num_dwords;
999
1000 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1001 if (num_dwords > 4)
1002 num_dwords = 4;
1003
1004 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1005 SO_DECL_HOLE_FLAG |
1006 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1007
1008 so_decls[num_entries++] = decl;
1009 buffer_offsets[buf] += num_dwords;
1010 }
1011
1012 reg = so_info->output[i].register_index;
1013 mask = ((1 << so_info->output[i].num_components) - 1) <<
1014 so_info->output[i].start_component;
1015
1016 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1017 reg << SO_DECL_REGISTER_INDEX_SHIFT |
1018 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1019
1020 so_decls[num_entries++] = decl;
1021 buffer_selects |= 1 << buf;
1022 buffer_offsets[buf] += so_info->output[i].num_components;
1023 }
1024 }
1025
1026 /*
1027 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1028 *
1029 * "Errata: All 128 decls for all four streams must be included
1030 * whenever this command is issued. The "Num Entries [n]" fields still
1031 * contain the actual numbers of valid decls."
1032 *
1033 * Also note that "DWord Length" has 9 bits for this command, and the type
1034 * of cmd_len is thus uint16_t.
1035 */
1036 cmd_len = 2 * 128 + 3;
1037
1038 ilo_cp_begin(cp, cmd_len);
1039 ilo_cp_write(cp, cmd | (cmd_len - 2));
1040 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1041 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1042 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1043 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1044 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1045 0 << SO_NUM_ENTRIES_2_SHIFT |
1046 0 << SO_NUM_ENTRIES_1_SHIFT |
1047 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1048
1049 for (i = 0; i < num_entries; i++) {
1050 ilo_cp_write(cp, so_decls[i]);
1051 ilo_cp_write(cp, 0);
1052 }
1053 for (; i < 128; i++) {
1054 ilo_cp_write(cp, 0);
1055 ilo_cp_write(cp, 0);
1056 }
1057
1058 ilo_cp_end(cp);
1059 }
1060
1061 static inline void
1062 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1063 int index, int base, int stride,
1064 const struct pipe_stream_output_target *so_target,
1065 struct ilo_cp *cp)
1066 {
1067 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1068 const uint8_t cmd_len = 4;
1069 struct ilo_buffer *buf;
1070 int end;
1071
1072 ILO_GPE_VALID_GEN(dev, 7, 7);
1073
1074 if (!so_target || !so_target->buffer) {
1075 ilo_cp_begin(cp, cmd_len);
1076 ilo_cp_write(cp, cmd | (cmd_len - 2));
1077 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1078 ilo_cp_write(cp, 0);
1079 ilo_cp_write(cp, 0);
1080 ilo_cp_end(cp);
1081 return;
1082 }
1083
1084 buf = ilo_buffer(so_target->buffer);
1085
1086 /* DWord-aligned */
1087 assert(stride % 4 == 0 && base % 4 == 0);
1088 assert(so_target->buffer_offset % 4 == 0);
1089
1090 stride &= ~3;
1091 base = (base + so_target->buffer_offset) & ~3;
1092 end = (base + so_target->buffer_size) & ~3;
1093
1094 ilo_cp_begin(cp, cmd_len);
1095 ilo_cp_write(cp, cmd | (cmd_len - 2));
1096 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1097 stride);
1098 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1099 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1100 ilo_cp_end(cp);
1101 }
1102
1103 static inline void
1104 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1105 const struct pipe_draw_info *info,
1106 const struct ilo_ib_state *ib,
1107 bool rectlist,
1108 struct ilo_cp *cp)
1109 {
1110 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1111 const uint8_t cmd_len = 7;
1112 const int prim = (rectlist) ?
1113 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1114 const int vb_access = (info->indexed) ?
1115 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1116 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1117 const uint32_t vb_start = info->start +
1118 ((info->indexed) ? ib->draw_start_offset : 0);
1119
1120 ILO_GPE_VALID_GEN(dev, 7, 7);
1121
1122 ilo_cp_begin(cp, cmd_len);
1123 ilo_cp_write(cp, cmd | (cmd_len - 2));
1124 ilo_cp_write(cp, vb_access | prim);
1125 ilo_cp_write(cp, info->count);
1126 ilo_cp_write(cp, vb_start);
1127 ilo_cp_write(cp, info->instance_count);
1128 ilo_cp_write(cp, info->start_instance);
1129 ilo_cp_write(cp, info->index_bias);
1130 ilo_cp_end(cp);
1131 }
1132
1133 static inline uint32_t
1134 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1135 const struct ilo_viewport_cso *viewports,
1136 unsigned num_viewports,
1137 struct ilo_cp *cp)
1138 {
1139 const int state_align = 64 / 4;
1140 const int state_len = 16 * num_viewports;
1141 uint32_t state_offset, *dw;
1142 unsigned i;
1143
1144 ILO_GPE_VALID_GEN(dev, 7, 7);
1145
1146 /*
1147 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1148 *
1149 * "The viewport-specific state used by both the SF and CL units
1150 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1151 * of which contains the DWords described below. The start of each
1152 * element is spaced 16 DWords apart. The location of first element of
1153 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1154 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1155 */
1156 assert(num_viewports && num_viewports <= 16);
1157
1158 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1159 state_len, state_align, &state_offset);
1160
1161 for (i = 0; i < num_viewports; i++) {
1162 const struct ilo_viewport_cso *vp = &viewports[i];
1163
1164 dw[0] = fui(vp->m00);
1165 dw[1] = fui(vp->m11);
1166 dw[2] = fui(vp->m22);
1167 dw[3] = fui(vp->m30);
1168 dw[4] = fui(vp->m31);
1169 dw[5] = fui(vp->m32);
1170 dw[6] = 0;
1171 dw[7] = 0;
1172 dw[8] = fui(vp->min_gbx);
1173 dw[9] = fui(vp->max_gbx);
1174 dw[10] = fui(vp->min_gby);
1175 dw[11] = fui(vp->max_gby);
1176 dw[12] = 0;
1177 dw[13] = 0;
1178 dw[14] = 0;
1179 dw[15] = 0;
1180
1181 dw += 16;
1182 }
1183
1184 return state_offset;
1185 }
1186
1187 #endif /* ILO_GPE_GEN7_H */