2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
31 #include "ilo_common.h"
32 #include "ilo_gpe_gen6.h"
35 * Commands that GEN7 GPE could emit.
37 enum ilo_gpe_gen7_command
{
38 ILO_GPE_GEN7_STATE_BASE_ADDRESS
, /* (0x0, 0x1, 0x01) */
39 ILO_GPE_GEN7_STATE_SIP
, /* (0x0, 0x1, 0x02) */
40 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS
, /* (0x1, 0x0, 0x0b) */
41 ILO_GPE_GEN7_PIPELINE_SELECT
, /* (0x1, 0x1, 0x04) */
42 ILO_GPE_GEN7_MEDIA_VFE_STATE
, /* (0x2, 0x0, 0x00) */
43 ILO_GPE_GEN7_MEDIA_CURBE_LOAD
, /* (0x2, 0x0, 0x01) */
44 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD
, /* (0x2, 0x0, 0x02) */
45 ILO_GPE_GEN7_MEDIA_STATE_FLUSH
, /* (0x2, 0x0, 0x04) */
46 ILO_GPE_GEN7_GPGPU_WALKER
, /* (0x2, 0x1, 0x05) */
47 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS
, /* (0x3, 0x0, 0x04) */
48 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER
, /* (0x3, 0x0, 0x05) */
49 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER
, /* (0x3, 0x0, 0x06) */
50 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER
, /* (0x3, 0x0, 0x07) */
51 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS
, /* (0x3, 0x0, 0x08) */
52 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS
, /* (0x3, 0x0, 0x09) */
53 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER
, /* (0x3, 0x0, 0x0a) */
54 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS
, /* (0x3, 0x0, 0x0e) */
55 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS
, /* (0x3, 0x0, 0x0f) */
56 ILO_GPE_GEN7_3DSTATE_VS
, /* (0x3, 0x0, 0x10) */
57 ILO_GPE_GEN7_3DSTATE_GS
, /* (0x3, 0x0, 0x11) */
58 ILO_GPE_GEN7_3DSTATE_CLIP
, /* (0x3, 0x0, 0x12) */
59 ILO_GPE_GEN7_3DSTATE_SF
, /* (0x3, 0x0, 0x13) */
60 ILO_GPE_GEN7_3DSTATE_WM
, /* (0x3, 0x0, 0x14) */
61 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS
, /* (0x3, 0x0, 0x15) */
62 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS
, /* (0x3, 0x0, 0x16) */
63 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS
, /* (0x3, 0x0, 0x17) */
64 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK
, /* (0x3, 0x0, 0x18) */
65 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS
, /* (0x3, 0x0, 0x19) */
66 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS
, /* (0x3, 0x0, 0x1a) */
67 ILO_GPE_GEN7_3DSTATE_HS
, /* (0x3, 0x0, 0x1b) */
68 ILO_GPE_GEN7_3DSTATE_TE
, /* (0x3, 0x0, 0x1c) */
69 ILO_GPE_GEN7_3DSTATE_DS
, /* (0x3, 0x0, 0x1d) */
70 ILO_GPE_GEN7_3DSTATE_STREAMOUT
, /* (0x3, 0x0, 0x1e) */
71 ILO_GPE_GEN7_3DSTATE_SBE
, /* (0x3, 0x0, 0x1f) */
72 ILO_GPE_GEN7_3DSTATE_PS
, /* (0x3, 0x0, 0x20) */
73 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
, /* (0x3, 0x0, 0x21) */
74 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC
, /* (0x3, 0x0, 0x23) */
75 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS
, /* (0x3, 0x0, 0x24) */
76 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
, /* (0x3, 0x0, 0x25) */
77 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS
, /* (0x3, 0x0, 0x26) */
78 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS
, /* (0x3, 0x0, 0x27) */
79 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS
, /* (0x3, 0x0, 0x28) */
80 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS
, /* (0x3, 0x0, 0x29) */
81 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS
, /* (0x3, 0x0, 0x2a) */
82 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS
, /* (0x3, 0x0, 0x2b) */
83 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS
, /* (0x3, 0x0, 0x2c) */
84 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS
, /* (0x3, 0x0, 0x2d) */
85 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS
, /* (0x3, 0x0, 0x2e) */
86 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS
, /* (0x3, 0x0, 0x2f) */
87 ILO_GPE_GEN7_3DSTATE_URB_VS
, /* (0x3, 0x0, 0x30) */
88 ILO_GPE_GEN7_3DSTATE_URB_HS
, /* (0x3, 0x0, 0x31) */
89 ILO_GPE_GEN7_3DSTATE_URB_DS
, /* (0x3, 0x0, 0x32) */
90 ILO_GPE_GEN7_3DSTATE_URB_GS
, /* (0x3, 0x0, 0x33) */
91 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE
, /* (0x3, 0x1, 0x00) */
92 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET
, /* (0x3, 0x1, 0x06) */
93 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN
, /* (0x3, 0x1, 0x07) */
94 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE
, /* (0x3, 0x1, 0x08) */
95 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS
, /* (0x3, 0x1, 0x0a) */
96 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE
, /* (0x3, 0x1, 0x0d) */
97 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS
, /* (0x3, 0x1, 0x12) */
98 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS
, /* (0x3, 0x1, 0x13) */
99 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS
, /* (0x3, 0x1, 0x14) */
100 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS
, /* (0x3, 0x1, 0x15) */
101 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS
, /* (0x3, 0x1, 0x16) */
102 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST
, /* (0x3, 0x1, 0x17) */
103 ILO_GPE_GEN7_3DSTATE_SO_BUFFER
, /* (0x3, 0x1, 0x18) */
104 ILO_GPE_GEN7_PIPE_CONTROL
, /* (0x3, 0x2, 0x00) */
105 ILO_GPE_GEN7_3DPRIMITIVE
, /* (0x3, 0x3, 0x00) */
107 ILO_GPE_GEN7_COMMAND_COUNT
,
111 * Indirect states that GEN7 GPE could emit.
113 enum ilo_gpe_gen7_state
{
114 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA
,
115 ILO_GPE_GEN7_SF_CLIP_VIEWPORT
,
116 ILO_GPE_GEN7_CC_VIEWPORT
,
117 ILO_GPE_GEN7_COLOR_CALC_STATE
,
118 ILO_GPE_GEN7_BLEND_STATE
,
119 ILO_GPE_GEN7_DEPTH_STENCIL_STATE
,
120 ILO_GPE_GEN7_SCISSOR_RECT
,
121 ILO_GPE_GEN7_BINDING_TABLE_STATE
,
122 ILO_GPE_GEN7_SURFACE_STATE
,
123 ILO_GPE_GEN7_SAMPLER_STATE
,
124 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE
,
125 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER
,
127 ILO_GPE_GEN7_STATE_COUNT
,
131 * GEN7 graphics processing engine
135 struct ilo_gpe_gen7
{
136 int (*estimate_command_size
)(const struct ilo_dev_info
*dev
,
137 enum ilo_gpe_gen7_command cmd
,
140 int (*estimate_state_size
)(const struct ilo_dev_info
*dev
,
141 enum ilo_gpe_gen7_state state
,
145 const struct ilo_gpe_gen7
*
146 ilo_gpe_gen7_get(void);
149 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info
*dev
,
152 assert(!"GPGPU_WALKER unsupported");
156 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info
*dev
,
160 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x04);
161 const uint8_t cmd_len
= 3;
163 ILO_GPE_VALID_GEN(dev
, 7, 7);
165 ilo_cp_begin(cp
, cmd_len
);
166 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
167 ilo_cp_write(cp
, clear_val
);
173 gen7_emit_3dstate_pointer(const struct ilo_dev_info
*dev
,
174 int subop
, uint32_t pointer
,
177 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, subop
);
178 const uint8_t cmd_len
= 2;
180 ILO_GPE_VALID_GEN(dev
, 7, 7);
182 ilo_cp_begin(cp
, cmd_len
);
183 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
184 ilo_cp_write(cp
, pointer
);
189 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info
*dev
,
190 uint32_t color_calc_state
,
193 gen7_emit_3dstate_pointer(dev
, 0x0e, color_calc_state
, cp
);
197 gen7_emit_3DSTATE_GS(const struct ilo_dev_info
*dev
,
198 const struct ilo_shader_state
*gs
,
202 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x11);
203 const uint8_t cmd_len
= 7;
204 const struct ilo_shader_cso
*cso
;
205 uint32_t dw2
, dw4
, dw5
;
207 ILO_GPE_VALID_GEN(dev
, 7, 7);
210 ilo_cp_begin(cp
, cmd_len
);
211 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
216 ilo_cp_write(cp
, GEN6_GS_STATISTICS_ENABLE
);
222 cso
= ilo_shader_get_kernel_cso(gs
);
223 dw2
= cso
->payload
[0];
224 dw4
= cso
->payload
[1];
225 dw5
= cso
->payload
[2];
227 dw2
|= ((num_samplers
+ 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT
;
229 ilo_cp_begin(cp
, cmd_len
);
230 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
231 ilo_cp_write(cp
, ilo_shader_get_kernel_offset(gs
));
232 ilo_cp_write(cp
, dw2
);
233 ilo_cp_write(cp
, 0); /* scratch */
234 ilo_cp_write(cp
, dw4
);
235 ilo_cp_write(cp
, dw5
);
241 gen7_emit_3DSTATE_SF(const struct ilo_dev_info
*dev
,
242 const struct ilo_rasterizer_state
*rasterizer
,
243 const struct pipe_surface
*zs_surf
,
246 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x13);
247 const uint8_t cmd_len
= 7;
248 const int num_samples
= 1;
251 ILO_GPE_VALID_GEN(dev
, 7, 7);
253 ilo_gpe_gen6_fill_3dstate_sf_raster(dev
,
254 rasterizer
, num_samples
,
255 (zs_surf
) ? zs_surf
->format
: PIPE_FORMAT_NONE
,
256 payload
, Elements(payload
));
258 ilo_cp_begin(cp
, cmd_len
);
259 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
260 ilo_cp_write_multi(cp
, payload
, 6);
265 gen7_emit_3DSTATE_WM(const struct ilo_dev_info
*dev
,
266 const struct ilo_shader_state
*fs
,
267 const struct ilo_rasterizer_state
*rasterizer
,
271 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x14);
272 const uint8_t cmd_len
= 3;
273 const int num_samples
= 1;
276 ILO_GPE_VALID_GEN(dev
, 7, 7);
278 /* see ilo_gpe_init_rasterizer_wm() */
279 dw1
= rasterizer
->wm
.payload
[0];
280 dw2
= rasterizer
->wm
.payload
[1];
282 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
285 dw1
|= GEN7_WM_DEPTH_CLEAR
;
286 dw1
|= GEN7_WM_DEPTH_RESOLVE
;
287 dw1
|= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE
;
291 const struct ilo_shader_cso
*fs_cso
= ilo_shader_get_kernel_cso(fs
);
293 dw1
|= fs_cso
->payload
[3];
297 dw1
|= GEN7_WM_DISPATCH_ENABLE
|
301 if (num_samples
> 1) {
302 dw1
|= rasterizer
->wm
.dw_msaa_rast
;
303 dw2
|= rasterizer
->wm
.dw_msaa_disp
;
306 ilo_cp_begin(cp
, cmd_len
);
307 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
308 ilo_cp_write(cp
, dw1
);
309 ilo_cp_write(cp
, dw2
);
314 gen7_emit_3dstate_constant(const struct ilo_dev_info
*dev
,
316 const uint32_t *bufs
, const int *sizes
,
320 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, subop
);
321 const uint8_t cmd_len
= 7;
323 int total_read_length
, i
;
325 ILO_GPE_VALID_GEN(dev
, 7, 7);
327 /* VS, HS, DS, GS, and PS variants */
328 assert(subop
>= 0x15 && subop
<= 0x1a && subop
!= 0x18);
330 assert(num_bufs
<= 4);
335 total_read_length
= 0;
336 for (i
= 0; i
< 4; i
++) {
340 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
342 * "Constant buffers must be enabled in order from Constant Buffer 0
343 * to Constant Buffer 3 within this command. For example, it is
344 * not allowed to enable Constant Buffer 1 by programming a
345 * non-zero value in the VS Constant Buffer 1 Read Length without a
346 * non-zero value in VS Constant Buffer 0 Read Length."
348 if (i
>= num_bufs
|| !sizes
[i
]) {
350 assert(i
>= num_bufs
|| !sizes
[i
]);
356 /* read lengths are in 256-bit units */
357 read_len
= (sizes
[i
] + 31) / 32;
358 /* the lower 5 bits are used for memory object control state */
359 assert(bufs
[i
] % 32 == 0);
361 dw
[i
/ 2] |= read_len
<< ((i
% 2) ? 16 : 0);
364 total_read_length
+= read_len
;
368 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
370 * "The sum of all four read length fields must be less than or equal
373 assert(total_read_length
<= 64);
375 ilo_cp_begin(cp
, cmd_len
);
376 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
377 ilo_cp_write_multi(cp
, dw
, 6);
382 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info
*dev
,
383 const uint32_t *bufs
, const int *sizes
,
387 gen7_emit_3dstate_constant(dev
, 0x15, bufs
, sizes
, num_bufs
, cp
);
391 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info
*dev
,
392 const uint32_t *bufs
, const int *sizes
,
396 gen7_emit_3dstate_constant(dev
, 0x16, bufs
, sizes
, num_bufs
, cp
);
400 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info
*dev
,
401 const uint32_t *bufs
, const int *sizes
,
405 gen7_emit_3dstate_constant(dev
, 0x17, bufs
, sizes
, num_bufs
, cp
);
409 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info
*dev
,
410 unsigned sample_mask
,
414 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x18);
415 const uint8_t cmd_len
= 2;
416 const unsigned valid_mask
= ((1 << num_samples
) - 1) | 0x1;
418 ILO_GPE_VALID_GEN(dev
, 7, 7);
421 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
423 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
424 * (Sample Mask) must be zero.
426 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
429 sample_mask
&= valid_mask
;
431 ilo_cp_begin(cp
, cmd_len
);
432 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
433 ilo_cp_write(cp
, sample_mask
);
438 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info
*dev
,
439 const uint32_t *bufs
, const int *sizes
,
443 gen7_emit_3dstate_constant(dev
, 0x19, bufs
, sizes
, num_bufs
, cp
);
447 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info
*dev
,
448 const uint32_t *bufs
, const int *sizes
,
452 gen7_emit_3dstate_constant(dev
, 0x1a, bufs
, sizes
, num_bufs
, cp
);
456 gen7_emit_3DSTATE_HS(const struct ilo_dev_info
*dev
,
457 const struct ilo_shader_state
*hs
,
461 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1b);
462 const uint8_t cmd_len
= 7;
464 ILO_GPE_VALID_GEN(dev
, 7, 7);
468 ilo_cp_begin(cp
, cmd_len
);
469 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
480 gen7_emit_3DSTATE_TE(const struct ilo_dev_info
*dev
,
483 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1c);
484 const uint8_t cmd_len
= 4;
486 ILO_GPE_VALID_GEN(dev
, 7, 7);
488 ilo_cp_begin(cp
, cmd_len
);
489 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
497 gen7_emit_3DSTATE_DS(const struct ilo_dev_info
*dev
,
498 const struct ilo_shader_state
*ds
,
502 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1d);
503 const uint8_t cmd_len
= 6;
505 ILO_GPE_VALID_GEN(dev
, 7, 7);
509 ilo_cp_begin(cp
, cmd_len
);
510 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
521 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info
*dev
,
522 unsigned buffer_mask
,
523 int vertex_attrib_count
,
524 bool rasterizer_discard
,
527 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1e);
528 const uint8_t cmd_len
= 3;
529 const bool enable
= (buffer_mask
!= 0);
533 ILO_GPE_VALID_GEN(dev
, 7, 7);
536 dw1
= 0 << SO_RENDER_STREAM_SELECT_SHIFT
;
537 if (rasterizer_discard
)
538 dw1
|= SO_RENDERING_DISABLE
;
542 ilo_cp_begin(cp
, cmd_len
);
543 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
544 ilo_cp_write(cp
, dw1
);
545 ilo_cp_write(cp
, dw2
);
550 read_len
= (vertex_attrib_count
+ 1) / 2;
554 dw1
= SO_FUNCTION_ENABLE
|
555 0 << SO_RENDER_STREAM_SELECT_SHIFT
|
556 SO_STATISTICS_ENABLE
|
559 if (rasterizer_discard
)
560 dw1
|= SO_RENDERING_DISABLE
;
564 dw1
|= SO_REORDER_TRAILING
;
566 dw2
= 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT
|
567 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT
|
568 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT
|
569 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT
|
570 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT
|
571 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT
|
572 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT
|
573 (read_len
- 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT
;
575 ilo_cp_begin(cp
, cmd_len
);
576 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
577 ilo_cp_write(cp
, dw1
);
578 ilo_cp_write(cp
, dw2
);
583 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info
*dev
,
584 const struct ilo_rasterizer_state
*rasterizer
,
585 const struct ilo_shader_state
*fs
,
586 const struct ilo_shader_state
*last_sh
,
589 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1f);
590 const uint8_t cmd_len
= 14;
593 ILO_GPE_VALID_GEN(dev
, 7, 7);
595 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev
, rasterizer
,
596 fs
, last_sh
, dw
, Elements(dw
));
598 ilo_cp_begin(cp
, cmd_len
);
599 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
600 ilo_cp_write_multi(cp
, dw
, 13);
605 gen7_emit_3DSTATE_PS(const struct ilo_dev_info
*dev
,
606 const struct ilo_shader_state
*fs
,
607 int num_samplers
, bool dual_blend
,
610 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x20);
611 const uint8_t cmd_len
= 8;
612 const struct ilo_shader_cso
*cso
;
613 uint32_t dw2
, dw4
, dw5
;
615 ILO_GPE_VALID_GEN(dev
, 7, 7);
618 /* see brwCreateContext() */
619 const int max_threads
= (dev
->gt
== 2) ? 172 : 48;
621 ilo_cp_begin(cp
, cmd_len
);
622 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
626 /* GPU hangs if none of the dispatch enable bits is set */
627 ilo_cp_write(cp
, (max_threads
- 1) << IVB_PS_MAX_THREADS_SHIFT
|
628 GEN7_PS_8_DISPATCH_ENABLE
);
637 cso
= ilo_shader_get_kernel_cso(fs
);
638 dw2
= cso
->payload
[0];
639 dw4
= cso
->payload
[1];
640 dw5
= cso
->payload
[2];
642 dw2
|= (num_samplers
+ 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT
;
645 dw4
|= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE
;
647 ilo_cp_begin(cp
, cmd_len
);
648 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
649 ilo_cp_write(cp
, ilo_shader_get_kernel_offset(fs
));
650 ilo_cp_write(cp
, dw2
);
651 ilo_cp_write(cp
, 0); /* scratch */
652 ilo_cp_write(cp
, dw4
);
653 ilo_cp_write(cp
, dw5
);
654 ilo_cp_write(cp
, 0); /* kernel 1 */
655 ilo_cp_write(cp
, 0); /* kernel 2 */
660 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info
*dev
,
661 uint32_t sf_clip_viewport
,
664 gen7_emit_3dstate_pointer(dev
, 0x21, sf_clip_viewport
, cp
);
668 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info
*dev
,
669 uint32_t cc_viewport
,
672 gen7_emit_3dstate_pointer(dev
, 0x23, cc_viewport
, cp
);
676 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info
*dev
,
677 uint32_t blend_state
,
680 gen7_emit_3dstate_pointer(dev
, 0x24, blend_state
, cp
);
684 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info
*dev
,
685 uint32_t depth_stencil_state
,
688 gen7_emit_3dstate_pointer(dev
, 0x25, depth_stencil_state
, cp
);
692 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info
*dev
,
693 uint32_t binding_table
,
696 gen7_emit_3dstate_pointer(dev
, 0x26, binding_table
, cp
);
700 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info
*dev
,
701 uint32_t binding_table
,
704 gen7_emit_3dstate_pointer(dev
, 0x27, binding_table
, cp
);
708 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info
*dev
,
709 uint32_t binding_table
,
712 gen7_emit_3dstate_pointer(dev
, 0x28, binding_table
, cp
);
716 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info
*dev
,
717 uint32_t binding_table
,
720 gen7_emit_3dstate_pointer(dev
, 0x29, binding_table
, cp
);
724 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info
*dev
,
725 uint32_t binding_table
,
728 gen7_emit_3dstate_pointer(dev
, 0x2a, binding_table
, cp
);
732 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info
*dev
,
733 uint32_t sampler_state
,
736 gen7_emit_3dstate_pointer(dev
, 0x2b, sampler_state
, cp
);
740 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info
*dev
,
741 uint32_t sampler_state
,
744 gen7_emit_3dstate_pointer(dev
, 0x2c, sampler_state
, cp
);
748 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info
*dev
,
749 uint32_t sampler_state
,
752 gen7_emit_3dstate_pointer(dev
, 0x2d, sampler_state
, cp
);
756 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info
*dev
,
757 uint32_t sampler_state
,
760 gen7_emit_3dstate_pointer(dev
, 0x2e, sampler_state
, cp
);
764 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info
*dev
,
765 uint32_t sampler_state
,
768 gen7_emit_3dstate_pointer(dev
, 0x2f, sampler_state
, cp
);
772 gen7_emit_3dstate_urb(const struct ilo_dev_info
*dev
,
773 int subop
, int offset
, int size
,
777 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, subop
);
778 const uint8_t cmd_len
= 2;
779 const int row_size
= 64; /* 512 bits */
780 int alloc_size
, num_entries
, min_entries
, max_entries
;
782 ILO_GPE_VALID_GEN(dev
, 7, 7);
784 /* VS, HS, DS, and GS variants */
785 assert(subop
>= 0x30 && subop
<= 0x33);
787 /* in multiples of 8KB */
788 assert(offset
% 8192 == 0);
791 /* in multiple of 512-bit rows */
792 alloc_size
= (entry_size
+ row_size
- 1) / row_size
;
797 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
799 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
800 * cause performance to decrease due to banking in the URB. Element
801 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
803 if (subop
== 0x30 && alloc_size
== 5)
806 /* in multiples of 8 */
807 num_entries
= (size
/ row_size
/ alloc_size
) & ~7;
810 case 0x30: /* 3DSTATE_URB_VS */
812 max_entries
= (dev
->gt
== 2) ? 704 : 512;
814 assert(num_entries
>= min_entries
);
815 if (num_entries
> max_entries
)
816 num_entries
= max_entries
;
818 case 0x31: /* 3DSTATE_URB_HS */
819 max_entries
= (dev
->gt
== 2) ? 64 : 32;
820 if (num_entries
> max_entries
)
821 num_entries
= max_entries
;
823 case 0x32: /* 3DSTATE_URB_DS */
825 assert(num_entries
>= 138);
827 case 0x33: /* 3DSTATE_URB_GS */
828 max_entries
= (dev
->gt
== 2) ? 320 : 192;
829 if (num_entries
> max_entries
)
830 num_entries
= max_entries
;
836 ilo_cp_begin(cp
, cmd_len
);
837 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
838 ilo_cp_write(cp
, offset
<< GEN7_URB_STARTING_ADDRESS_SHIFT
|
839 (alloc_size
- 1) << GEN7_URB_ENTRY_SIZE_SHIFT
|
845 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info
*dev
,
846 int offset
, int size
, int entry_size
,
849 gen7_emit_3dstate_urb(dev
, 0x30, offset
, size
, entry_size
, cp
);
853 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info
*dev
,
854 int offset
, int size
, int entry_size
,
857 gen7_emit_3dstate_urb(dev
, 0x31, offset
, size
, entry_size
, cp
);
861 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info
*dev
,
862 int offset
, int size
, int entry_size
,
865 gen7_emit_3dstate_urb(dev
, 0x32, offset
, size
, entry_size
, cp
);
869 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info
*dev
,
870 int offset
, int size
, int entry_size
,
873 gen7_emit_3dstate_urb(dev
, 0x33, offset
, size
, entry_size
, cp
);
877 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info
*dev
,
878 int subop
, int offset
, int size
,
881 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x1, subop
);
882 const uint8_t cmd_len
= 2;
885 ILO_GPE_VALID_GEN(dev
, 7, 7);
887 /* VS, HS, DS, GS, and PS variants */
888 assert(subop
>= 0x12 && subop
<= 0x16);
891 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
893 * "(A table that says the maximum size of each constant buffer is
896 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
898 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
899 * may not exceed the maximum value of the Constant Buffer Size."
901 * Thus, the valid range of buffer end is [0KB, 16KB].
903 end
= (offset
+ size
) / 1024;
905 assert(!"invalid constant buffer end");
909 /* the valid range of buffer offset is [0KB, 15KB] */
910 offset
= (offset
+ 1023) / 1024;
912 assert(!"invalid constant buffer offset");
921 /* the valid range of buffer size is [0KB, 15KB] */
924 assert(!"invalid constant buffer size");
928 ilo_cp_begin(cp
, cmd_len
);
929 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
930 ilo_cp_write(cp
, offset
<< GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT
|
936 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info
*dev
,
937 int offset
, int size
,
940 gen7_emit_3dstate_push_constant_alloc(dev
, 0x12, offset
, size
, cp
);
944 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info
*dev
,
945 int offset
, int size
,
948 gen7_emit_3dstate_push_constant_alloc(dev
, 0x13, offset
, size
, cp
);
952 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info
*dev
,
953 int offset
, int size
,
956 gen7_emit_3dstate_push_constant_alloc(dev
, 0x14, offset
, size
, cp
);
960 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info
*dev
,
961 int offset
, int size
,
964 gen7_emit_3dstate_push_constant_alloc(dev
, 0x15, offset
, size
, cp
);
968 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info
*dev
,
969 int offset
, int size
,
972 gen7_emit_3dstate_push_constant_alloc(dev
, 0x16, offset
, size
, cp
);
976 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info
*dev
,
977 const struct pipe_stream_output_info
*so_info
,
980 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x1, 0x17);
982 int buffer_selects
, num_entries
, i
;
983 uint16_t so_decls
[128];
985 ILO_GPE_VALID_GEN(dev
, 7, 7);
991 int buffer_offsets
[PIPE_MAX_SO_BUFFERS
];
993 memset(buffer_offsets
, 0, sizeof(buffer_offsets
));
995 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
996 unsigned decl
, buf
, reg
, mask
;
998 buf
= so_info
->output
[i
].output_buffer
;
1000 /* pad with holes */
1001 assert(buffer_offsets
[buf
] <= so_info
->output
[i
].dst_offset
);
1002 while (buffer_offsets
[buf
] < so_info
->output
[i
].dst_offset
) {
1005 num_dwords
= so_info
->output
[i
].dst_offset
- buffer_offsets
[buf
];
1009 decl
= buf
<< SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT
|
1011 ((1 << num_dwords
) - 1) << SO_DECL_COMPONENT_MASK_SHIFT
;
1013 so_decls
[num_entries
++] = decl
;
1014 buffer_offsets
[buf
] += num_dwords
;
1017 reg
= so_info
->output
[i
].register_index
;
1018 mask
= ((1 << so_info
->output
[i
].num_components
) - 1) <<
1019 so_info
->output
[i
].start_component
;
1021 decl
= buf
<< SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT
|
1022 reg
<< SO_DECL_REGISTER_INDEX_SHIFT
|
1023 mask
<< SO_DECL_COMPONENT_MASK_SHIFT
;
1025 so_decls
[num_entries
++] = decl
;
1026 buffer_selects
|= 1 << buf
;
1027 buffer_offsets
[buf
] += so_info
->output
[i
].num_components
;
1032 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1034 * "Errata: All 128 decls for all four streams must be included
1035 * whenever this command is issued. The "Num Entries [n]" fields still
1036 * contain the actual numbers of valid decls."
1038 * Also note that "DWord Length" has 9 bits for this command, and the type
1039 * of cmd_len is thus uint16_t.
1041 cmd_len
= 2 * 128 + 3;
1043 ilo_cp_begin(cp
, cmd_len
);
1044 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1045 ilo_cp_write(cp
, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT
|
1046 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT
|
1047 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT
|
1048 buffer_selects
<< SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT
);
1049 ilo_cp_write(cp
, 0 << SO_NUM_ENTRIES_3_SHIFT
|
1050 0 << SO_NUM_ENTRIES_2_SHIFT
|
1051 0 << SO_NUM_ENTRIES_1_SHIFT
|
1052 num_entries
<< SO_NUM_ENTRIES_0_SHIFT
);
1054 for (i
= 0; i
< num_entries
; i
++) {
1055 ilo_cp_write(cp
, so_decls
[i
]);
1056 ilo_cp_write(cp
, 0);
1058 for (; i
< 128; i
++) {
1059 ilo_cp_write(cp
, 0);
1060 ilo_cp_write(cp
, 0);
1067 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info
*dev
,
1068 int index
, int base
, int stride
,
1069 const struct pipe_stream_output_target
*so_target
,
1072 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x1, 0x18);
1073 const uint8_t cmd_len
= 4;
1074 struct ilo_buffer
*buf
;
1077 ILO_GPE_VALID_GEN(dev
, 7, 7);
1079 if (!so_target
|| !so_target
->buffer
) {
1080 ilo_cp_begin(cp
, cmd_len
);
1081 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1082 ilo_cp_write(cp
, index
<< SO_BUFFER_INDEX_SHIFT
);
1083 ilo_cp_write(cp
, 0);
1084 ilo_cp_write(cp
, 0);
1089 buf
= ilo_buffer(so_target
->buffer
);
1092 assert(stride
% 4 == 0 && base
% 4 == 0);
1093 assert(so_target
->buffer_offset
% 4 == 0);
1096 base
= (base
+ so_target
->buffer_offset
) & ~3;
1097 end
= (base
+ so_target
->buffer_size
) & ~3;
1099 ilo_cp_begin(cp
, cmd_len
);
1100 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1101 ilo_cp_write(cp
, index
<< SO_BUFFER_INDEX_SHIFT
|
1103 ilo_cp_write_bo(cp
, base
, buf
->bo
, INTEL_DOMAIN_RENDER
, INTEL_DOMAIN_RENDER
);
1104 ilo_cp_write_bo(cp
, end
, buf
->bo
, INTEL_DOMAIN_RENDER
, INTEL_DOMAIN_RENDER
);
1109 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info
*dev
,
1110 const struct pipe_draw_info
*info
,
1111 const struct ilo_ib_state
*ib
,
1115 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x3, 0x00);
1116 const uint8_t cmd_len
= 7;
1117 const int prim
= (rectlist
) ?
1118 _3DPRIM_RECTLIST
: ilo_gpe_gen6_translate_pipe_prim(info
->mode
);
1119 const int vb_access
= (info
->indexed
) ?
1120 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
1121 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
1122 const uint32_t vb_start
= info
->start
+
1123 ((info
->indexed
) ? ib
->draw_start_offset
: 0);
1125 ILO_GPE_VALID_GEN(dev
, 7, 7);
1127 ilo_cp_begin(cp
, cmd_len
);
1128 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1129 ilo_cp_write(cp
, vb_access
| prim
);
1130 ilo_cp_write(cp
, info
->count
);
1131 ilo_cp_write(cp
, vb_start
);
1132 ilo_cp_write(cp
, info
->instance_count
);
1133 ilo_cp_write(cp
, info
->start_instance
);
1134 ilo_cp_write(cp
, info
->index_bias
);
1138 static inline uint32_t
1139 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info
*dev
,
1140 const struct ilo_viewport_cso
*viewports
,
1141 unsigned num_viewports
,
1144 const int state_align
= 64 / 4;
1145 const int state_len
= 16 * num_viewports
;
1146 uint32_t state_offset
, *dw
;
1149 ILO_GPE_VALID_GEN(dev
, 7, 7);
1152 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1154 * "The viewport-specific state used by both the SF and CL units
1155 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1156 * of which contains the DWords described below. The start of each
1157 * element is spaced 16 DWords apart. The location of first element of
1158 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1159 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1161 assert(num_viewports
&& num_viewports
<= 16);
1163 dw
= ilo_cp_steal_ptr(cp
, "SF_CLIP_VIEWPORT",
1164 state_len
, state_align
, &state_offset
);
1166 for (i
= 0; i
< num_viewports
; i
++) {
1167 const struct ilo_viewport_cso
*vp
= &viewports
[i
];
1169 dw
[0] = fui(vp
->m00
);
1170 dw
[1] = fui(vp
->m11
);
1171 dw
[2] = fui(vp
->m22
);
1172 dw
[3] = fui(vp
->m30
);
1173 dw
[4] = fui(vp
->m31
);
1174 dw
[5] = fui(vp
->m32
);
1177 dw
[8] = fui(vp
->min_gbx
);
1178 dw
[9] = fui(vp
->max_gbx
);
1179 dw
[10] = fui(vp
->min_gby
);
1180 dw
[11] = fui(vp
->max_gby
);
1189 return state_offset
;
1192 #endif /* ILO_GPE_GEN7_H */