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ilo: preliminary GEN 7.5 support
[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "intel_winsys.h"
32
33 #include "ilo_common.h"
34 #include "ilo_cp.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_gpe_gen6.h"
38
39 /**
40 * Commands that GEN7 GPE could emit.
41 */
42 enum ilo_gpe_gen7_command {
43 ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
44 ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
45 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
46 ILO_GPE_GEN7_PIPELINE_SELECT, /* (0x1, 0x1, 0x04) */
47 ILO_GPE_GEN7_MEDIA_VFE_STATE, /* (0x2, 0x0, 0x00) */
48 ILO_GPE_GEN7_MEDIA_CURBE_LOAD, /* (0x2, 0x0, 0x01) */
49 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD, /* (0x2, 0x0, 0x02) */
50 ILO_GPE_GEN7_MEDIA_STATE_FLUSH, /* (0x2, 0x0, 0x04) */
51 ILO_GPE_GEN7_GPGPU_WALKER, /* (0x2, 0x1, 0x05) */
52 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS, /* (0x3, 0x0, 0x04) */
53 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER, /* (0x3, 0x0, 0x05) */
54 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER, /* (0x3, 0x0, 0x06) */
55 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER, /* (0x3, 0x0, 0x07) */
56 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS, /* (0x3, 0x0, 0x08) */
57 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS, /* (0x3, 0x0, 0x09) */
58 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER, /* (0x3, 0x0, 0x0a) */
59 ILO_GPE_GEN7_3DSTATE_VF, /* (0x3, 0x0, 0x0c) */
60 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS, /* (0x3, 0x0, 0x0e) */
61 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS, /* (0x3, 0x0, 0x0f) */
62 ILO_GPE_GEN7_3DSTATE_VS, /* (0x3, 0x0, 0x10) */
63 ILO_GPE_GEN7_3DSTATE_GS, /* (0x3, 0x0, 0x11) */
64 ILO_GPE_GEN7_3DSTATE_CLIP, /* (0x3, 0x0, 0x12) */
65 ILO_GPE_GEN7_3DSTATE_SF, /* (0x3, 0x0, 0x13) */
66 ILO_GPE_GEN7_3DSTATE_WM, /* (0x3, 0x0, 0x14) */
67 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS, /* (0x3, 0x0, 0x15) */
68 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS, /* (0x3, 0x0, 0x16) */
69 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS, /* (0x3, 0x0, 0x17) */
70 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK, /* (0x3, 0x0, 0x18) */
71 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS, /* (0x3, 0x0, 0x19) */
72 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS, /* (0x3, 0x0, 0x1a) */
73 ILO_GPE_GEN7_3DSTATE_HS, /* (0x3, 0x0, 0x1b) */
74 ILO_GPE_GEN7_3DSTATE_TE, /* (0x3, 0x0, 0x1c) */
75 ILO_GPE_GEN7_3DSTATE_DS, /* (0x3, 0x0, 0x1d) */
76 ILO_GPE_GEN7_3DSTATE_STREAMOUT, /* (0x3, 0x0, 0x1e) */
77 ILO_GPE_GEN7_3DSTATE_SBE, /* (0x3, 0x0, 0x1f) */
78 ILO_GPE_GEN7_3DSTATE_PS, /* (0x3, 0x0, 0x20) */
79 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, /* (0x3, 0x0, 0x21) */
80 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC, /* (0x3, 0x0, 0x23) */
81 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS, /* (0x3, 0x0, 0x24) */
82 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, /* (0x3, 0x0, 0x25) */
83 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, /* (0x3, 0x0, 0x26) */
84 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, /* (0x3, 0x0, 0x27) */
85 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, /* (0x3, 0x0, 0x28) */
86 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, /* (0x3, 0x0, 0x29) */
87 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, /* (0x3, 0x0, 0x2a) */
88 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, /* (0x3, 0x0, 0x2b) */
89 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, /* (0x3, 0x0, 0x2c) */
90 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, /* (0x3, 0x0, 0x2d) */
91 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, /* (0x3, 0x0, 0x2e) */
92 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, /* (0x3, 0x0, 0x2f) */
93 ILO_GPE_GEN7_3DSTATE_URB_VS, /* (0x3, 0x0, 0x30) */
94 ILO_GPE_GEN7_3DSTATE_URB_HS, /* (0x3, 0x0, 0x31) */
95 ILO_GPE_GEN7_3DSTATE_URB_DS, /* (0x3, 0x0, 0x32) */
96 ILO_GPE_GEN7_3DSTATE_URB_GS, /* (0x3, 0x0, 0x33) */
97 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE, /* (0x3, 0x1, 0x00) */
98 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET, /* (0x3, 0x1, 0x06) */
99 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN, /* (0x3, 0x1, 0x07) */
100 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE, /* (0x3, 0x1, 0x08) */
101 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS, /* (0x3, 0x1, 0x0a) */
102 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE, /* (0x3, 0x1, 0x0d) */
103 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, /* (0x3, 0x1, 0x12) */
104 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, /* (0x3, 0x1, 0x13) */
105 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, /* (0x3, 0x1, 0x14) */
106 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, /* (0x3, 0x1, 0x15) */
107 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, /* (0x3, 0x1, 0x16) */
108 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST, /* (0x3, 0x1, 0x17) */
109 ILO_GPE_GEN7_3DSTATE_SO_BUFFER, /* (0x3, 0x1, 0x18) */
110 ILO_GPE_GEN7_PIPE_CONTROL, /* (0x3, 0x2, 0x00) */
111 ILO_GPE_GEN7_3DPRIMITIVE, /* (0x3, 0x3, 0x00) */
112
113 ILO_GPE_GEN7_COMMAND_COUNT,
114 };
115
116 /**
117 * Indirect states that GEN7 GPE could emit.
118 */
119 enum ilo_gpe_gen7_state {
120 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA,
121 ILO_GPE_GEN7_SF_CLIP_VIEWPORT,
122 ILO_GPE_GEN7_CC_VIEWPORT,
123 ILO_GPE_GEN7_COLOR_CALC_STATE,
124 ILO_GPE_GEN7_BLEND_STATE,
125 ILO_GPE_GEN7_DEPTH_STENCIL_STATE,
126 ILO_GPE_GEN7_SCISSOR_RECT,
127 ILO_GPE_GEN7_BINDING_TABLE_STATE,
128 ILO_GPE_GEN7_SURFACE_STATE,
129 ILO_GPE_GEN7_SAMPLER_STATE,
130 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE,
131 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER,
132
133 ILO_GPE_GEN7_STATE_COUNT,
134 };
135
136 int
137 ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
138 enum ilo_gpe_gen7_command cmd,
139 int arg);
140
141 int
142 ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev,
143 enum ilo_gpe_gen7_state state,
144 int arg);
145
146 static inline void
147 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
148 struct ilo_cp *cp)
149 {
150 assert(!"GPGPU_WALKER unsupported");
151 }
152
153 static inline void
154 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
155 uint32_t clear_val,
156 struct ilo_cp *cp)
157 {
158 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
159 const uint8_t cmd_len = 3;
160
161 ILO_GPE_VALID_GEN(dev, 7, 7.5);
162
163 ilo_cp_begin(cp, cmd_len);
164 ilo_cp_write(cp, cmd | (cmd_len - 2));
165 ilo_cp_write(cp, clear_val);
166 ilo_cp_write(cp, 1);
167 ilo_cp_end(cp);
168 }
169
170 static inline void
171 gen7_emit_3DSTATE_VF(const struct ilo_dev_info *dev,
172 bool enable_cut_index,
173 uint32_t cut_index,
174 struct ilo_cp *cp)
175 {
176 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0c);
177 const uint8_t cmd_len = 2;
178
179 ILO_GPE_VALID_GEN(dev, 7.5, 7.5);
180
181 ilo_cp_begin(cp, cmd_len);
182 ilo_cp_write(cp, cmd | (cmd_len - 2) |
183 ((enable_cut_index) ? HSW_CUT_INDEX_ENABLE : 0));
184 ilo_cp_write(cp, cut_index);
185 ilo_cp_end(cp);
186 }
187
188 static inline void
189 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
190 int subop, uint32_t pointer,
191 struct ilo_cp *cp)
192 {
193 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
194 const uint8_t cmd_len = 2;
195
196 ILO_GPE_VALID_GEN(dev, 7, 7.5);
197
198 ilo_cp_begin(cp, cmd_len);
199 ilo_cp_write(cp, cmd | (cmd_len - 2));
200 ilo_cp_write(cp, pointer);
201 ilo_cp_end(cp);
202 }
203
204 static inline void
205 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
206 uint32_t color_calc_state,
207 struct ilo_cp *cp)
208 {
209 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
210 }
211
212 static inline void
213 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
214 const struct ilo_shader_state *gs,
215 int num_samplers,
216 struct ilo_cp *cp)
217 {
218 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
219 const uint8_t cmd_len = 7;
220 const struct ilo_shader_cso *cso;
221 uint32_t dw2, dw4, dw5;
222
223 ILO_GPE_VALID_GEN(dev, 7, 7.5);
224
225 if (!gs) {
226 ilo_cp_begin(cp, cmd_len);
227 ilo_cp_write(cp, cmd | (cmd_len - 2));
228 ilo_cp_write(cp, 0);
229 ilo_cp_write(cp, 0);
230 ilo_cp_write(cp, 0);
231 ilo_cp_write(cp, 0);
232 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
233 ilo_cp_write(cp, 0);
234 ilo_cp_end(cp);
235 return;
236 }
237
238 cso = ilo_shader_get_kernel_cso(gs);
239 dw2 = cso->payload[0];
240 dw4 = cso->payload[1];
241 dw5 = cso->payload[2];
242
243 dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
244
245 ilo_cp_begin(cp, cmd_len);
246 ilo_cp_write(cp, cmd | (cmd_len - 2));
247 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
248 ilo_cp_write(cp, dw2);
249 ilo_cp_write(cp, 0); /* scratch */
250 ilo_cp_write(cp, dw4);
251 ilo_cp_write(cp, dw5);
252 ilo_cp_write(cp, 0);
253 ilo_cp_end(cp);
254 }
255
256 static inline void
257 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
258 const struct ilo_rasterizer_state *rasterizer,
259 const struct pipe_surface *zs_surf,
260 struct ilo_cp *cp)
261 {
262 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
263 const uint8_t cmd_len = 7;
264 const int num_samples = 1;
265 uint32_t payload[6];
266
267 ILO_GPE_VALID_GEN(dev, 7, 7.5);
268
269 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
270 rasterizer, num_samples,
271 (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE,
272 payload, Elements(payload));
273
274 ilo_cp_begin(cp, cmd_len);
275 ilo_cp_write(cp, cmd | (cmd_len - 2));
276 ilo_cp_write_multi(cp, payload, 6);
277 ilo_cp_end(cp);
278 }
279
280 static inline void
281 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
282 const struct ilo_shader_state *fs,
283 const struct ilo_rasterizer_state *rasterizer,
284 bool cc_may_kill,
285 struct ilo_cp *cp)
286 {
287 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
288 const uint8_t cmd_len = 3;
289 const int num_samples = 1;
290 uint32_t dw1, dw2;
291
292 ILO_GPE_VALID_GEN(dev, 7, 7.5);
293
294 /* see ilo_gpe_init_rasterizer_wm() */
295 dw1 = rasterizer->wm.payload[0];
296 dw2 = rasterizer->wm.payload[1];
297
298 dw1 |= GEN7_WM_STATISTICS_ENABLE;
299
300 if (false) {
301 dw1 |= GEN7_WM_DEPTH_CLEAR;
302 dw1 |= GEN7_WM_DEPTH_RESOLVE;
303 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
304 }
305
306 if (fs) {
307 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
308
309 dw1 |= fs_cso->payload[3];
310 }
311
312 if (cc_may_kill) {
313 dw1 |= GEN7_WM_DISPATCH_ENABLE |
314 GEN7_WM_KILL_ENABLE;
315 }
316
317 if (num_samples > 1) {
318 dw1 |= rasterizer->wm.dw_msaa_rast;
319 dw2 |= rasterizer->wm.dw_msaa_disp;
320 }
321
322 ilo_cp_begin(cp, cmd_len);
323 ilo_cp_write(cp, cmd | (cmd_len - 2));
324 ilo_cp_write(cp, dw1);
325 ilo_cp_write(cp, dw2);
326 ilo_cp_end(cp);
327 }
328
329 static inline void
330 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
331 int subop,
332 const uint32_t *bufs, const int *sizes,
333 int num_bufs,
334 struct ilo_cp *cp)
335 {
336 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
337 const uint8_t cmd_len = 7;
338 uint32_t dw[6];
339 int total_read_length, i;
340
341 ILO_GPE_VALID_GEN(dev, 7, 7.5);
342
343 /* VS, HS, DS, GS, and PS variants */
344 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
345
346 assert(num_bufs <= 4);
347
348 dw[0] = 0;
349 dw[1] = 0;
350
351 total_read_length = 0;
352 for (i = 0; i < 4; i++) {
353 int read_len;
354
355 /*
356 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
357 *
358 * "Constant buffers must be enabled in order from Constant Buffer 0
359 * to Constant Buffer 3 within this command. For example, it is
360 * not allowed to enable Constant Buffer 1 by programming a
361 * non-zero value in the VS Constant Buffer 1 Read Length without a
362 * non-zero value in VS Constant Buffer 0 Read Length."
363 */
364 if (i >= num_bufs || !sizes[i]) {
365 for (; i < 4; i++) {
366 assert(i >= num_bufs || !sizes[i]);
367 dw[2 + i] = 0;
368 }
369 break;
370 }
371
372 /* read lengths are in 256-bit units */
373 read_len = (sizes[i] + 31) / 32;
374 /* the lower 5 bits are used for memory object control state */
375 assert(bufs[i] % 32 == 0);
376
377 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
378 dw[2 + i] = bufs[i];
379
380 total_read_length += read_len;
381 }
382
383 /*
384 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
385 *
386 * "The sum of all four read length fields must be less than or equal
387 * to the size of 64"
388 */
389 assert(total_read_length <= 64);
390
391 ilo_cp_begin(cp, cmd_len);
392 ilo_cp_write(cp, cmd | (cmd_len - 2));
393 ilo_cp_write_multi(cp, dw, 6);
394 ilo_cp_end(cp);
395 }
396
397 static inline void
398 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
399 const uint32_t *bufs, const int *sizes,
400 int num_bufs,
401 struct ilo_cp *cp)
402 {
403 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
404 }
405
406 static inline void
407 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
408 const uint32_t *bufs, const int *sizes,
409 int num_bufs,
410 struct ilo_cp *cp)
411 {
412 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
413 }
414
415 static inline void
416 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
417 const uint32_t *bufs, const int *sizes,
418 int num_bufs,
419 struct ilo_cp *cp)
420 {
421 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
422 }
423
424 static inline void
425 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
426 unsigned sample_mask,
427 int num_samples,
428 struct ilo_cp *cp)
429 {
430 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
431 const uint8_t cmd_len = 2;
432 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
433
434 ILO_GPE_VALID_GEN(dev, 7, 7.5);
435
436 /*
437 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
438 *
439 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
440 * (Sample Mask) must be zero.
441 *
442 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
443 * must be zero."
444 */
445 sample_mask &= valid_mask;
446
447 ilo_cp_begin(cp, cmd_len);
448 ilo_cp_write(cp, cmd | (cmd_len - 2));
449 ilo_cp_write(cp, sample_mask);
450 ilo_cp_end(cp);
451 }
452
453 static inline void
454 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
455 const uint32_t *bufs, const int *sizes,
456 int num_bufs,
457 struct ilo_cp *cp)
458 {
459 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
460 }
461
462 static inline void
463 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
464 const uint32_t *bufs, const int *sizes,
465 int num_bufs,
466 struct ilo_cp *cp)
467 {
468 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
469 }
470
471 static inline void
472 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
473 const struct ilo_shader_state *hs,
474 int num_samplers,
475 struct ilo_cp *cp)
476 {
477 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
478 const uint8_t cmd_len = 7;
479
480 ILO_GPE_VALID_GEN(dev, 7, 7.5);
481
482 assert(!hs);
483
484 ilo_cp_begin(cp, cmd_len);
485 ilo_cp_write(cp, cmd | (cmd_len - 2));
486 ilo_cp_write(cp, 0);
487 ilo_cp_write(cp, 0);
488 ilo_cp_write(cp, 0);
489 ilo_cp_write(cp, 0);
490 ilo_cp_write(cp, 0);
491 ilo_cp_write(cp, 0);
492 ilo_cp_end(cp);
493 }
494
495 static inline void
496 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
497 struct ilo_cp *cp)
498 {
499 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
500 const uint8_t cmd_len = 4;
501
502 ILO_GPE_VALID_GEN(dev, 7, 7.5);
503
504 ilo_cp_begin(cp, cmd_len);
505 ilo_cp_write(cp, cmd | (cmd_len - 2));
506 ilo_cp_write(cp, 0);
507 ilo_cp_write(cp, 0);
508 ilo_cp_write(cp, 0);
509 ilo_cp_end(cp);
510 }
511
512 static inline void
513 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
514 const struct ilo_shader_state *ds,
515 int num_samplers,
516 struct ilo_cp *cp)
517 {
518 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
519 const uint8_t cmd_len = 6;
520
521 ILO_GPE_VALID_GEN(dev, 7, 7.5);
522
523 assert(!ds);
524
525 ilo_cp_begin(cp, cmd_len);
526 ilo_cp_write(cp, cmd | (cmd_len - 2));
527 ilo_cp_write(cp, 0);
528 ilo_cp_write(cp, 0);
529 ilo_cp_write(cp, 0);
530 ilo_cp_write(cp, 0);
531 ilo_cp_write(cp, 0);
532 ilo_cp_end(cp);
533
534 }
535
536 static inline void
537 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
538 unsigned buffer_mask,
539 int vertex_attrib_count,
540 bool rasterizer_discard,
541 struct ilo_cp *cp)
542 {
543 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
544 const uint8_t cmd_len = 3;
545 const bool enable = (buffer_mask != 0);
546 uint32_t dw1, dw2;
547 int read_len;
548
549 ILO_GPE_VALID_GEN(dev, 7, 7.5);
550
551 if (!enable) {
552 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
553 if (rasterizer_discard)
554 dw1 |= SO_RENDERING_DISABLE;
555
556 dw2 = 0;
557
558 ilo_cp_begin(cp, cmd_len);
559 ilo_cp_write(cp, cmd | (cmd_len - 2));
560 ilo_cp_write(cp, dw1);
561 ilo_cp_write(cp, dw2);
562 ilo_cp_end(cp);
563 return;
564 }
565
566 read_len = (vertex_attrib_count + 1) / 2;
567 if (!read_len)
568 read_len = 1;
569
570 dw1 = SO_FUNCTION_ENABLE |
571 0 << SO_RENDER_STREAM_SELECT_SHIFT |
572 SO_STATISTICS_ENABLE |
573 buffer_mask << 8;
574
575 if (rasterizer_discard)
576 dw1 |= SO_RENDERING_DISABLE;
577
578 /* API_OPENGL */
579 if (true)
580 dw1 |= SO_REORDER_TRAILING;
581
582 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
583 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
584 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
585 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
586 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
587 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
588 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
589 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
590
591 ilo_cp_begin(cp, cmd_len);
592 ilo_cp_write(cp, cmd | (cmd_len - 2));
593 ilo_cp_write(cp, dw1);
594 ilo_cp_write(cp, dw2);
595 ilo_cp_end(cp);
596 }
597
598 static inline void
599 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
600 const struct ilo_rasterizer_state *rasterizer,
601 const struct ilo_shader_state *fs,
602 struct ilo_cp *cp)
603 {
604 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
605 const uint8_t cmd_len = 14;
606 uint32_t dw[13];
607
608 ILO_GPE_VALID_GEN(dev, 7, 7.5);
609
610 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer, fs, dw, Elements(dw));
611
612 ilo_cp_begin(cp, cmd_len);
613 ilo_cp_write(cp, cmd | (cmd_len - 2));
614 ilo_cp_write_multi(cp, dw, 13);
615 ilo_cp_end(cp);
616 }
617
618 static inline void
619 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
620 const struct ilo_shader_state *fs,
621 int num_samplers, bool dual_blend,
622 struct ilo_cp *cp)
623 {
624 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
625 const uint8_t cmd_len = 8;
626 const struct ilo_shader_cso *cso;
627 uint32_t dw2, dw4, dw5;
628
629 ILO_GPE_VALID_GEN(dev, 7, 7.5);
630
631 if (!fs) {
632 int max_threads;
633
634 /* GPU hangs if none of the dispatch enable bits is set */
635 dw4 = GEN7_PS_8_DISPATCH_ENABLE;
636
637 /* see brwCreateContext() */
638 switch (dev->gen) {
639 case ILO_GEN(7.5):
640 max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
641 dw4 |= max_threads << HSW_PS_MAX_THREADS_SHIFT;
642 break;
643 case ILO_GEN(7):
644 default:
645 max_threads = (dev->gt == 2) ? 172 : 48;
646 dw4 |= max_threads << IVB_PS_MAX_THREADS_SHIFT;
647 break;
648 }
649
650 ilo_cp_begin(cp, cmd_len);
651 ilo_cp_write(cp, cmd | (cmd_len - 2));
652 ilo_cp_write(cp, 0);
653 ilo_cp_write(cp, 0);
654 ilo_cp_write(cp, 0);
655 ilo_cp_write(cp, dw4);
656 ilo_cp_write(cp, 0);
657 ilo_cp_write(cp, 0);
658 ilo_cp_write(cp, 0);
659 ilo_cp_end(cp);
660
661 return;
662 }
663
664 cso = ilo_shader_get_kernel_cso(fs);
665 dw2 = cso->payload[0];
666 dw4 = cso->payload[1];
667 dw5 = cso->payload[2];
668
669 dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT;
670
671 if (dual_blend)
672 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
673
674 ilo_cp_begin(cp, cmd_len);
675 ilo_cp_write(cp, cmd | (cmd_len - 2));
676 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
677 ilo_cp_write(cp, dw2);
678 ilo_cp_write(cp, 0); /* scratch */
679 ilo_cp_write(cp, dw4);
680 ilo_cp_write(cp, dw5);
681 ilo_cp_write(cp, 0); /* kernel 1 */
682 ilo_cp_write(cp, 0); /* kernel 2 */
683 ilo_cp_end(cp);
684 }
685
686 static inline void
687 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
688 uint32_t sf_clip_viewport,
689 struct ilo_cp *cp)
690 {
691 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
692 }
693
694 static inline void
695 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
696 uint32_t cc_viewport,
697 struct ilo_cp *cp)
698 {
699 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
700 }
701
702 static inline void
703 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
704 uint32_t blend_state,
705 struct ilo_cp *cp)
706 {
707 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
708 }
709
710 static inline void
711 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
712 uint32_t depth_stencil_state,
713 struct ilo_cp *cp)
714 {
715 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
716 }
717
718 static inline void
719 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
720 uint32_t binding_table,
721 struct ilo_cp *cp)
722 {
723 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
724 }
725
726 static inline void
727 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
728 uint32_t binding_table,
729 struct ilo_cp *cp)
730 {
731 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
732 }
733
734 static inline void
735 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
736 uint32_t binding_table,
737 struct ilo_cp *cp)
738 {
739 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
740 }
741
742 static inline void
743 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
744 uint32_t binding_table,
745 struct ilo_cp *cp)
746 {
747 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
748 }
749
750 static inline void
751 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
752 uint32_t binding_table,
753 struct ilo_cp *cp)
754 {
755 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
756 }
757
758 static inline void
759 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
760 uint32_t sampler_state,
761 struct ilo_cp *cp)
762 {
763 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
764 }
765
766 static inline void
767 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
768 uint32_t sampler_state,
769 struct ilo_cp *cp)
770 {
771 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
772 }
773
774 static inline void
775 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
776 uint32_t sampler_state,
777 struct ilo_cp *cp)
778 {
779 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
780 }
781
782 static inline void
783 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
784 uint32_t sampler_state,
785 struct ilo_cp *cp)
786 {
787 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
788 }
789
790 static inline void
791 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
792 uint32_t sampler_state,
793 struct ilo_cp *cp)
794 {
795 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
796 }
797
798 static inline void
799 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
800 int subop, int offset, int size,
801 int entry_size,
802 struct ilo_cp *cp)
803 {
804 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
805 const uint8_t cmd_len = 2;
806 const int row_size = 64; /* 512 bits */
807 int alloc_size, num_entries, min_entries, max_entries;
808
809 ILO_GPE_VALID_GEN(dev, 7, 7.5);
810
811 /* VS, HS, DS, and GS variants */
812 assert(subop >= 0x30 && subop <= 0x33);
813
814 /* in multiples of 8KB */
815 assert(offset % 8192 == 0);
816 offset /= 8192;
817
818 /* in multiple of 512-bit rows */
819 alloc_size = (entry_size + row_size - 1) / row_size;
820 if (!alloc_size)
821 alloc_size = 1;
822
823 /*
824 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
825 *
826 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
827 * cause performance to decrease due to banking in the URB. Element
828 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
829 */
830 if (subop == 0x30 && alloc_size == 5)
831 alloc_size = 6;
832
833 /* in multiples of 8 */
834 num_entries = (size / row_size / alloc_size) & ~7;
835
836 switch (subop) {
837 case 0x30: /* 3DSTATE_URB_VS */
838 min_entries = 32;
839
840 switch (dev->gen) {
841 case ILO_GEN(7.5):
842 max_entries = (dev->gt >= 2) ? 1644 : 640;
843 break;
844 case ILO_GEN(7):
845 default:
846 max_entries = (dev->gt == 2) ? 704 : 512;
847 break;
848 }
849
850 assert(num_entries >= min_entries);
851 if (num_entries > max_entries)
852 num_entries = max_entries;
853 break;
854 case 0x31: /* 3DSTATE_URB_HS */
855 max_entries = (dev->gt == 2) ? 64 : 32;
856 if (num_entries > max_entries)
857 num_entries = max_entries;
858 break;
859 case 0x32: /* 3DSTATE_URB_DS */
860 if (num_entries)
861 assert(num_entries >= 138);
862 break;
863 case 0x33: /* 3DSTATE_URB_GS */
864 switch (dev->gen) {
865 case ILO_GEN(7.5):
866 max_entries = (dev->gt >= 2) ? 640 : 256;
867 break;
868 case ILO_GEN(7):
869 default:
870 max_entries = (dev->gt == 2) ? 320 : 192;
871 break;
872 }
873
874 if (num_entries > max_entries)
875 num_entries = max_entries;
876 break;
877 default:
878 break;
879 }
880
881 ilo_cp_begin(cp, cmd_len);
882 ilo_cp_write(cp, cmd | (cmd_len - 2));
883 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
884 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
885 num_entries);
886 ilo_cp_end(cp);
887 }
888
889 static inline void
890 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
891 int offset, int size, int entry_size,
892 struct ilo_cp *cp)
893 {
894 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
895 }
896
897 static inline void
898 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
899 int offset, int size, int entry_size,
900 struct ilo_cp *cp)
901 {
902 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
903 }
904
905 static inline void
906 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
907 int offset, int size, int entry_size,
908 struct ilo_cp *cp)
909 {
910 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
911 }
912
913 static inline void
914 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
915 int offset, int size, int entry_size,
916 struct ilo_cp *cp)
917 {
918 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
919 }
920
921 static inline void
922 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
923 int subop, int offset, int size,
924 struct ilo_cp *cp)
925 {
926 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
927 const uint8_t cmd_len = 2;
928 int end;
929
930 ILO_GPE_VALID_GEN(dev, 7, 7.5);
931
932 /* VS, HS, DS, GS, and PS variants */
933 assert(subop >= 0x12 && subop <= 0x16);
934
935 /*
936 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
937 *
938 * "(A table that says the maximum size of each constant buffer is
939 * 16KB")
940 *
941 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
942 *
943 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
944 * may not exceed the maximum value of the Constant Buffer Size."
945 *
946 * Thus, the valid range of buffer end is [0KB, 16KB].
947 */
948 end = (offset + size) / 1024;
949 if (end > 16) {
950 assert(!"invalid constant buffer end");
951 end = 16;
952 }
953
954 /* the valid range of buffer offset is [0KB, 15KB] */
955 offset = (offset + 1023) / 1024;
956 if (offset > 15) {
957 assert(!"invalid constant buffer offset");
958 offset = 15;
959 }
960
961 if (offset > end) {
962 assert(!size);
963 offset = end;
964 }
965
966 /* the valid range of buffer size is [0KB, 15KB] */
967 size = end - offset;
968 if (size > 15) {
969 assert(!"invalid constant buffer size");
970 size = 15;
971 }
972
973 ilo_cp_begin(cp, cmd_len);
974 ilo_cp_write(cp, cmd | (cmd_len - 2));
975 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
976 size);
977 ilo_cp_end(cp);
978 }
979
980 static inline void
981 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
982 int offset, int size,
983 struct ilo_cp *cp)
984 {
985 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
986 }
987
988 static inline void
989 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
990 int offset, int size,
991 struct ilo_cp *cp)
992 {
993 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
994 }
995
996 static inline void
997 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
998 int offset, int size,
999 struct ilo_cp *cp)
1000 {
1001 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
1002 }
1003
1004 static inline void
1005 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
1006 int offset, int size,
1007 struct ilo_cp *cp)
1008 {
1009 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
1010 }
1011
1012 static inline void
1013 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
1014 int offset, int size,
1015 struct ilo_cp *cp)
1016 {
1017 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
1018 }
1019
1020 static inline void
1021 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
1022 const struct pipe_stream_output_info *so_info,
1023 struct ilo_cp *cp)
1024 {
1025 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
1026 uint16_t cmd_len;
1027 int buffer_selects, num_entries, i;
1028 uint16_t so_decls[128];
1029
1030 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1031
1032 buffer_selects = 0;
1033 num_entries = 0;
1034
1035 if (so_info) {
1036 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
1037
1038 memset(buffer_offsets, 0, sizeof(buffer_offsets));
1039
1040 for (i = 0; i < so_info->num_outputs; i++) {
1041 unsigned decl, buf, reg, mask;
1042
1043 buf = so_info->output[i].output_buffer;
1044
1045 /* pad with holes */
1046 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
1047 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
1048 int num_dwords;
1049
1050 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1051 if (num_dwords > 4)
1052 num_dwords = 4;
1053
1054 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1055 SO_DECL_HOLE_FLAG |
1056 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1057
1058 so_decls[num_entries++] = decl;
1059 buffer_offsets[buf] += num_dwords;
1060 }
1061
1062 reg = so_info->output[i].register_index;
1063 mask = ((1 << so_info->output[i].num_components) - 1) <<
1064 so_info->output[i].start_component;
1065
1066 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1067 reg << SO_DECL_REGISTER_INDEX_SHIFT |
1068 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1069
1070 so_decls[num_entries++] = decl;
1071 buffer_selects |= 1 << buf;
1072 buffer_offsets[buf] += so_info->output[i].num_components;
1073 }
1074 }
1075
1076 /*
1077 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1078 *
1079 * "Errata: All 128 decls for all four streams must be included
1080 * whenever this command is issued. The "Num Entries [n]" fields still
1081 * contain the actual numbers of valid decls."
1082 *
1083 * Also note that "DWord Length" has 9 bits for this command, and the type
1084 * of cmd_len is thus uint16_t.
1085 */
1086 cmd_len = 2 * 128 + 3;
1087
1088 ilo_cp_begin(cp, cmd_len);
1089 ilo_cp_write(cp, cmd | (cmd_len - 2));
1090 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1091 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1092 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1093 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1094 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1095 0 << SO_NUM_ENTRIES_2_SHIFT |
1096 0 << SO_NUM_ENTRIES_1_SHIFT |
1097 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1098
1099 for (i = 0; i < num_entries; i++) {
1100 ilo_cp_write(cp, so_decls[i]);
1101 ilo_cp_write(cp, 0);
1102 }
1103 for (; i < 128; i++) {
1104 ilo_cp_write(cp, 0);
1105 ilo_cp_write(cp, 0);
1106 }
1107
1108 ilo_cp_end(cp);
1109 }
1110
1111 static inline void
1112 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1113 int index, int base, int stride,
1114 const struct pipe_stream_output_target *so_target,
1115 struct ilo_cp *cp)
1116 {
1117 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1118 const uint8_t cmd_len = 4;
1119 struct ilo_buffer *buf;
1120 int end;
1121
1122 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1123
1124 if (!so_target || !so_target->buffer) {
1125 ilo_cp_begin(cp, cmd_len);
1126 ilo_cp_write(cp, cmd | (cmd_len - 2));
1127 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1128 ilo_cp_write(cp, 0);
1129 ilo_cp_write(cp, 0);
1130 ilo_cp_end(cp);
1131 return;
1132 }
1133
1134 buf = ilo_buffer(so_target->buffer);
1135
1136 /* DWord-aligned */
1137 assert(stride % 4 == 0 && base % 4 == 0);
1138 assert(so_target->buffer_offset % 4 == 0);
1139
1140 stride &= ~3;
1141 base = (base + so_target->buffer_offset) & ~3;
1142 end = (base + so_target->buffer_size) & ~3;
1143
1144 ilo_cp_begin(cp, cmd_len);
1145 ilo_cp_write(cp, cmd | (cmd_len - 2));
1146 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1147 stride);
1148 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1149 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1150 ilo_cp_end(cp);
1151 }
1152
1153 static inline void
1154 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1155 const struct pipe_draw_info *info,
1156 const struct ilo_ib_state *ib,
1157 bool rectlist,
1158 struct ilo_cp *cp)
1159 {
1160 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1161 const uint8_t cmd_len = 7;
1162 const int prim = (rectlist) ?
1163 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1164 const int vb_access = (info->indexed) ?
1165 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1166 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1167 const uint32_t vb_start = info->start +
1168 ((info->indexed) ? ib->draw_start_offset : 0);
1169
1170 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1171
1172 ilo_cp_begin(cp, cmd_len);
1173 ilo_cp_write(cp, cmd | (cmd_len - 2));
1174 ilo_cp_write(cp, vb_access | prim);
1175 ilo_cp_write(cp, info->count);
1176 ilo_cp_write(cp, vb_start);
1177 ilo_cp_write(cp, info->instance_count);
1178 ilo_cp_write(cp, info->start_instance);
1179 ilo_cp_write(cp, info->index_bias);
1180 ilo_cp_end(cp);
1181 }
1182
1183 static inline uint32_t
1184 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1185 const struct ilo_viewport_cso *viewports,
1186 unsigned num_viewports,
1187 struct ilo_cp *cp)
1188 {
1189 const int state_align = 64 / 4;
1190 const int state_len = 16 * num_viewports;
1191 uint32_t state_offset, *dw;
1192 unsigned i;
1193
1194 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1195
1196 /*
1197 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1198 *
1199 * "The viewport-specific state used by both the SF and CL units
1200 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1201 * of which contains the DWords described below. The start of each
1202 * element is spaced 16 DWords apart. The location of first element of
1203 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1204 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1205 */
1206 assert(num_viewports && num_viewports <= 16);
1207
1208 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1209 state_len, state_align, &state_offset);
1210
1211 for (i = 0; i < num_viewports; i++) {
1212 const struct ilo_viewport_cso *vp = &viewports[i];
1213
1214 dw[0] = fui(vp->m00);
1215 dw[1] = fui(vp->m11);
1216 dw[2] = fui(vp->m22);
1217 dw[3] = fui(vp->m30);
1218 dw[4] = fui(vp->m31);
1219 dw[5] = fui(vp->m32);
1220 dw[6] = 0;
1221 dw[7] = 0;
1222 dw[8] = fui(vp->min_gbx);
1223 dw[9] = fui(vp->max_gbx);
1224 dw[10] = fui(vp->min_gby);
1225 dw[11] = fui(vp->max_gby);
1226 dw[12] = 0;
1227 dw[13] = 0;
1228 dw[14] = 0;
1229 dw[15] = 0;
1230
1231 dw += 16;
1232 }
1233
1234 return state_offset;
1235 }
1236
1237 #endif /* ILO_GPE_GEN7_H */